Lithography M
e
t
r
o
l
o
g
y
Optimizing FinFET Structures with Design-based Metrology Tom Vandeweyer, Christie Delvaux, Johan De Backer, and Monique Ercken, IMEC Gian Lorusso, Radhika Jandhyala, Amir Azordegan, Gordon Abbott, and Zeev Kaliblotzky, KLA-Tencor Corporation
Considering the engineering challenges in developing a reliable high-k gate stack that limits leakage current for planar transistors, fin field effect transistor (FinFET) structures may actually be needed at the 65-nm node. The decreasing sizes of FinFETs make it particularly important to obtain good 2D and 3D pattern fidelity in lithography and etching. This article examines characterization of a detailed 2D layout and creation of a complete model of the lithographic process using design-based metrology (DBM). This model can be used for model-based biasing of the FinFET structure. Introduction
The characterization of fin field effect transistor (FinFET) structures, or other two-dimensional (2D) designs, becomes important with the decreasing sizes in future technologies. Robust measuring methods are therefore needed to characterize the changing shape of the structure during the different process steps. A good metrology approach is also important for the creation of robust simulation models. These models predict how a design will be patterned in resist. Some typical concerns for FinFETs that need characterization are: the rounded corner (top-down view); fin width variation through pitch and as function of fin length; line edge roughness (LER); and sidewall roughness. They all have an impact on the performance of the FinFET device. The magnitude of the rounded corner decreases the final length (or, source-drain distance) of the FinFET (Figure 1A). One of the problems stemming from this rounding phenomenon is the significant increase in fin width W when the fin length L is decreasing (Figure 1B). Variation in fin width, due to the rounding of the fin opening, will impact short channel effects. This effect increases for shorter fin lengths.1 As for most structures, critical dimension (CD) variations through pitch (Figure 1C) 6
Spring 2006
Yield Management Solutions
and as a function of fin length are undesirable, because they render the devices non-reliable.1 Since LER and sidewall roughness have an influence on electrical behavior, it’s also important to control them and keep them as low as possible.2,3 (LER and sidewall roughness will not be addressed in this paper). Different methods can be used to reduce some of these effects.4 For example, adding serifs in combination with a conventional illumination, or applying strong off-axis illumination settings, like annular, will reduce the rounding of the corners. But, what will happen with the proximity behavior? The annular exposure setting will deteriorate the fin width variation through pitch, while the effect of using conventional illumination on the through pitch behavior will be smaller. Many variables play a role in the optimization of a 2D pattern, some with a larger effect than others. Two simple exposure settings will be tested in this first case: a conventional one and an annular one (the latter in combination with some basic serif introduction). Since a full characterization of the 2D structure is wanted, design-based metrology (DBM) is introduced to decrease the effort that the creation of the measurement job takes. DBM creates an automatic CD scanning electron microscope (SEM) job with hundreds of sites, starting from the design in GDS format. This development takes approximately one hour, whereas an engineer will spend several hours behind the SEM to create the job manually. DBM is used here in combination with an an off-line measure-