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Yield Management

S O L U T I O N S Yield Enhancement and Process Control Strategies for the Semiconductor Industry

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COVER COVER STORY STORY — — CMP ECHNOLOGY T TRENDS RENDS CMP T TECHNOLOGY

12 VALUATING ALUATING IINSPECTION NSPECTION 12 E EV S STRATEGIES TRATEGIES USING USING A ADV DVANCED ANCED S STATISTICAL TATISTICAL M METHODS ETHODS 33 33 IIMPROVED MPROVED Y YIELD IELD L LEARNING EARNING IN IN CMP CMP

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Yield Management Consulting 12 Evaluating Inspection Strategies Using Advanced Statistical Methods Sample Planner 2 software developed by KLA-Tencor gives critical ability to determine and evolve the optimum inspection strategy through each operational phase.

Analysis 15 Offline ADC Solution Maximizes Inspection Value Automated defect classification used with 7000 series patterned inspection system helps fabs drive up baseline yields.

17 Intelligent Line Monitoring Intelligent line monitoring strategy helps IBM‘s Microelectronics Division accelerate yield learning and improve productivity.

Metrology 21 Replacing C-V Monitoring with Non-Contact COS Charge Analysis Early warning of diffusion furnace contamination with Quantox system helps maintain high yields.

24 Control of HSG-Si Fabrication Using Film and Surface Technologies Film and surface technologies monitor fabrication process of HSG-Si and predict DRAM capacitor performance.

Inspection 28 Wafer Inspection Technology Challenges for ULSI Manufacturing Today’s technology challenges require comprehensive inspection strategies — from detecting, classifying and analyzing defects to recommending corrective action (Part one in a series).

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Photo: Courtesy of SpeedFam-IPEC

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Cover image by Luie Lopez, Stephen Marley Productions

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CMP Technology Trends: From Implementation to Improvement Rapid changes in the semiconductor industry have made CMP one of the most widely accepted planarization methods in IC technology. Long the domain of the electrical or mechanical engineer, CMP has emerged as a complex methodology requiring the expertise of chemists and physicists.

Managing implementation and improvements in CMP will be crucial to the advancement of products in the next millennium.

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33 Improved Yield Learning Using CMP Equipment Monitors Introduction of new CMP monitoring points leads to increased yields at VLSI San Antonio.

50 AIT II In-line Defect Inspection System 2401 Automated Macro Defect Inspection System

36 Automation Comes to Litho Inspection New automated macro defect inspection system detects wide range of defect types frequently missed by manual inspection techniques.

FabVARS 500 Digital Image Management System

Lithography

SEMSpec Random Mode Advanced E-beam Inspection System

38 Low k1 Lithography Redefines Photomask Quality With low k1 lithography, conventional parameters for defining photomask quality are no longer adequate.

41 Analysis of Reticle CD Uniformity with CD SEMs Today’s mask industry needs new metrology technologies to meet current and future CD control requirements.

Standards 46 The Role of Standards In Yield Management Consistent application of metrology standards can help ensure the effective use of yield data.

Sections

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Editorial: The Responsibilities of Leadership

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Business News

News

51 8100XP-R CD SEM Advanced Reticle Metrology System 5300 Overlay Metrology System SL3UV Reticle Contamination Inspection System for DUV Lithography 363UV Reticle Pattern Inspection System for DUV Lithography Yield Management Solutions is published by KLA-Tencor Corporation. To receive Yield Management Solutions contact Corporate Communications at:

KLA-Tencor Adds Quantox and Ultrapointe Acquisitions help KLA-Tencor provide new solutions and broaden range of product offerings.

SEI Level 2 Software Capability Achieved KLA-Tencor is the first semiconductor equipment company to reach Level 2 on the SEI five level SW-CMM. 40 KLA-Tencor Trade Show Calendar 44 Best of YMS MiCRUS Corporation benefits from using KLA-Tencor product monitoring tools at key process points to reveal causes of yield loss.

45 Yield Management Seminar Series

KLA-Tencor Corporation 160 Rio Robles San Jose, CA 95134 Tel 408.875.4200 Fax 408.875.4144 www.kla-tencor.com For literature requests call: 800.450.5308

Š1999 KLA-Tencor Corporation.

All rights reserved. Material may not be reproduced without permission from KLA-Tencor Corporation.

Products in this document are identified by trademarks of their respective companies or organizations.

49 Q & A KLA-Tencor answers questions about the Y2K issue.

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Responsibilities OF Leadership As companies grow and emerge from among their competitors as industry leaders, they must assume new responsibilities in addition to those associated with continued financial success and customer satisfaction. Whether they want to or not, by assuming the rank of “industry leader,” these companies bear an inherent responsibility to truly be leaders.

They have an obligation to learn and understand where the new frontiers will be and to drive the advances in technologies or processes needed to meet future demands.

Their visions further not just their own companies, but the industry as a whole.

EDITOR-IN-CHIEF Roberta Emerson MANAGING EDITOR Judy Dale CONTRIBUTING EDITORS Kern Beare Kavitha Kannan Holly Nielsen Viet Pham A S S O C I AT E E D I T O R Kevin Clover E D I T O R I A L A S S I S TA N T S Rolando Gonzales Carol Johnson Marie Sholar ART DIRECTOR AND PRODUCTION MANAGER Shirley Short D E S I G N C O N S U LTA N T Carlos Hueso C I R C U L AT I O N Cathy Correia

Throughout the history of the semiconductor and equipment industries, the mantle of leadership has been worn by some impressive companies. Unfortunately, those who are leaders in one time can quickly become followers in another. Those companies best positioned to understand the roadmaps of the future, and their implications for today, are also those best positioned to maintain customer satisfaction and a solid revenue stream over the long term.

The dynamic nature of the semiconductor equipment industry makes living up to the leadership role a multifaceted challenge. Not only must the leaders understand and develop solutions for new materials and new methods, such as copper interconnect, low k dielectrics, and new photomask designs, they must also continue to overcome existing challenges in areas such as chemical mechanical planarization, automatic defect classification and yield ramp acceleration. Within this environment of rapid change, where linewidths decrease faster with each new generation of devices, leaders must combine the flexibility and agility of a start up organization with the critical mass of a wellestablished corporation.

Emerging as a leader through revenue growth is indeed a credible achievement.

Maintaining that leadership by recognizing and developing solutions to the coming challenges, by driving advances in current technologies, and by satisfying the needs of customers, both now and in the future, is the true test of a leading company in this or any industry.

KLA-Tencor Worldwide C O R P O R AT E H E A D Q U A R T E R S

KLA-Tencor Corporation 160 Rio Robles San Jose, California 95134 408.875.4200 I N T E R N AT I O N A L O F F I C E S

KLA-Tencor France SARL Evry Cedex, France 011 33 16 936 6969 KLA-Tencor GmbH Munich, Germany 011 49 89 8902 170 KLA-Tencor (Israel) Corporation Migdal Ha’Emek, Israel 011 972 6 6449449 KLA-Tencor Japan Ltd. Yokohama, Japan 011 81 45 335 8200 KLA-Tencor Korea Inc. Seoul, Korea 011 822 41 50552 KLA-Tencor (Malaysia) Sdn. Bhd. Johor Bahru, Malaysia 011 607 557 1946 KLA-Tencor (Singapore) Pte. Ltd. Singapore 011 65 780 1088

Roberta Emerson Vice President, Corporate Communications

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KLA-Tencor Taiwan Branch Hsinchu, Taiwan 011 886 35 335163 KLA-Tencor Limited Wokingham, United Kingdom 011 44 118 936 5700

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Business News KLA-Tencor Adds Quantox and Ultrapointe Synergy in film measurement KLA-Tencor added to its broad range of product offerings with the acquisition of Quantox from Keithley Instruments in November 1998. The acquisition helps KLA-Tencor meet the increasing challenges of monitoring and controlling gate oxides as the semiconductor industry continues to push toward 0.13 µm device technology and beyond.

The Quantox tools monitor charge contamination in dielectrics using a non-contact capacitance voltage (CV) technique without the use of MOS-CAP structures. Monitoring charge contamination is critical in IC manufacturing where failure to do so can result in yield or binning loss, decreased field reliability and increased device failure.

“Quantox tools are the leading contamination monitoring products for materials such as iron and copper. We

also find a very strong synergy between their ability to determine the electrical characteristics of films and the optical measurement capabilities of KLA-Tencor products,” said Gary Bultman, vice president and general manager of KLA-Tencor’s Film and Surface Technology Division.

Enhanced defect review and classification KLA-Tencor acquired the assets of the Ultrapointe subsidiary of Uniphase, including inventory for the Confocal laser Review Station (CRS) product in January 1999. The CRS, which is used to analyze defects on silicon wafers during the semiconductor manufacturing process, has been the market leader in optical defect review for the past two years.

According to Scott Landstrom, vice president and general manager of KLA-Tencor’s Defect Review and Classification Division, “Bringing the

The Quantox System.

system directly into the product portfolio allows us to better focus our resources in supporting CRS customers worldwide.” The CRS system will be linked with KLA-Tencor’s family of other leading inspection products, including IMPACT automatic defect classification (ADC) technology, which has already been adopted by 18 of the top 20 semiconductor manufacturers worldwide.

SEI Level 2 Software Capability Achieved KLA-Tencor reached an important milestone early in 1999, becoming the first semiconductor equipment company to reach Level 2 on the Software Engineering Institute's (SEI) five level Capability Maturity Model for Software (SW-CMM). By working to attain this level, the company's Reticle and Photomask Inspection Division was able to deliver higher quality software on schedule and at lower costs.

An internal survey conducted over the past three years showed that implementing the processes used to reach Level 2 have raised the division's customer satisfaction rate for software

quality nearly 40 percent. According to SEI, a federally funded research and development center sponsored by the U.S. Department of Defense, the SW-CMM has become a defacto standard for assessing and improving software processes. "With the increasing dependence on automated defect inspection and analysis, software quality is becoming a crucial differentiator between systems," said Harvey Wohlwend, program manager for software improvement at SEMATECH.

critical role in helping to meet schedule commitments and reduce the number of software defects reported by customers during beta testing. "Since comprehensive analysis capabilities are key components in KLA-Tencor's yield management solutions, developing software that meets customer needs has been and continues to be one of our critical initiatives across all divisions," said Robert Rubino, chief technical officer for software at KLA-Tencor.

For KLA-Tencor, this progression in software quality has already played a Spring 1999

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CMP TECHNOLOGY TRENDS: IMPLEMENTATION

by Anantha R. Sethuraman, Ph.D., CMP Solutions, KLA-Tencor

Mechanical Polishing C hemical (CMP) has become one of the

most widely-accepted and practiced planarization methods in IC fabrication in less than two decades. The explosive growth of this segment of semiconductor process technology has been remarkable in an industry that has been credited with rapid growth. In an industry that aspires to reach six sigma process control based on scientific first principles, CMP is still being used and developed by artisans. The rigor in the design of experiments held as gospel by the semiconductor industry has not been applied in the development of CMP consumables. After more than ten years of widespread assimilation of this technology, users need an integrated process control solution for their CMP needs. This article discusses some of the history of the maturation of the technology, notes current challenges facing the industry and presents some views on the timeliness of an integrated process control solution for CMP. Current status and emerging trends

When viewed as a process module within a fab, CMP is comprised of a number of elements from a number of different suppliers (see figure 1).1

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Each user assembles a selection of components from this list and integrates the process in manufacture. It is quite likely that each of these components are available from a relatively limited group of vendors who specialize in products unique to CMP which are guarded by high levels of secrecy and intellectual property protection. In contrast, for the more mature sectors such as plasma etch or thin film chemical vapor deposition (CVD), an equipment supplier can more than likely provide the user with the tool, best-known-methods (BKMs), endpoint detection, process consumables, delivery systems and even exhaust treatment systems.

With the broadening of knowledge and expertise in CMP, the technical community is driving towards achieving the maturity level that they have become accustomed to expect in widely accepted processes.

However, due to the consumablespecific nature of CMP itself, the fact remains that all slurries and pads will still be specialty materials, controlled by one or two vendors. By its very nature — its multiple vendors and specialty material requirements — CMP has developed into a niche market technology that demands generous amounts of “black magic” and folklore to achieve success!

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Planarization Equipment Conditioner Endpoint detect Process Slurry Pad Insert Template Slurry delivery Slurry replenishing Slurry recycling Slurry disposal

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Equipment Thickness Uniformity Particles Scratches Defects Electrical quality Setup standards

Figure 1. Elements of a CMP process module. 1

# of Layers Polished

ILD polish Metal polish

1994 (0.8 - 0.5)

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The rapid growth in the use of CMP technology is shown in figure 2.

Between 1994 and 1998, CMP use more than doubled — use of CMP on interlayer dielectrics (ILD) grew from three to five layers, and polishing of metal contacts and the introduction of the damascene process created the need for CMP on metal. For example in a four metal layer process with shallow trench isolation (STI), ILD and tungsten CMP: 15-25 polishers would be needed at 60 percent utilization, with 20 wafers per hour, in a fab with 5000 wafer starts per week.

Furthermore, the extension of CMP to the front-end in order to enable STI integration has triggered the need for innovation. STI has become an architectural requirement for sub0.25 micron device rules, as localized oxidation of silicon (LOCOS) does not deliver the critical transistor properties. The challenge of STI is typically to planarize a high density plasma oxide over silicon nitride.

The objective is to remove the overburden without damaging the nitride excessively, while preserving the integrity of the circuit. Although this is a formidable requirement, it presents a great opportunity. The result has been development of exotically exciting technical solutions in CMP consumables, especially highselectivity slurries. In addition, process solutions using better endpointing have also enabled STI CMP. In the memory area (specifically DRAM), polysilicon polish has been in implementation for about a year.

The volume is expected to increase as more manufacturers adopt poly CMP. Figure 3 describes the evolution of CMP applications in chip manufacture. About two-thirds of the 93 semiconductor fabs producing devices with sub-0.5 micron geometries require some form of CMP. When considered in number of wafer

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starts per week that would need CMP, this number is in the thousands. This implies that the process has emerged as a critical part of the architecture of an integrated circuit and is therefore needed for integrated control of the process to achieve yield goals.

Emerging trends in equipment also support the need. A typical layout of a polishing area in the fab is shown in figure 4. As one can imagine, a wafer fab with more than 10,000 wafer starts per week would have several polishers. Currently each polish and clean tool is intrinsically connected with the input and output device. In the future, a robot will be used to allow two or more polishers to be attached to a single input/output source and a single cleaning station.

This arrangement will optimize tool use and increase processing speed.

The development of the infrastructure needed to support an efficient operation is drawn from all the vendors that supply into the area. Since CMP is a relatively new area for semiconductor manufacture, the expertise on the user side is sparse although growing. Larger organizations such as IBM, Intel, Micron Technology, Motorola and AMD have over the years developed a reasonable methodology to manage the technology. The development of such Application 1st Generation 0.8-0.5 µm

Oxide (ILD)

2nd Generation <0.5 µm

Above + ILD0 W CMP + STI

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Above + Cu, Al & low k CMP + new applications (both FE & BE, e.g.

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methodologies has been evolutionary.

The conventional control that a semiconductor engineer would like to have over the various aspects of the process has not been possible with CMP, primarily due to the continuing and rapid metamorphosis of the process itself.

A history of CMP development

Let us examine a little bit of history.

The chronology described in figure 5 shows the initial rollout of CMP3.

Conceived and developed at IBM under strictest secrecy during the early 1980’s, the process was not well publicized. Vendors who supplied equipment such as IPEC Westech, R. Howard Strasbaugh and process consumable suppliers with pads/carrier films from Rodel and slurry from Cabot were not told the end result of their involvement. This was a typical practice in early semiconductor process development, as intellectual property issues were not well worked out between vendors and chipmakers. The concept of joint development projects (JDPs) between vendors and chipmakers was alien in the era of big company research and development activities. The result was that early understanding of the intricacies of the process rested solely with the users and an infrastructure for development of an ideal solution

CMP

Post-CMP Cleaning

Single Platen/Single Head 1-step polish

Conventional wafer cleaning (wet stations) Wafer scrubbing/DI water

Multi-Platen/Multi-Head 2-step polish (buff step) End-point detection On-board metrology

Wafer scrubbing/DI water NH4OH

Integrated Dry-in/Dry-out Multi-Platen/Multi-Head Non-Rotary (e.g. Orbital, Linear CMP) multi-step polish, End-point detection On-board metrology

Integrated Dry-in/Dry-out Multi-Platen/DIW NH4OH, HF New cleaning methods & New chemistries

trends in CMP applications.

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integrating both equipment and materials was not developed. After all, the concept of polishing a wafer with expensive circuitry that had been developed and manufactured in a clean room environment using “dirty” particle-laden slurry was started as an “experiment”. Given the dramatic shift in thinking required to accept such an idea, there were a multitude of skeptics who did not expect CMP to survive, let alone be where it is today.

As with every breakthrough we have witnessed in the technology sector, what was once deemed improbable, or even impossible, has become a reality and is now accepted as an essential step. Until depth of focus requirements necessitated more stringent planarity as the shift to 0.35 micron devices occurred, CMP was never seriously viewed as a longrange solution. Due to the secrecy with which it was developed, understanding both the power and the challenges of CMP has taken longer to achieve than many other processes in our industry’s history.

Following on the heels of IBM, Intel launched CMP via technology transfer in the 1987-88 timeframe followed by Micron Technology in 1989. The SEMATECH program on CMP was conceived in 1989 and then began the pursuit of rigorous characterization of the process as adoption rose quickly. Member companies dispatched their best talent to collaborate in this “sand box” called SEMATECH. Technical advisory boards were formed and vendors were initiated into the “inner circle”, although again restrictions against disclosing the JDP progress to nonmember companies were imposed in an effort to ensure better return on investment for the member companies. Figure 6 presents the number of process areas that were involved in the CMP sector in 1992 and the increase to date. It depicts a 5-10 Spring 1999

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East Fishkill Base Technology (83) East Fishkill Pilot Line (86) Logic (Oxide, Al) (89) Logic (Oxide, W) (89) Burlington Pilot Line (86) 4MB DRAM (89)

Figure 5. CMP development at IBM.

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times increase in the number of suppliers, each filling a specific need with a tailored solution. These suppliers now vie for nearly a billion dollars in total revenue available today.3 Considering the unusual complexity created by both the very nature of CMP and its idiosyncratic development, an integrated process control solution provider has not emerged.

Figure 6. Growth in the number of CMP vendors to date. 3

Number of CMP Patents Filed

Figure 7. Number of CMP patents filed.

What does the future hold?

With the advent of copper interconnect, the influence of CMP on final yield has increased even more. The success of copper dual damascene interconnect technology lies squarely on the film deposition, CMP and post-CMP clean steps. Along with the enabling characteristics of CMP for copper, there also is a hidden danger. Flaking of copper during or as a result of the CMP process creates defects that might be insignificant in other processes, but are considered “killers” in these highly sensitive applications. The thin layers and multiple levels used in copper interconnect structures will require increased CMP use, yet little is understood about the criticality of the defects seen there. The principal challenge in copper CMP is optimizing copper polish rate with respect to barrier layers (typically Ta or TaN).

Currently this is being achieved by a two or three stage process wherein a new slurry is employed for barrier polish. Although not fully optimized, the challenge has opened doors for technology development.

For this reason, the introduction of copper presents a huge inspection challenge and thereby a valuable opportunity for innovation.

We are currently approaching a point in time when there is a definite need to provide an integrated process control solution for CMP. Copper interconnect and a continuation of the challenges in areas such as shallow trench isolation and other interlayer

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dielectric applications makes control of CMP more critical in achieving appropriate device yield and performance.

What are the core competencies that will be needed in a supplier to win in the integrated process control solution game? To begin with, this highly complex technology will require an understanding of polymer chemistry, colloid chemistry, powder synthesis, electrochemistry, and surface chemistry, none of which are mainstream competencies in an industry that makes electrical devices. So who would be most successful in delivering an integrated process control solution for CMP? The most likely case would be a coalition of capital equipment vendors and consumable vendors who can service the market with all that is needed to run the process. Unlike many other semiconductor processes, CMP is unique in its requirement for both chemical and mechanical superiority, making the coordination of tools and materials considerably more important to a successful effort.

This industry is largely dominated by electrical engineers and, to a certain extent by mechanical engineers, due to equipment needs, so the few chemists or physical sciences engineers available have not been adequate to drive the creation of an integrated solution scenario. Furthermore, the newness of the technology has led to a “rat race” to file patents (figure 7). Propelled by the need to be the “first-to-file” company, most of the users have been unwilling to disclose or “share” the secrets with vendors who might then have been in a position to provide better solutions. This thinking is changing, but it has left a legacy of slow change in its wake.

Only now, as CMP has finally emerged as not just an accepted but an essential practice in the majority

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of fabs, is the industry turning from “implementing” to “improving” the use of this technology. An integrated solution utilizing the best tools, materials and techniques will be critical in achieving the high level of device performance and production yield required for the advanced products of the next millennium.

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1. M.A. Fury, Solid State Technology, April 1995 and July 1995.

2. M. Moinpour, Proc.NCCAVS CMPUG Annual Symposium., 1997.

3. K. A. Perry, VLSI Conference., June 1997.

4. A.R. Sethuraman, Future Fab International, Vol. 5, pp.261, 1998.

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Acknowledgments The author would like to acknowledge the helpful discussions with Mike Fury of Allied Signal, Mansour Moinpour of Intel Corporation and Kathleen Perry of Obsidian Inc. for the theme of this article.

5. A.R. Sethuraman, Proc. of CMP 98, NCCAVS, 1998.

About the Author Anantha Sethuraman has a Ph.D. in Materials Science with a metallization specialization. He is a Senior Director in Corporate Marketing focused on CMP strategy. He has held managerial positions in technology development at Cypress Semiconductor and Rodel Inc. He was involved in the development of CMP technology for several years at Rodel, primarily responsible for slurry and process development for advanced CMP processes. Anantha has published more than 70 papers and holds several patents in CMP technology.

Contact information KLA-Tencor • 160 Rio Robles • San Jose, CA. 95134 Tel 408.875.4374 • Fax 408.875.4144 Email: anantha.sethuraman@kla-tencor.com

FROM THIS

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In R e c o r d Ti m e Add our yield management consulting services to your fab engineering team’s expertise.

And you will see that you’re working with a collaborative enabler. A Consulting Group that provides powerful resources during planning, product transfer, yield ramp and volume production to implement the latest in systematic

and random defect reduction techniques.

Giving you access to proprietary benchmark databases. Yield analysis tools. And sampleplanning software that can provide a critical edge in today’s highly competitive marketplace.

For more information call 408-875-2696 or email YMC@kla-tencor.com

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Evaluating Inspection Strategies Using Advanced Statistical Methods

by Raman K. Nurani, Ph.D., Meryl Stoller, and Dadi Gudmundsson, KLA-Tencor; J. George Shanthikumar, Ph.D., University of California at Berkeley

Increasing fab construction costs, shortening product life cycles and eroding market prices are realities for today’s integrated circuit (IC) manufacturers. In this competitive environment, cost-effective operations are an important part of a successful business plan. High yields have to be reached faster and maintained at lower wafer processing cost levels than ever before.

Towards this goal, optimal capacity of inspection equipment and its allocation across different process steps are imperative, whether it is defect or metrology oriented.

The problem of optimally applying inspection equipment in defect inspection is very complex and only partially addressed1. The problem involves numerous interrelated variables such as the process technology, defect mechanisms, the inspection equipment, fab logistics, processing parameters, and financial data. Making the problem even more complex, the fab’s inspection requirements are not static, they continuously evolve throughout a fab’s operational phases. During the process transfer and yield learning phases, inspection is focused on understanding and improving baseline defect densities, as opposed to focused on excursion control during the mature, full production phase. Defect mechanisms and types also evolve — from a higher content of systematic, process integration related issues during early phases — to more random-related process tool events at the mature, full production phase. Defect excursion types and frequencies, wafer starts, and device average selling prices are just a few of the drivers that evolve and affect the optimum inspection strategy for each phase.

Advanced statistical and stochastic models have been developed to estimate the optimal defect inspection capacity, allocation, and operation (sampling strategy) in fabs.

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based upon these models that uses an unprecedented number of variables to create and optimize a fab-wide inspection strategy. This software program can also be used as a tool for KLA-Tencor’s engineering and development to determine the best inspection technology and configurations for future process technologies.

The sample planning problem

It has become well accepted that defect inspection tools play an important role in a fab’s yield management strategy. While few manufacturers currently operate without some type of defect inspection, many IC manufacturers tend to view inspection as non-value added and are overly conservative when planning inspection capacity. It is here that the sample planning problem arises, i.e. what types of inspections to perform, where to locate them in the process, and how frequently to perform the inspections. The optimum level of inspection is reached through the trade-off between the cost of inspection operations, both fixed and variable, and the cost of yield loss due to undetected yield-limiting defects and process excursions.

The main decision parameters are: type of inspections (test wafer, product, or in-situ inspections), placement of the inspections (which process steps/tools), inspection frequency (percent lots to sample, number of wafers per lot, area per wafer), inspection sensitivity setting, which parameters to track and respond to (statistical process control scheme), the fraction of defects to review, and inspection capacity. All of these parame-

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ters are interrelated and each one gives rise to a set of variables that need to be understood. Overall, the problem is so complex that no comprehensive solution methodologies existed prior to our efforts. The Sample Planner cost model provides the framework and tools to analyze critical fab parameters to develop an optimal inspection strategy with reasonable effort.

The excursion control methodology

In its simplest form, the cost model methodology is based around a recurring in-and-out of control cycle occurring at each step in the process, see figure 2. A cycle starts where each step in the process is assumed to have an in-control mode of operation which delivers a high yield. After a random length of time an excursion takes place, causing lower yields. At this point the inspection sampling strategy determines how quickly the excursion is caught and fixed, restarting the in-and-out of control cycle. The goal is to minimize financial loss by catching the excursions quickly, i.e. minimizing the time between excursion start and detection. However, this needs to be done only for a reasonable inspection cost, which is the essence of the optimization. To do that, modeling mathematically how the process behaves and how the inspection tools “see” the process is the foundation.

The widespread use of a standard statistical process control (SPC) scheme results in accumulation of important data from the processes. We process this data using statistical models and hypothesis tests to Excursion First sample Last sample occurs after excursion before excursion

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Cycle starts

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Source identified

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Output Optimized Sampling Strategy Based Upon • • • • • •

Excursion yield loss/costs Inspection costs Test wafer monitor costs Lots at risk False verification man hours Root cause analysis time

Figure 3. Sample Planner 2 inputs and outputs.

quantify mean and variance of defects during in and out of control states, the propagation of defects to subsequent process steps, the types of excursions and the frequency of excursions. Combining this information with yield and financial data allows the financial loss per year from excursions to be quantified. The financial loss due to excursions can be decreased by sampling more often. To determine the cost of sampling we quantify: equipment sensitivity to defects, inspection tool throughput, inspection tool operation, cost of ownership, and queuing/transit times. A stochastic algorithm uses this information along with the excursion, yield, and financial data to calculate the overall cost. By iterating through several operationally feasible sample plans, the algorithm determines the most cost effective inspection strategy.

Sample Planner 2

A software tool called Sample Planner 2 has been developed based on the above methodology. Sample Planner 2 allows an unprecedented number of critical variables to be involved in sample planning optimization. Besides addressing the decision variables of the sample planning problem mentioned earlier, it incorporates IC manufacturing issues such as, re-entrant flow, rework decisions, and complete process line modeling (300+ steps). The categories of data used by the Sample Planner are five: fab information, inspecSpring 1999

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mine the optimum inspection strategy for all phases of a fab’s life cycle (from new fab planning, through yield ramp and into full production), and 2) by internal KLA-Tencor product development group to help determine the technology and configurations to use when developing inspection tools for future IC manufacturing processes.

An example of the output from Sample Planner 2 analysis performed for a customer is shown in figure 4.

Conclusion

Inspection Sampling Strategy

Figure 4. Example output from Sample Planner 2 analysis.

tion technologies, inspection strategy, baseline defect information, and excursion characteristics. The primary data of interest in these categories can be seen in figure 3. This data is entered into the Sample Planner database through a user friendly graphical interface where the user can outline many different operational scenarios to analyze.

Currently, the Sample Planner 2 software is being utilized in two ways, 1) by KLA-Tencor’s yield management consultants to help customer fabs deter-

The advanced statistical methodology developed by KLA-Tencor has greatly expanded the field of inspection strategy optimization. With its most recent capability, Sample Planner 2 gives users the critical ability to determine and update/ evolve the optimum inspection strategy through each operational phase. This methodology is now being adapted to additional inspection avenues, such as reticle inspection and CD metrology. circle RS#026 1. Nurani, Raman K., Akella, Ram, Strojwas, Andrzej J. “In-line Defect Sampling Methodology in Yield Management: An Integrated Framework”. IEEE Transactions on Semiconductor Manufacturing, vol. 9, No. 4, November 1996.

Singapore Malaysia

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Offline ADC Solution Maximizes Inspection Value

by David L. Goss, Lucent Technologies; Kevin Kan, Prashant Aji, KLA-Tencor

Although the semiconductor manufacturing industry is predominantly utilizing 0.50 µm or smaller design rules, there are currently a number of fabs operating at larger device geometries, some of which have not yet implemented defect classification as part of a defect reduction or yield management program. A standard tool in these fabs, the KLA-Tencor 7000 series patterned wafer inspection system is relied upon to monitor defect levels using total defect counts. Rarely is the defect population optically reviewed to track and analyze defects by type (rather than by count) to monitor their impact on yield. To maximize the value of the 7000 series inspection, however, intelligent classification schemes can be used in conjunction with a fab’s inspection methodology to obtain a great amount of useful data about the types and sources of defects that can then help fabs drive up baseline yield.

Classification of defects allows a fab to trend defects by type rather than by count. When looking at defect counts alone, an operator or engineer may miss a process excursion caused by killer defects, even though the total count is below the defined control limit. The advantage of trending by defect type is that it can detect hidden excursions and provide a basis for defect type baseline reduction efforts. In addition to indicating the possible origin of defects, it enables the characterization and optimization of manufacturing processes, process equipment and inspection recipes, and helps distinguish between killer vs. non-killer or nuisance defects.

Implementing manual defect classification in a fab can prove costly in terms of manpower and training and inherently lacks speed, consistency and high accuracy. Automatic defect classification (ADC), with its fixed cost and automation, thus becomes a very desirable solution. ADC also catches defects that humans may miss and eliminates the variability associ-

ated with human operators, resulting in more accurate classifications that match the capabilities of the fab expert.

Because the 7000 series inspection systems employ oblique angle laser scattering for defect detection, defects are frequently out of the field of view (OFOV) when attempting to review inspection results. The defect positioning inaccuracy of the 7000 series systems thus has been an obstacle to effectively implementing ADC. An ADC solution however, can be implemented on the white-light/laser Confocal Review Station (CRS), KLA-Tencor’s, high-resolution, off-line review tool that is capable of performing offline ADC on wafers inspected by various platforms. KLA-Tencor recently partnered

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intensity defects occurred, virtually all remaining defects from the 7000 scan fell inside the field of view of the CRS at 50x magnification. As shown in figure 2, between 94 and 99 percent of the defects were IFOV, indicating the potential for high classification accuracy.

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The type pareto charts in figure 3 demonstrate good agreement between the expert manual and ADC classification of defects found on the wafers. The overall ADC performance of 80 percent accuracy and 85 percent purity (figure 4) reveals that using the 50x objective for ADC did not result in any loss of classification capability. Results from this study by Lucent Technologies indicate that ADC can be applied successfully to 7000 series inspections and can be an effective part of a fab’s yield management program.

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Figure 2. Defects within the field of view are ADC classifiable after binning of large, high intensity defects.

with Lucent Technologies and successfully demonstrated the use of an ADC solution on the CRS that compensates for the positioning inaccuracy of wafers scanned by 7700 and 7600 inspection systems.

For this study, ADC was conducted using images taken with the 50x objective lens instead of the typical 100x or 150x objectives, and the CRS stage was calibrated to more closely match that of the 7700. For purposes of comparison, five wafers at three levels — poly, metal 1, and base P — were each scanned on a 7700 in two different inspection modes. The wafers were then reviewed and classified, both manually and automatically, on the CRS.

Accuracy Purity

A strong correlation between saturation intensity and large fall-on defects1 allowed the sorting out of saturation intensity defects as a separate class before ADC was performed. Thus, defects out of the field of view at saturation intensity that would have been previously classified as “undetected” could be binned as “large fall-on defects”. Once this screening of large, high-

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over manual classification techniques.

1. Goss, D. et al, “Offline ADC Solution for 7000 Series Inspectors using the CRS”, proceedings of KLA-Tencor Yield Management Solutions Seminar 1998, Austin, Texas.

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Intelligent Line Monitoring Maximum productivity through an integrated and automated strategy

by Tom Pilon, IBM Microelectronics Division; Mark Burns, Verlyn Fischer, Matthew Saunders, KLA-Tencor

Maximizing the number of yielding parts per wafer while minimizing the cost to produce each part is the goal of any semiconductor fabricator. For this reason, considerable investment is placed on ramping yields and protecting them once they mature. The task for the semiconductor industry becomes more challenging as critical dimensions decrease, the number of process steps and their interdependence increase, and as throughput becomes an ever-demanding factor. The result is that as these changes occur in the production environment, yield engineers require larger volumes of intelligently collected data.

They also require the tools to adequately process that data and make responsive changes on the production line to ramp and protect yield.

The industry’s need for greater volumes of intelligently collected defect data is mirrored at the state-of-the-art 0.25 µm technology fabrication facility of IBM’s Microelectronics Division, which produces multiple memory and logic devices across a number of technologies. IBM recognized the need to have a system that would help solve yield problems at a reasonable cost, maximize fab productivity and offer the flexibility to make enhancements with the advances in technology and manufacturing capacity.

KLA-Tencor’s Intelligent Line Monitoring System (ILM) was installed to assess the effectiveness of such an integrated approach to yield management.

What is an intelligent line monitor?

ILM is an integrated set of defect inspection systems, automatic defect classification (ADC) systems, optical review tools, scanning electron microscope (SEM) defect review tools, and a defect database and analysis system (figure 1). An intelligent line monitor is used to monitor and diagnose process excursions, provide information necessary to

Figure 1. Intelligent line monitoring system flow.

ramp yields on new products or technologies, and provide information necessary to predict yields.

As a product flows through the manufacturing line, samples of wafers are pulled, fed into the ILM system, and returned to the production line. As the product travels through the ILM system, wafers are inspected and reviewed. Data are exchanged between the various components in the ILM system.

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Figure 2. Reduction in time spent on classifier training and verification.

software, scanning electron defect review microscopes with automatic defect location (ADL) capabilities such as the Amray 3800, off-line optical defect review stations such as the CRS-1010, 2552 data analysis stations, in-house operational systems, in-house analysis systems, and a Quest defect analysis system.

The fundamental difference between an integrated defect reduction system and a non-integrated tool set is that the integrated system leverages the capabilities of the point products through integration and automation to generate a maximally informative and cost-effective sample (termed as “smart sample”). Such integration helps provide maximum information about only those defects that most detract from yield. This type of sampling strategy provides the greatest impact toward improving chip yields and fabricator productivity.

Because SmartSampling™ is automated by the ILM system, data can be continuously collected as products move through the production line. SmartSampling provides information which allows a line monitoring system to optimally detect process excursions, predict yield, and assist in yield learning. It does this by providing the source, type, and quantity of defects for products and technologies at the various process levels.

Distillation processing is the key feature of an ILM system used to produce a smart sample. It does this by choosing defects on which to collect additional information based on the defects’ potential impact on yield and other current in-line information.

Since the installation of ILM less than a year ago, IBM has reallocated up to 40 percent of its review operators to other work. In addition, time spent on training and verifying classifiers has decreased with the implementation of ADC versus manual classification techniques (figure 2). This occurred because ADC training sets are fixed, whereas human memory and judgment is subjective and varies with each operator’s level of expertise and knowledge of the defect source, defect-kill potential, operator mood, and time during the week or shift.

Furthermore, IBM has recently negated its originally established need to increase their number of manual review stations by 43 percent.

Cycle Time Reduction The ILM solution reduced cycle time in three ways.

First, by decreased defect review times. ADC has been shown to require far less time to classify a defect than manual review (by as much as 66 percent). Second, by decreased queue times. By coupling wafer inspection and optical review, the queue time between these steps was completely eliminated. Queue time is the time wafers sit on a shelf in between the inspection and review steps and has been measured to be as much as 70 minutes (on average) when performing manual review.

Using manual review versus ADC review systems on a defect sample set showed that the time savings with the ADC system were significant (figure 3). Based on a gate-oxide classifier, cycle time was reduced by as much as 67 percent with in-line ADC versus off-line manual review.

The third way cycle time was reduced was with the use of a minimized sample size. While reduction in the time taken to process defects during review is an important contribution to decreased cycle times, the greatest benefit derived with the ILM solution is that the sample set can be smaller yet contain all the critical information. This is important because a sample that is too large and takes too long to measure can cost more in lost production than in lost yield. The ILM solution allows on-the-fly defect filtering, which decreases the impact of doing off-line optical and SEM review on

Improved productivity

Installation of the ILM system at IBM and its ability to intelligently sample the production line generated several measurable productivity improvements:

Reallocation of Resources By automating the optical review process, valuable resources can be reallocated from manual review activities (such as performing review, training, or verification) to other value-added processing tasks or higher-level yield improvement tasks.

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Figure 3. Cycle time for three 8" wafers, with 100 percent coverage, 0.62 µm pixel, and 100 defects classified per wafer.

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The addition of database components to IBMâ&#x20AC;&#x2122;s ILM system, and feature extensions that were made with the addition of ADC as an option to the defect inspector demonstrate the ILM system flexibility. Inspectors here have been matched on three product levels (at two inspection sensitivities each) to 95 percent while ADC systems have matched in the neighborhood of 80 percent on product wafers and up to 97 percent on a defect standard wafer (figure 5). In addition, the means to track and maintain ADC matching has been studied.

Figure 4. Cycle-time reduction based on smart sampling.

Increased Flexibility

ADC classifier extendibility across products and similar process levels for a given technology has limited the set-up time and classifier maintenance duties to ranges acceptable in a manufacturing environment. For example, without classifier extendibility, a fab running two technologies, two products each, and three via levels per product would require 12 classifiers. However, with classifier extendibility, that same fab would need to build only two ADC classifiers. At IBM, classifier extendibility has been shown to reduce classifier creation by 80 percent.

Modular design of the ILM system allows inspection systems to be swapped, feature extensions to be made or a system to be conveniently expanded and enhanced as demanded by shifts in technology and capacity requirements. The benefit of increased flexibility, which is especially important in a manufacturing environment, is improved and protected cycle time.

Component similarity of tools in the ILM system allows the user to run a product interchangeably through similar tools eliminating overheads associated with set-up and extensive recipe management for each individual tool.

Figure 6. Total detection delay for via-level excursion monitoring

total cycle time. This is especially important since SEM defect review is a costly inspection.

Figure 4 shows how the number of defects that are sent for ADC on optical review tools such as the Confocal Review Station and SEM defect review tools such as the Amray is reduced by using smart sampling techniques.

strategies.

For the inspection/ADC components in an ILM system to be interchangeable they must match. Matching requires that defects be identified equally well on one or more inspection tools and that defect classification calls be similar on one or more ADC review systems.

In other words, a lot placed at any inspector/ADC system will generate the same wafer map and review pareto as it would at any other inspector/ADC system.

Yield Protection and Enhancement The time to detect a yield-limiting process excursion is the sum of the beta risk, inspection time, and review time. The beta risk is the time that a process is out-ofcontrol but undetected and depends on a number of parameters, including production rates, line sampling strategy, and defect count statistics.

Data gathered on products at the via levels were used to calculate time-to-detection using manual defect classification (MDC) and ADC techniques (figure 6). The greatest contribution to detection time was the beta risk. In addition, it has been shown that review accuracy has a significant impact in reducing the beta risk contribution. The model that was used to make this calculation was developed by the Competitive Semiconductor Manufacturing (CSM) Automated Inspection Focus Study Research Group.

Figure 5. ADC matching performance.

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The two greatest contributions to the total revenue loss are the beta risk and cost of review (figure 7). Revenue loss due to excursions at the via levels has been reduced by 36 percent with the implementation of the ILM solution.

The solutions for future challenges

Figure 7. Revenue loss per hour for via-level excursion monitoring

The ILM system serves to improve productivity by limiting the number of wafers exposed to yield-limiting conditions, allowing valuable resources to be reallocated to value-added processing tasks and reducing sampling cycle times while maintaining the integrity of the sample data.

strategies.

excursion is the sum of five components. Beta risk is the lost revenue due to product failing because of an out-of-control situation. Inspection cost is associated with the cost to operate an inspection system. Review cost is associated with the cost to perform review. In this model, ADC review cost was rolled into the cost of inspection. Source identification is a measure of the cost to isolate the cause of a measured excursion, and fixing cost is associated with the cost of resolving the yield-limiting problem.

As the ILM solution matures, new features will be added which will further reduce time-to-results. For example adaptive sampling, singular integrated interfaces, central inspection and classifier creation and management, intelligent classifier builds, signature analysis, automated engineering analysis and decision making, parametric analysis, and ADC on SEM and laser-based inspection tools will become standard features necessary to keep pace with the increasing demands of the industry. circle RS#012

New Off-Tool Software Products for Increased Film Measurement Productivity THIN FILM SOFTWARE 2.x WORKSTATION

RECIPE GENERATOR

Off-tool data analysis and recipe management

Automatic waferless recipe creation using basic stepper and reticle database information

GEM/SECS software development and training tool

Recipe generation on a local tool or workstation database

OLSA 1.x Off-line spectral analysis software for recipe development, measurement simulation, and analysis

For more information, circle RS#032 located on the business reply card or call (408) 875-7996.

LAPLINKâ&#x201E;˘ FOR NT Remote control for diagnostics and troubleshooting

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Replacing C-V Monitoring with Non-Contact COS Charge Analysis

by Kelvin Catmull, Richard Cosway, Motorola; Brian Letherer, Greg Horner, KLA-Tencor

Monitoring contamination levels in diffusion furnaces is necessary to ensure that a consistent environment is maintained for the production of semiconductor devices. Due to the large load sizes of diffusion furnaces, there is a potential for significant amounts of scrap if adequate contamination monitoring is not maintained. In addition, a significant amount of product remains at-risk if contamination monitoring is not performed in a timely manner. Clearly, the value of monitor data is greatest immediately after a product run and this value decreases with time.

Poly MOSCAP process vs. in-line

Electrical testing is often used after thermal oxidation as a means of detecting oxide contaminants introduced or activated during processing. It is important, however, to recognize that the degree and type of processing prior to test will influence the type of information received. For instance, the sample preparation necessary to get poly metal oxide silicon capacitors (MOSCAP) wafers ready for capacitance voltage (C-V) testing results in a significant exposure of the test structure to high temperatures.

This process mimics the thermal exposure to full-flow devices, so the C-V electrical test parameters should ostensibly detect oxide problems that will ultimately result in end-of-line test failure. The natural annealing and cleaning action of the process, however, tends to mask true variations in the as-grown oxide quality. From a manufacturing viewpoint, it would be preferable to have an early warning system that flags impending problems before they have reached a critical stage. The standard C-V parameters are still desired, but without the cleaning action inherent in the poly MOSCAP deposition process. A preferred method would be an in-line technique analogous to C-V that does not require MOSCAP processing.

This paper describes one of the first production implementations of such a system,

based on the corona-oxide-semiconductor (COS) technique. To provide a well-known reference for this work, we will concentrate on the sensitivity differences between poly MOSCAP test structures and the COS technology.

COS technology

COS is similar to quasi-static (low frequency) C-V testing. The principal difference is that COS is a non-contact method, whereas C-V requires MOSCAP processing. As in C-V technology, COS analysis requires applying an electrical bias to the sample to measure the oxideâ&#x20AC;&#x2122;s electrical properties. For C-V, this bias is a voltage applied to the MOSCAP through an electrical prober and the response is the measured capacitance. With COS, the bias is applied by charging the oxide surface. The bias, in charge/area, is measured by a coulombmeter attached in series with the chuck.

A typical sweep may bias the surface to create an electric field of Âą1MV/cm2 (the same bias range used in conventional C-V testing). The full sweep is composed of approximately 40 small charge depositions. Two techniques are used to measure the response of the semiconductor after each charge deposition: 1. Surface voltage (Vs) is measured by a noncontact vibrating Kelvin probe. Vs is controlled by the capacitance of the series-connected oxide and silicon.

The oxide capacitance is a constant, while the silicon capacitance has an inherent bias dependence due to the semiconducting nature of the silicon.

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Dit were produced. All samples had 500 ร thermal oxides grown at 1050ยบC on p-type, boron-doped (100) silicon substrates. The following methods were employed to change the characteristics of the thermal oxide intentionally: 1. Photoresist was applied to the surface of the wafer, then ashed off to increase Qm on several wafers.

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Figure 1. Comparison of mobile charge detection following photoresist/ash processing.

near surface region of the silicon. In this case, the probe vibration used to measure Vs is turned off, and a highspeed light flash is used to photo-generate carriers. A voltage spike caused by the temporary collapse of the near surface band bending is capacitively coupled to the motionless sensor and captured by a high speed A/D converter.

2. An O2 flow during the temperature ramp down of a thermal oxidation process was used to increase the fixed oxide charge and density of interface traps. A subsequent forming gas anneal was used to passivate the Si/SiO2 interface.

3. An HCl treatment at elevated temperature was used to remove mobile charge from the surface of the wafers.

The Vfb, Dit and Qm of all the wafers were measured with the Quantox Process Monitoring System, which is based on COS technology. Pairs of wafers were measured

Measurement Fundamentals

Mobile Charge Determination In the COS technique, mobile charge is pushed and pulled across the oxide. An electric field is applied using corona charge. Heat cycles similar to conventional bias temperature stress measurements (200-250ยบC) are performed. The surface voltage drop that occurs during a heat cycle is directly proportional to the amount of mobile charge in the oxide.

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The building blocks described above are used in a repetitive fashion to build a COS data sweep: deposit charge (Q), measure Vs, and measure SPV. The resultant Q, Vs, and SPV curves are analyzed using non-linear curve fitting and a full quasi-static band bending analysis1.

Several oxide electrical parameters (Vfb, Dit, Tox, Qtot, etc.) are extracted during this analysis.

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to verify repeatability. Measurements were made with the Quantox system both before and after exposure to contamination. Split lot experiments were carried out with C-V testing, while control wafers were measured with both techniques.

Experimental

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Photoresist Ashing Measurements made with the Quantox system, both before and after the resist-and-ash and ash-only processes, indicate a significant increase in the amount of Qm, as shown in figure 1, as well as a change in the flatband voltage, shown in figure 2. The data indicate the resistand-ash and ash-only processes deposit significant amounts of mobile charge on the wafer. Assuming a one-micron-thick photoresist deposition, the level of mobile charge is ~0.3 ppb, if it is attributed solely to contamination of the photoresist. A small amount of interface damage, presumably due to the plasma ash, was also detected as a shift in flatband voltage. The

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companion data from C-V measurements did not show a significant change in either of the parameters, indicating a lower sensitivity to this type of contamination and damage.

Oxygen Ramp-Down C-V measurements of the samples cooled in an O2 environment exhibited inconsistent response to a forming gas anneal, as shown in figure 3. One sample showed an increase in Vfb, while a second sample showed a decrease. Dit results, however, were as expected — the forming gas anneal lowered the density of interface traps. The Quantox system’s results, illustrated in figures 3 and 4, show a significant improvement in flatband voltage and interface trap density after the forming gas anneal.

The low sensitivity of poly MOSCAP C-V shown here is apparently due to the processing sequence, rather than a fundamental sensitivity issue for C-V. The poly

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Conclusions

The effective sensitivity of poly MOSCAP C-V testing has been compared with a new non-contact COS technology. While the COS technique is analogous to quasistatic C-V, it has been shown the COS technology is significantly more responsive than poly MOSCAP C-V to variations in oxide contamination. The differences in sensitivity are ascribed to the significant annealing and gettering mechanisms activated during poly MOSCAP processing, and split lot experiments support this hypothesis. circle RS#035

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2. Fung and R.L. Verkuil in A Contactless Alternative to MOS Charge Measurements by Means of a Corona-Oxide-Semicon-ductor (COS) Technique, (Spring Electrochemical Meeting, abstract no. 169, 1988).

Figure 5. SPV-Vs plot showing stretch out due to high D it .

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Control of HSG-Si Fabrication Using Film and Surface Technologies

by Clive Hayzelden, Senior Technical Marketing Manager; Albert Bivas, Technical Marketing Manager; Carlos L. Ygartua, Process Module Manager; Kin-Chung Chan, Senior Applications Engineer; Jason Schneir, Product Marketing Manager

The fabrication of hemispherical-grained silicon (HSG-Si) was developed to increase the surface area of capacitor plates and consequently the storage capacitance of high-density dynamic random access memory (DRAM) devices. The increase in surface area (typically 1.8–2.4 times, as compared with smooth polysilicon electrode plates) is extremely sensitive to processing conditions (e.g., seeding and annealing temperatures). Tight in-line process control is, therefore, essential to obtain high yields.

In this article, a KLA-Tencor UV-1250SE spectroscopic ellipsometer was used to measure both the film thickness and the optical properties of seven HSG-Si films fabricated using a range of seeding and anneal temperatures.

Capacitor fabrication was completed by the deposition of a dielectric film on top of the HSG-Si followed by a top polysilicon electrode. We report a strong linear correlation between the HSG-Si film thickness and the completed device capacitance. Additional insight into the discontinuous surface structure of HSG-Si films was provided by high resolution profilometry using a KLA-Tencor HRP-220.

Wafer fabrication

In a typical fabrication of HSG-Si films, a layer of oxide (SiO2) is first deposited on a crystalline silicon (c-Si) substrate. A capacitor plate (or storage electrode) that consists of a layer of doped amorphous silicon is formed on this oxide by low-pressure chemical vapor deposition. Silicon microcrystals – seeds – are then grown from the gaseous phase on the amorphous silicon layer. The wafer is finally annealed in order to grow the amorphous silicon HSG-Si layer using the seeds as nucleation sites. During the 24

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annealing process, which occurs under high vacuum, the HSG-Si seeds grow at the expense of the underlying amorphous Si layer to yield the characteristically rough surface. During annealing, the amorphous Si layer becomes partially crystallized (and is hereafter referred to as polysilicon).

HSG surface topography and film parameters

The cross-section of a typical HSG-Si film stack is represented schematically in figure 1. The HSG-Si layer is composed of islands or “grains” of silicon, and can be described by the mean grain diameter, height and the number of grains per unit surface area. The underlying polysilicon layer is assumed to be smooth.

Figure 2 is a topographic image obtained from an HSG-Si wafer using the profilometer. The area analyzed is 1 x 1 µm2. The maximum grain height is approximately 1000 Å.

HSG-Si Silicon (poly/amorphous) Oxide Silicon (crystaline) Figure 1. Schematic: cross-section of a typical HSG-Si film stack.

F For typical film stacks – composed of homogeneous layers with smooth interfaces – the optical parameters of a film layer are the thickness, t, the refractive index,

Figure 2. Topographic image obtained from an HSG-Si wafer using an HRP-220.

n, and the extinction coefficient, k. The parameters for the film substrate are its refractive index and extinction coefficient. Since n and k depend on the wavelength in a way that is characteristic of the material (a property known as dispersion), it is important to measure the optical properties of the film stack over a broad wavelength range. The UV-1250SE uses broadband light in the wavelength range 240-800 nm.

Spectroscopic ellipsometry (SE) measures the polarization of the light reflected from the surface of a wafer.

This technique has been widely adopted for the nondestructive determination of the thickness and optical parameters of both single- and multi-layer thin film stacks.

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The SE optical path is represented schematically in figure 3. The wafer is illuminated using linearly polarized light at a large angle of incidence. The reflected light is elliptically polarized and its polarization state is analyzed over a selected wavelength range. In this analysis we utilized the wavelength range 320-800 nm. This wavelength range included spectral information from the n and k peaks at 372 nm, while avoiding the effects of scattering and absorption by the HSG-Si layer in the deeper part of the ultra-violet part of the spectrum.

The SE measurement provides the experimental spectra, tanΨe(λ) and cos∆e(λ). Theoretical ellipsometry equations, tanΨt(λ) and cos∆t(λ), represent the expected reflected light polarization for a given set of film stack parameters.

TanΨ and cos∆ are derived from the complex electrical field reflection coefficients, Rp and Rs, of the p and s polarization components of the reflected light, and from the phase difference, ∆, between these two components by the equation: Rp tanΨe • exp(i∆) = (1) cos∆ = Re (exp(i∆)) Rs The quality of the spectral fit (goodness of fit or GOF) based upon the difference between these spectra is provided by the system.

Because the HSG-Si layer is discontinuous, the spectroscopic ellipsometric analysis reports “effective” values of t, n and k for this layer. For the polysilicon layer, both the thickness and degree of crystallinity were determined.

Spectroscopic ellipsometry

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Polysilicon

Polysilicon HSG Figure 4. Schematic: deposition of a dielectric layer and polysilicon top electrode on HSG-Si.

Dispersion models

A good fit between experimental and theoretical spectra requires knowing or calculating the values of n and k at all the individual wavelengths in the spectra. As this is not practically possible, continuous approximation models – with a limited number of variables – are developed to describe the dispersion of the different materials that constitute the film stack. During the calculations, n and k are fitted at the same time as the film thickness until the best fit is obtained.

Figure 3. Spectroscopic ellipsometr y optical path schematic.

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variable parameters. The thickness of the oxide was fixed at 1000 Å. A standard n and k table, with no variable parameters, was used for the Si substrate.

Results

We analyzed each of the seven wafers at five sites using SE. The thicknesses of the HSG-Si layer and underlying polysilicon layer were calculated, along with the crystallinity of the polysilicon. After the optical measurements, the wafers were processed further to create capacitors by first depositing a dielectric layer then a polysilicon top electrode on top of the HSG-Si (shown schematically in figure 4). The capacitance was then measured at the same sites that were characterized using SE. An example of tanΨ(λ) and cos∆(λ) spectra for one of the HSG-Si wafers (wafer #3 at site #1) is presented in figure 5. The corresponding dispersion plots for n and k are shown in figure 6.

The calculation method and dispersion models worked well for the entire range of process conditions and the results are summarized in table 1.

Table 1 shows the average capacitance enhancement values (i.e., the ratio of the capacitance with an HSG-Si layer to that of capacitors with a flat electrode). A linear correlation (>95 percent), with a reasonable sensitivity (slope), was found between the HSG-Si thickness and the capacitance enhancement, as shown in figure 7. The calculated percentages of amorphous silicon and voids in the polysilicon layer indicate that this layer was approximately 80 percent crystallized during the growth of HSG-Si. It was also found that wafer #6 had been misprocessed as evidenced by abnormal polysilicon thickness, crystallinity and optical properties.

Figure 5. TanΨ(λ) and cos∆(λ) spectra for an HSG-Si wafer.

electron acted upon by an electromagnetic field. This model was used to represent the effective dispersion of the HSG-Si. The Bruggeman effective medium approximation (BEMA) model represents the film material as a mixture of several components, each defined by a table of n and k values as a function of wavelength. In the calculations, the volume fraction of each component in the mixture is obtained. This model, which combined amorphous Si, crystalline Si and voids, was used to represent the polysilicon layer and account for a wide range of crystallinity.

Conclusion

The thermal silicon dioxide beneath the polysilicon was modeled using a standard n and k table, with no

The characterization of HSG-Si wafers is particularly challenging because the top layer is a rough and discontinuous film with a large sensitivity to process changes.

wafer

HSG t(Å)

1 2 3 4 5 6 7

501.6 362.8 498.2 313.1 448.0 521.5 475.3

HSG Polysilicon n@633 nm t(Å) 2.059 1.913 2.159 1.953 1.904 2.036 1.944

1031.2 1041.3 1037.3 1049.9 1053.5 883.6 1037.2

Polysilicon n@633 nm

Polysilicon % crystallinity

Goodness of fit

Capacitance enhancement

3.488 3.626 3.436 3.676 3.501 4.299 3.534

0.799 0.802 0.786 0.789 0.827 0.578 0.807

0.9814 0.9829 0.9830 0.9840 0.9753 0.9806 0.9803

2.120 1.570 2.102 1.473 1.937 2.032 1.958

Table 1. Summar y of spectroscopic ellipsometr y results for the HSG-Si, underlying polysilicon layer, and capacitance enhancement values for the seven wafers.

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Figure 7. Linear correlation between HSG-Si thickness and the capacitance enhancement.

Figure 6. Dispersion plots for n and k for HSG-Si.

High resolution profilometry is able to assess grain size and spatial distribution of the grains. In this study we demonstrated that spectroscopic ellipsometry can be used to characterize both the HSG-Si and underlying polysilicon layers. A direct correlation between the thickness of the HSG-Si layer and the capacitance enhancement of the fabricated devices was shown. The degree of crystallinity of the bottom electrode was about 80 percent. These two results can be used in production to monitor the fabrication process and to predict DRAM capacitor performance. circle RS#002 + 005

HIGH RESOLUTION PROFILER SERIES

KLA-Tencor’s High Resolution Profiler (HRP) Series was recently honored with Semiconductor International magazine’s “Editors’ Choice Best Product” award for 1998. Nominations for this award are submitted to Semiconductor International by customers.

The HRP has been delivered to the top semiconductor manufacturers for advanced CMP development and production, including copper programs. With this broad installed base, KLA-Tencor continues to offer fieldproven surface metrology solutions.

Visit our website at www.kla-tencor.com, or call 408-875-2098. circle RS#005

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Wafer Inspection Technology Challenges for ULSI Manufacturing–Part I

by Stan Stokowski, Ph.D., Chief Scientist; Mehdi Vaez-Iravani, Ph.D., Principal Research Scientist

Evolution of the semiconductor manufacturing industry is placing ever greater demands on yield management and in particular, on metrology and inspection systems. As critical dimensions shrink to 0.13 µm and 0.10 µm in the near future and wafer sizes increase from 200 mm to 300 mm, economics will drive the industry to decrease the time for achieving high-yield, high-value production. Continued pressure to increase the return-on-investment for the semiconductor fabricator has made it critical for inspection systems to evolve from stand-alone “tools” that just find defects to being a part of a more complete solution where detecting defects, classifying them, analyzing these results and recommending corrective action are their functions.(Part one of two) To understand how inspection systems will meet the requirements of manufacturing integrated circuits with smaller structures on larger wafers in the future, we need to consider some of the basic physics, engineering, and economic constraints imposed on these systems.

Physics: To inspect an object we look at it via some interrogating means, which are usually photons or electrons scattered by the object.

The detected scattered photons or electrons as a function of position (an image) hopefully contain the information needed to determine whether a defect is present. An image processing system then decides if there is a defect. Thus, defect detection naturally consists of three main steps: first, obtaining the image, second, processing the image, and third, applying criteria to this processed image to detect defects.

It is interesting to compare inspection technology with that of lithography, in particular, the exposure process. Lithography is almost exclusively optical [I-line (365 nm wavelength), deep ultraviolet (DUV, 248 nm), 193 nm, and eventually extreme ultraviolet (EUV, 13 nm)]. The print rate of optical lithography is now about 1010 resolution elements per second and is increasing to 1011 28

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over the next few years. This high print rate is a consequence of the massive parallelism of optical techniques.

On the other hand, the highest inspection rate currently is 6 x 108 pixels per sec. However, optical lithography has an easier task in that it does not have to process and analyze an image.

The challenge for inspection tools is then to detect small defects with a system resolution spot size much larger than the defect size. Fortunately, one does not have to “resolve” a defect in order to detect it.

Resolution, appropriately, does impact defect classification and identification. However, even for performing these functions, we can sometimes obtain sufficient information without necessarily “resolving” the defect.

Even the first step of obtaining the image, by its nature, includes an optical processing step. How we illuminate and collect the resultant scattered light determines the contrast between a defect and the background in which it resides (surface or pattern scattering). Ideally one wants to maximize this contrast by carefully choosing the optical arrangement. Fortunately, there are tools and techniques for accomplishing this choice, some of which are described here. In addition, for periodic array cells optical spatial filtering is effective. Finally, light polarization plays an extremely important role in enhancing sensitivity.

This article focuses on optical techniques for wafer inspection because they are most commonly used.

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Brightfield and darkfield systems

All optical inspection systems depend on photon scattering from the inspected object. Brightfield systems collect both the scattered and reflected light through the same aperture to obtain an image. In addition, the object is illuminated through the objective aperture.

Basically, these systems are a high-speed microscope.

Darkfield systems, on the other hand, only collect the scattered light; no part of the reflected light falls within the collection angle. They can have a multiplicity of configurations, depending on the angle and type of illumination, collection angles, and detector type.

Both these systems have their advantages and disadvantages for detecting different defect types. In general, darkfield systems are particularly useful when the defect has some high-spatial-frequency topography, whereas brightfield is good at finding planar defects. In most cases darkfield systems find defects much smaller than the system resolution or spot size; whereas, in brightfield systems the detected defects are about the same size as the system resolution. This fact has important implications for system throughput. Of particular importance for system sensitivity, however, is the fact that no one optical arrangement is optimal for detecting all possible defect types.

Particle scattering

Particles or their effects are the source of a majority of defects in ICs. Thus, understanding particle scattering helps to design sensitive inspection tools. KLA-Tencor’s proprietary application software that calculates the polarized scattering from a sphere into the 2π hemisphere above the substrate was used to calculate the scattering patterns described in this article, unless otherwise stated.

Figure 1 shows our definition of the spherical coordinates used in discussing scattering from particles, surfaces and defects. The polar angle is defined from the surface normal and the azimuthal angle counterclockwise from the reflected beam projected onto the surface plane. The illumination polarization definitions Surface Normal Incident Light (i) Incidence Plane

Ep

Ep(s)

0i

Scattered Light (s)

0s

Es(s) Scattering Plane

Es

Reflected Light

οs

Figure 1. Diagram for coordinate and polarization definitions.

Figure 2. Scattered intensity patterns of PSL spheres on silicon as a function of diameter, polarization, and incidence angle. The 488 nm plane wave comes in from the left at 70° incidence and view is about –90° in azimuth from the incidence plane. The last column of images is for normal incidence, circular polarization. The numbers correspond to the peak differential cross sections and the total integrated cross sections in µm 2 divided by the cosine of the incidence angle.

are s (E perpendicular to the incidence plane) and p (E parallel to the incidence plane). The scattered field polarization is s or p relative to the plane containing the surface normal and the scattered light direction. To understand some of the basic scattering rules, we start with a polystyrene latex sphere (PSL) on silicon.

Although PSL spheres are not found in IC fabs, they are convenient for calibrating inspection systems because they are spheres of known diameter.

Figure 2 shows scattering from PSL spheres as a function of diameter, polarization, and angle of incidence.

Of particular interest is the advantage of using p-polarized light for detecting small particles. The total scattering cross section for a 60 nm PSL sphere with p-polarized illumination at 70º incident angle is 86 times that with s-polarized light and 42 times that with normal incidence. Also note that most of the scattered light under oblique p-polarized illumination is in the polar angular range of 20º to 70º. Thus, an optimum system for detecting small particles uses obliquely incident p-polarized light and collects the scattered light over a large solid angle, 20º to 70º in polar angle and almost 360º in azimuth.

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Figure 5. Total integrated scattering cross sections for PSL (dotted line), silicon (solid line), and aluminum (dashed line) spheres on silicon.

Figure 3. Magnitude of the electric field as a function of distance above a silicon surface for s-polarization (solid line) and p-polarization (dashed line) for 70° incidence and an input field amplitude of 1.

fields above a surface. We can best describe this effect by realizing that for a small enough particle, the particle acts as a probe of the near field because the far-field scattering depends on the E-M field present at the particle. If the particle is small enough, it does not substantially perturb the field that would be present in the absence of the particle.

For 70º incidence figure 3 shows the electric field as a function of distance above a silicon surface for s- and ppolarization. Note that s-polarized light has a low field

Figure 4. Scattering model calculations agree with measurements for PSL spheres on silicon with 70° incidence angle, s-polarization

where d is the sphere diameter, λ is the illuminating wavelength, n is the refractive index of the sphere and E is the electric field at the sphere. Thus, higher refractive index materials, such as semiconductors and metals, scatter more light. Figure 5 compares the total integrated scattering (TIS) for PSL, silicon, and aluminum spheres on silicon. As a consequence, if a system can detect 60 nm PSL spheres on silicon, it can detect 40 nm aluminum spheres on silicon.

Particle sizing is always of interest. Typically the industry uses PSL spheres as a calibration standard. If an inspection system uses the total scattered light intensity as an indication of particle size, figure 4 reveals a problem: the intensity is not a monotonic function of the sphere diameter (oblique incidence has less of a problem than normal incidence). Furthermore, the scattered intensity from spheres of other materials obviously does not relate in a simple fashion to the PSL sphere response unless one compares the curves for sphere diameters less than 100 nm. To obtain better sizing one needs to use more than one configuration or mode as suggested, for example, by the responses shown in figure 4.

(squares) and p-polarization (triangles), and normal incidence (diamonds). The collector covers the polar angles from about 25° to

Surface scattering

72° and nearly 360° in azimuth.

For unpatterned wafers the background noise comes from surface scattering. We will only describe here the key parameters that determine surface scattering.

at the surface (“dark fringe”), whereas, p-polarized light is at a maximum. It follows then that small particle scattering is greatest for p-polarization.

Experimental results confirm the utility of the scattering model. For example, figure 4 shows the agreement between measurements and modeling results as a function of incidence angle and polarization.

The sensitivity of an inspection system for small particle detection depends on the particle material. In the Rayleigh limit the total integrated scattering of a sphere in a medium depends on d6 λ4 30

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For surfaces that are rough, but with height variations much less than the light wavelength, the scattered power per unit solid angle as a function of the polar angle and azimuth is: (2) dP 16π 2 = Pi • 4 • [cos (θi) • cos2 (θs) • Qp, q (θi,θs,φs)] • PSD(fx, fy) dΩ λ where Pi is the input power, dΩ is the differential solid angle, θi, θs, φs are defined in figure 1, Qij(θi, θs, φs ) is the polarization factor and PSD(fx, fy) is the power spectral density of the surface height variation as a

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function of the x and y components of the surface spatial frequency (1). The frequency components, fx and fy, are, in turn, related to the scattering angles through the diffraction equations.

Once the surface PSD characteristic is known, we can calculate, to a good approximation, the angular distribution of the light scattered by the surface.

Figure 7. Schematic illustrating the differ-

Obviously, one tries to minimize surface scattering to obtain good defect sensitivity on rough surfaces. Of particular importance is the polarization factor of equation 2. Figure 6 shows the variation of this factor for silicon over the full scattering hemisphere for the four combinations of input and scattered polarizations and 70º incidence. To minimize surface scattering, using the ss polarization combination and collecting light in the vicinity of 90º and 270º azimuth is very effective.

In addition, depending on the underlying material, the pp polarization combination and collecting scattered light in the forward direction is useful.

In equation 2 we can also see that the cos(θi) and cos2(θs) terms also imply that greater sensitivity to detecting particles is obtained in the double darkfield configuration, where both angles are >45º.

Figure 6.

Relative magnitudes of the optical polarization factors

Q i , j .cos 2 (θ) for 70° incidence on silicon: ss, pp, sp, and ps polarization combinations over the scattering hemisphere. (Gray scale converted from color: bright band contour is 0.5 of the maximum.) The 488-nm plane wave comes in from the left; view is near –90° in azimuth from the incidence plane.

Unpatterned inspection systems measure the background scattering level, which the industry refers to as “haze”. The measured haze value obviously depends on where in the hemisphere we collect the scattered light.

Obviously haze is related to the PSD characteristics of a surface, but the relationship is not necessarily a simple one.

Pit scattering

Pits are of great interest to silicon wafer manufacturers.

Pits have been a problem for inspection systems because they also scatter light and are indistinguish-

ence between particles and pits relative to the illumination incidence angle.

able from particles in a single channel detection system. The wafer manufacturers need to classify pits and particles on silicon wafers. Pits are octahedral voids in Czochralski-grown silicon that have been exposed at the surface by the polishing process. They are also known as crystal-originated particles (COP), obviously a misnomer. They sometimes are a single pit and, in a large number of cases, partially overlapping double pits.

Pits and scratches are “surface-breaking” defects; i.e., they are into the surface. The scattering characteristics, therefore, of pits and particles are different and as a consequence, we can classify detected defects as pits or particles if we have information from multiple channels or modes.

The first difference between pits and particles comes from their responses to normal and oblique illumination. Figure 7 is a simple illustration of this difference.

Part (a) shows the normal illumination with a sphere on a surface intercepting a cross section of the beam.

Part (b) is the condition for an oblique beam where the illuminated area on the surface is the same as in part (a). Note that in this plane the same-sized sphere intercepts a larger fraction of the incident beam cross section. Thus, a sphere will scatter significantly more with oblique incidence (see figure 2). Part (c), however, shows that with oblique incidence a pit is at a significant disadvantage relative to a sphere on the surface for scattering light. Thus, comparing the scattered light in normal and oblique incidence can help classify pits and particles.

A more important difference between pits and particles is the angular pattern of the scattering. Both theoretical calculations and experimental results show that particles scatter light principally into the polar angle range from 20º to 70º when illuminated with p-polarized light. In contrast, pits scatter primarily toward the Spring 1999

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Scratches also scatter primarily toward the normal, similar to pits. Furthermore, for uniformly detecting scratches of any orientation, normal incidence is preferred.

Dielectric film effects

Figure 8. Signal levels of PSL spheres and silicon pits with about 25° to 72° collection vs. about 6° to 20° collection, shows superior classification of pits and particles using oblique incidence.

normal; therefore, comparing the light scattered into higher angles with those toward the normal will also classify pits and particles. Even for normal incidence this separation works; however, oblique incidence works best. We show experimental results for the p-polarized oblique incidence case are shown in figure 8.

Scratch scattering

Scratches are important in CMP processes and may be yield-limiting. Scratches preferentially scatter perpendicular to their long dimension. Real scratches are not perfect linear defects; in many cases they have cross-sectional variations along the scratch, may have particulate debris nearby, and commonly are “chatter marks.” These “chatter marks” or “micro-scratches” actually are a series of short small scratches along a line perpendicular to the long dimension of the scratches.

On patterned wafers, dielectric films are present. These lead to a couple of complications. One is the interference effect that produces color under broad band illumination and contrast variation under monochromatic illumination. These effects are particularly troublesome if the film thickness is not uniform, and one is trying to do a die-to-die comparison. In brightfield systems broad-band illumination has helped. In darkfield systems circularly polarized light is extremely useful in minimizing the film effect.

As a simple example, the scattering cross section of a PSL sphere on silicon dioxide on aluminum as a function of the oxide thickness is shown in figure 9. Note the substantial variations of total scattered light with film thickness with both s- and p-polarization with oblique incidence. However, because the s and p scattering are out-of-phase with respect to each other, scattering with circular polarization, which has both, is much less affected by film non-uniformity. For normal incidence, s, p, and circular are all equivalent and the film effect is worse than that seen with oblique incidence.

Digs and scratch detection will also be affected by dielectric film thickness and polarization, but their variation in scattering is not in phase with the particle scattered intensity.

Previous layer defects

One may or may not want to see previous layer defects, depending on the system application. Usually, while monitoring equipment one does not want to see down into the previous layers. Oblique illumination with s polarization has much less penetration of energy through transparent dielectrics than normal illumination and thus is preferred for detecting current layer defects.

Figure 9. Scattered intensity for a 100 nm PSL sphere and a 250 nm PSL sphere on silicon dioxide on aluminum as a function of oxide thickness and input polarization, p-polarization (long dash), s-polarization (short dash), and circular polarization (solid). Scattered light collected from about 25° to 72° polar angle.

Part II of this article addresses System Considerations to Meet the Design Shrink Challenge and Future Needs and Developments in Wafer Inspection Technology and will appear in the next issue. To view the whole article, you may also request an advance copy through the BRC or visit our website at www.kla-tencor.com/corpmag.

1. Church, E.L., Jenkinson, H.A., Zavada, J.M., Opt. Eng. 18, 125-138 (1979)

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Improved Yield Learning Using CMP Equipment Monitors

by Scott Hiemke, Dean Spaugh, John Givens, Albert Liu, Miguel Delgado, VLSI San Antonio; Rebecca Howland Pinto, Ph.D., KLA-Tencor

When a new line monitoring point is introduced into a manufacturing line within a fab, it must be justified. This justification process involves careful experimentation to determine that process excursions are occurring at these points which have significant impact on yield. It involves verification that inspection and metrology tools are optimized to identify the relevant excursions, and it involves bringing together people from several different groups within the fab to cooperate on the solution. Finally, the solution must be implemented on the manufacturing line.

CMP defects by polarization

CMP defects by sensitivity

CMP defects

CMP defects

At VLSI San Antonio, new inspection points were introduced to monitor intermetallic oxide (IMO) chemical mechanical polish (CMP) layers, and tungsten CMP (WCMP) layers. A combination of defect monitoring using the AIT, defect review using the CRS and JEOL SEM stations, and analysis using Quest produced information that led VLSI to make changes to the way their CMP scrubbers and polishers are utilized. These changes provided significant benefit to the yield learning rate at the San Antonio facility.

cn

pn

sn

high

Polarization

low Sensitivity

Figure 1. A combination of s input polarization and high sensitivity set-

Introducing a new inspection point

The process that VLSI used for determining whether a new inspection point should be introduced for post-CMP layers was comprised of several steps. First, the defect group characterized the proposed line monitor point. This involved setting up recipes on the AIT, and going through various combinations of polarizations and sensitivity settings to determine which setup provided the best capture of defects. In the case of CMP layers, success meant capturing the largest number of microscratches, shallow scratches, gouging and slurry residues while minimizing false counts. The defect group

tings on the AIT provided best capture of defects on CMP layers.

found that s-polarization and high sensitivity provided the best results, especially in open areas of low pattern density (figure 1).

The second step of the process involved collecting data from the manufacturing line at that inspection point, to establish a baseline and determine what impact these defects had on yield. Analysis of the data indicated that defects introduced at the CMP steps produce a high potential for die loss. Based on this information, a team was formed to address the CMP processes as a source of high yield impact.

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STD scrub process

Defect detected at WCMP1 Defect from Old Scrub Recipe Figure 2. Introducing a new scrub process made an immediate, positive impact on defectivity.

The team and its charter

The team’s charter was to optimize the CMP processes: specifically, to minimize defects introduced at CMP steps, and maximize true up-time of the CMP polishers.

VLSI set goals and deliverables for the project, and set limitations on allowable methods for addressing the problems. For example, existing CMP consumables (pads and slurries) and equipment had to be utilized.

Defect inspection and film thickness measurements were the chief techniques employed to attack the problem.

The interdepartmental team, comprised of process engineers from the defect group, CMP engineering and CMP manufacturing, discovered that the first step towards solution of the problem was to establish a control action system. This system is represented by a flow chart that documents ownership for each step of the decision of what to do with out-of-control lots. The process of documenting responsibility through the control action system proved invaluable in making progress towards the goals of the project.

The culprits

Defect detected at IMO2CMP Figure 3. Examples of defects detected after WCMP and after IMOCMP.

nine lots through the process flow, measuring film thickness and defectivity after each CMP step. The AIT was particularly well suited to this application, because its high throughput meant that every wafer in the lot could be scanned to enable characterization of wafer-towafer variation. Examples of defects found after WCMP and after IMOCMP are given in figure 3. Note that several defect types were captured well in areas of dense pattern.

Following the defect inspection, the wafers were measured on the UV-1280SE to characterize the variation

The second area investigated was the nonuniformity of the oxide layer after CMP. The team followed a set of

Figure 4. Film thickness measurements (using the UV-1280SE) showed

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Film Thickness

Once the control action system was in place, the team began its investigation by examining the effectiveness of the post-CMP scrub. They discovered that changing the scrub process significantly reduced the number of defects left on the wafer. A comparison of the new and old scrub processes is given in figure 2, along with examples of defects found after scrubbing. Introducing the new scrub process made an immediate, positive impact on defectivity.

Site on the Wafer

a domed oxide profile, which negatively affected edge die yield.

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Figure 5. Introduction of a line monitoring point helped trace defect excursions to a faulty drum of slurry and wear and tear of a polishing pad.

in oxide thickness across the wafer (figure 4). The film thickness measurements showed that the oxide profile was domed, and as a result, edge die yield was negatively affected. This prompted the team to recommend tightening the specifications for post-CMP oxide uniformity.

Transfer to manufacturing

The last part of the team’s responsibility was to transfer the improved process to manufacturing. This meant that the AIT had to be interfaced to PROMIS, VLSI’s Work In Progress (WIP) tracking system. Fortunately, more than 90 percent of the GEM/SECS code written originally for the Surfscan 7700 was transferable to the AIT. This ensured that the correct lot numbers, process levels, recipes and data were being sent to Quest and transferred to VLSI’s SPC system.

The line monitor was set up to monitor WIP in the queue for a tool, and skip lots past the inspection steps if more than a certain number of lots are waiting, or if a recipe is missing. As a result of this setup, more than 60 percent of the total volume are currently inspected post-CMP by scanning lots across 10 to 12 part types.

In addition, over 50 percent of the other process layers are inspected on the AIT. At VLSI San Antonio, over 19 process layers throughout the line are inspected by the AIT. The final step in transferring the process to manufacturing involved training the CMP engineers and manufacturing personnel to use Quest and the various review stations at their disposal.

The learning continued

Once the improved process was successfully transferred to manufacturing, some other important discoveries were made. One defectivity excursion at oxide CMP was traced to a change in a drum of slurry, when the lines had been improperly flushed out (figure 5).

Figure 6. Examples of defects found at a shallow trench isolation (STI) CMP layer.

CMP Manufacturing decided to change the pads more frequently: three times more often to reduce the defect levels. Introducing this inspection point has resulted in a dramatic change in the way maintenance is done on the CMP polishers in this facility.

Faster yield learning now and in the future

Since implementing the line monitoring methodology described above, VLSI San Antonio has increased their yield learning rate. A better yield learning rate translates directly into higher profitability for the fab.

Because of this success on their current products, VLSI San Antonio also elected to add an inspection point to their below-0.25 µm development work, at shallowtrench isolation CMP (figure 6).

This paper is largely derived from a presentation first given in July 1998 at the Yield Management Solutions Seminar during SEMICON/West.

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Automation Comes to Litho Inspection

by Alexander E. Braun, Associate Editor, Semiconductor International

Automated defect inspection and control strategies are commonplace across fabs, except for the litho cell. Because many litho process defects are relatively large, applicable solutions are limited. For example, the cost-of-ownership of using highly sensitive inspection systems utilized in other process steps often cannot be justified. Anyway, litho error detection requires a system that can be tuned to detect defect types with a wide range of characteristics.

Since over 75 percent of yield-relevant defect types are fairly large and visible to the eye, macro after-develop inspection (MADI) traditionally has been a manual, operator-intensive process. Fabs rely mostly on manual visual inspection to determine whether a wafer passes (to further processing), is reworked (stripped and rerun through the litho cell) or scrapped. Current MADI systems are manual or semi-automated, and illumination may range from common green lights or spotlights to special point sources and flat, monochromatic panels.

Always, the detector is human.

This is limited; defect detection and classification are inconsistent and unreliable, with results varying due to wafer complexity, background patterning noise and human boredom and fatigue. Up to 80 percent of all MADI defects may go undetected until after etch or final test, when it is too late, resulting in higher scrap rates and lower sort yields. Depending on fab size, approximately $3.6 million a year are wasted due to defects undetected by human operators.

Increases in wafer complexity are adding to problems likely to go undetected by manual inspection. While other process steps are improved by baseline defect density reduction through automated detection and control of defects, the litho cell — limited 36

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to manual inspection techniques that provide little visibility or control and collect very little usable data — is a source of yield loss and scrap issues.

KLA-Tencor [has introduced] an inspection suite designed to overcome these limitations, the 2401 Automated Macro Defect Inspection System. It is expected to replace the bright-light MADI performed by human operators. It provides automated detection, classification and reporting of all yield-critical MADI defect types, including hot spots, scratches, large particles, extra and missing resist, unexposed fields, striations and developer spots and splash-back (figure 1).

Hot Spots Contamination • particles • foreign materials

Scratches • handling errors

Coating • missing/extra • splashback • striations • comets

Edge-Bead Removal • missing • wrong width • miscentering Develop • wrong program • developer spots Exposure • missing • focus error • gross misalign

Figure 1. Macro inspection is relatively inexpensive (approximately $0.35 per wafer). If done properly, it ensures against expensive problems.

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The system’s sensitivity and inspection consistency, repeatability and accuracy far exceed a human operator’s, allowing disposition decisions to be made quickly and accurately, reducing scrap and averting investment in low-yielding wafers. Integrated with other yield analysis systems, it provides information that can be used to correct defect mechanisms.

The system integrates brightfield and darkfield inspection technologies, necessary for detection of all MADI defect types. These technologies, combined with detection algorithms, simultaneous ADC and 80-wafers-perhour throughput at 50 µm sensitivity, permit detection of individual or continued excursions on any wafer at every layer. Lacking the human equation, operator inattention or inadequate sampling are no longer issues.

The system’s analysis capabilities provide recommended go/no-go disposition decisions, summary statistics, defect maps and defect images. This allows more effec-

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tive dispositioning for higher productivity, lower scrap and more accurate rework decisions.

Integrated as part of a yield analysis system, the system can provide production and engineering analysis capabilities impossible with manual MADI. For example, it can create a composite map of wafers in a lot, revealing defect mechanisms invisible when looking at one wafer.

It also produces defect images that are transferable to the analysis database for a better understanding of defect characteristics. Other analysis capabilities include control charts, summary statistics, defect source analysis, layer subtraction and zone analysis. Pass/fail settings can be configured for each recipe, enabling automated disposition decision-making. Information supporting the recommended decision — such as wafer maps and images — is also automatically provided.

Reprinted from SEMICONDUCTOR INTERNATIONAL, February 1999.

Copyright 1999 by Cahners Business Information.

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ait system heads to samsung

Nominated by customers for performance excellence • Used by leading semiconductor fabs as an inline defect inspection system for CMP and films on 64MB DRAM and 0.25um logic devices • Used for Cu CMP and Cu Plating defect inspection applications at leading development fabs FOR MORE INFORMATION CALL 408-875-3000 OR VISIT WWW.KLA-TENCOR.COM

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Low k1 Lithography Redefines Photomask Quality

by Brian Grenon, Grenon Consulting, Inc.

Lithographers are continually driving their current lithography wavelength capabilities with the use of chemicallyamplified resists (CAR), as well as resolution enhancement techniques (RET) such as phase shifting masks (PSM), optical proximity correction (OPC), and off-axis illumination (OAI). While these improvements provide extended technical capability at a given wavelength and numerical aperture, they place an additional burden on the mask maker because the wafer lithographer is using a lower k1 factor to produce features on the wafer. As a result, the conventional parameters for defining mask quality or specifications – historically based on a fraction of the wafer feature size times the reticle magnification – are no longer adequate. Mask specifications need to be closely coupled with the lithography techniques used by the wafer fabs, rather than just chip feature size and reticle magnification.

k1 Factor 0.9

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0.8 0.7

k1 Factor

As a result of RET’s extending the use of a given wavelength for multiple generations of lithography, lower k1 values are being utilized to generate chips with today’s ground rules. Because the cost of lithography represents one third of the cost of manufacturing a chip, extending a given lithography tool set is the most cost-effective method for maintaining profitability in a wafer fab. Figure 1 shows the relationship between linewidth and k1 factor for a lithography system with λ = 248 nm and numerical aperture (NA) = 0.60. Today, many lithographers consider k1 values smaller than 0.60 to be “low k1 lithography”. A more simplistic definition is that if you are trying to make a feature smaller than the wavelength of light used, you are printing with a low k1 factor. (Some people refer to this as “sub-wavelength lithography”). At low k1 factors both the mask tolerances and the parameters defined in the specification become more stringent than for more relaxed higher k1 factors. As a result, mask specifications at low k1 factors require careful consideration.

0.6 0.5 0.4 0.3

k 1= Linewidth (µm) Wavelength/NA Low k1 Very Low k1

0.2 0.1 0

Wavelength = 248 nm NA = 0.6 .26 .25 .24 .23 .22 .21 .20 .19 .18 .17 .16 .15 .14 .13

Linewidth (µm) Figure 1. The relationship between k 1 factor and linewidth for a lithography system at λ = 248nm and NA = 0.60.

Low k1 leads to new defect classes

From a practical sense, the parameters that determine a quality photomask are related to the amount of light transmitted through each feature on the mask. In the case of critical dimension control — either CD-to-target or uniformity — the amount of light transmitted through each feature is either too much or too little.

Seldom is it exactly as required by design. These errors are classically called CD errors and not transmission errors. In the case of clear and opaque defects, there is either light transmitted where none is desired or no light transmitted where it is required. An image placement error results in light transmission misplaced in the x and y plane of the wafer.

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Localized transmission loss

When one looks at mask anomalies in terms of transmission errors, a different perspective develops relative to the definition of a photomask defect. Lawes reported that the minimum printable defect (MPD) was defined as a constant fraction (0.18λ/NA) for all linewidths down to a k1 of 0.8.1 While this simple equation may hold true for high k1 factor lithography, it does not work at low k1. Loss of transmission becomes the most important anomaly. Perhaps the best example of the fact that localized transmission loss represents a new class of defects was reported by Vacca et al.2 The authors reported a stain-like anomaly on a photomask as seen in figure 2. The left side of the figure shows a darker region or “stain” caused by localized reticle CD errors. With the advent of low k1 factor lithography and the development of KLA-Tencor’s advanced linewidth measurement (ALM) algorithm, the true nature of this local CD anomaly was understood. The right side of figure 2 shows the effect of this defect on the wafer.

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should be aligned by dividing the historical extrapolations by the MEEF: Low k1 reticle specification = Low k1 reticle specification/MEEF Transmission loss due to defect repair

The second most common defect that has become a significant concern to lithographers is the defect caused by transmission loss on the mask due to defect repair.

Like localized CD errors, this defect can print on the wafer causing yield loss. Reynolds and Schellenberg reported on the effects of laser repair on mask transmission and their printability.4 Similarly, focused ion beam (FIB) repairs can print if transmission loss is too high.

Transmission loss caused by mask repair is the result of damaging the quartz either by thermal shock with the laser, or in the case of focused ion beam (FIB) by embedding ions or surface damage to the quartz.

Figure 3 shows the relationship between transmission loss and yield loss as a function of k1 factor. It can be seen from figure 3 that at k1 factors of around 0.60, transmission losses of 5 percent on the mask can have a significant effect on yield. While figure 3 more accurately represents yield loss as a function of transmission loss due to repair, it is safe to say that similar yield loss may be expected for any localized transmission loss.

Obviously, the location of the transmission loss will have a significant effect on its impact on wafer yield.

Figure 2. (Left) shows a stain-like defect on a chrome mask, which is in fact a localized CD error. The right side of the figure shows its impact on the wafer. (Vacca, 1997).

Figure 2 also demonstrates that CD errors result in loss of transmission and manifest themselves as printable defects. The findings of Vacca et al. are consistent with those reported by Wong et al.3 that as k1 factor decreases the mask error enhancement factor (MEEF) increases rapidly from unity.

Transmission loss due to organic defects

The third type of transmission loss defect that has recently become more common in the low k1 factor lithography arena is the partially transparent organic defect. Two of these defects are generally known. The first is the defect caused by fragments of damaged Yield Loss vs. Reticle Defect Transmission

That is to say, when k1 factors are below 0.60, then the ratio of mask CD error to wafer CD error is no longer linear and mask errors have a greater effect on wafer lithography quality and yield.

It is important to note that while errors associated with CD-to-target can be compensated by changing exposure at the wafer, localized CD errors (or CD nonuniformities) cannot be corrected by exposure. As a result, to prevent reticle CD errors and defects from consuming an increasing percentage of the error budget, mask CD uniformity and defect specifications

% Yield Loss

MEEF = ∆resist CD/∆normalized (by reduction ratio) mask CD3

Defect Transmission Loss % Figure 3. The potential effect of mask transmission loss on yield as a function of k 1 factor.

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pellicle material. There have been incidents where small fragments of pellicle material have remained on masks during the pellicle replacement process. These fragments cause localized transmission loss resulting in the type of defect shown in figure 2 on the wafer. The second of these is the so-called Santovar case, where this material when exposed to UV radiation is sublimed and re-crystallized at the edge of chrome images causing “killer” defects. Santovar is used as a staining protector in rubber adhesives. In this case the source of the defect was identified as the pellicle adhesive. While this material is no longer used in pellicle adhesives, other hydroquinones are also used as UV stabilizers in the polymer industry. Most hydroquinones will absorb UV light and be converted to quinones in the process. Many quinones are easily sublimed. The purpose of this discussion is to highlight the point that many organic compounds become volatile and undergo polymerization when exposed to UV light. Wavelengths of 248 and 365 nm are quite efficient for

molecular photochemistry, which is why they are used for lithography.

It is important to keep in mind that some volatile organic compounds found in the environment of the wafer fab can be polymerized on optical surfaces. Two of those optical surfaces are the photomask and the pellicle. Inoue et al. reported on the effects of various environmental contaminants on the transmission characteristics of nitrocellulose pellicles.5 Summary

Considering the increasing significance of transmission loss defects at low k1 factor lithography, it is imperative that both the mask tolerances and the parameters defined in the specification become more stringent. At the same time, it is important that the systems used to inspect for mask quality have the capability to detect localized CD errors and organic defects, as well as transmission losses resulting from mask repair. With the increased use of DUV lithography and the advent of 193 nm lithography, it is manda-

tory to identify all mask anomalies.

The most effective method to assure mask quality is through a comprehensive mask inspection routine which includes both transmitted and reflected light inspection, preferably as close as possible to the wavelength at which the mask will be exposed.

1. Lawes, R. A., Future Developments for Optical Mask Technology, Microelectronics Engineering 23, pp. 23-29 (1994).

2. Vacca, A., Eynon, B. and Yeomans, S., 100 nm defect detection using an existing image acquisition system, Proceedings of SPIE 17th Annual Symposium on Photomask Technology and Management, Vol. 3236, pp. 208-214, (1997).

3. Wong, A., Ferguson, R. A., Liebmann, L. W., Mansfield, S. M., Molless, A. F. and Neissier, M. O., Lithographic Effects of Mask Critical Dimension Error, SPIE’s 23rd International Symposium on Microlithography, p.167, (1998).

4. Reynolds, J. A., and Schellenberg, F., The printability of laser mask repairs at Deep UV, , Proceedings of SPIE 15th Annual Symposium on Photomask Technology and Management, Vol. 2621 pp. 145-156, (1995).

5. Inoue, N., Nakagawa, M., and Kitajima, M., Pellicle vs. Influence of Clean Room Environments, SPIE Proceedings Photomask and X-ray Mask Technologies II, Photomask Japan, Vol. 2512, pp.

60-73, (1995).

KLA-Tencor Trade Show Calendar

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May 3-5

Electrochemical Society, Seattle, Washington

May 9-11

P2ID, Monterey, California

July 12-14

SEMICON/West, San Francisco, California

July 14-16

SEMICON/West, San Jose, California

September 6-10

VMIC, Santa Clara, California

September 15-16

BACUS, Monterey, California

September 15-17

SEMICON/Taiwan, Taipei, Taiwan

September 21-23

Diskcon, San Jose, California

September 28-30

ITC, Atlantic City, New Jersey

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Analysis of Reticle CD Uniformity with CD SEMs

by Waiman Ng, Ph.D., Senior Product Marketing Engineer

As device dimensions are scaled below 0.18 Âľm, increasing demands are placed on critical dimension (CD) control of the lithography process. One large contributor to this total CD error can be attributed to the reticle. This is pushing the mask industry to improve their capabilities in pattern generation, inspection and metrology in order to meet these stringent CD requirements. Current optical metrology tools are operating at the limit of their resolution. CD SEM technology will be required to help mask makers meet these challenges.

The requirements of semiconductor manufacturers, as evidenced by the SIA roadmap, are driving the reticle development cycle at an ever-increasing rate. With the current trends toward employing optical proximity corrections (OPC) to features to improve the image transfer to the wafer, as well as phase shift masks (PSM), both targeting the extension of the range of optical lithography, even more emphasis is being placed on photomask quality. This is driving the mask industry to improve their capabilities and technology in order to meet these stringent CD requirements.

characterization of both the reticle and printed wafer with the same system. This ability eliminates one possible source of error in reticle to wafer correlation studies. This capability will become increasingly important as CD uniformity and pattern fidelity for OPC features become more critical.

Previous reticle CD metrology is based primarily on optical technologies. As the reticle feature size approaches the wavelength of light used in these metrology instruments, diffraction can cause large proximity effects.

This leads to a highly non-linear optical response for metrology in the sub-micron range. The mask industry must explore new CD measurement technologies in order to meet the current and future CD control requirements.

The KLA-Tencor 8100XP-R makes use of a proprietary advanced charge elimination (ACEâ&#x201E;˘) system, which ensures that local surface changing on the reticle is eliminated. The ACE system allows the 8100XP-R to provide stable imaging and metrology even on isolated chrome features. Figures 1 and 2 illustrate how the 8100XP-R controls surface charging of an isolated chrome feature on a reticle with an average chrome density of 5 percent. This imaging technology allowed us to perform the following experiment to quantify the reticle contribution to CD error.

Low voltage CD SEM-based imaging and measurement systems are the current platform of choice for high throughput automated metrology systems used for lithography process control on silicon wafers.

These systems offer the imaging resolution and precision required for wafer CD control below the 0.18 Âľm level. Recent modification of the wafer CD SEM for reticle use also offers the additional advantage of direct

Adaptation of wafer CD SEMs for reticle CD metrology is not a simple task. SEM imaging of chrome on glass (COG) reticles pose significant challenges, since glass is a highly insulating material. Isolated areas of chrome on glass have no direct path for charge dissipation; the resulting sample charging can be a major cause of image instability in conventional SEMs.

Figure 1. Typical sample charging

Figure 2. The same isolated chrome

effect for isolated chrome feature.

feature imaged with the ACE system.

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Reticle CD: Verticle Iso 1130 1120 1110 1100 1090 1080 1070 1060 1050 1040

Figure 3. Reticle CD contour plot, vertical isolated line.

Case study: reticle CD uniformity

Intrafield CD uniformity is becoming an increasing limitation to integrated circuit performance. Tighter restrictions are placed on the across chip linewidth variation (ACLV) to improve yield and device speed on an increasingly larger die. In addition, non-linear transfer of reticle CD errors to the wafer, known as Mask Error Factor (MEF)1, has increased the importance of studying reticle CD variation on printed ACLV. The capability to identify and separate the component sources of variation is essential when working to reduce ACLV. In particular, quantification of the across-reticle contribution of CD variation to the printed CD on the wafer is critical in order to isolate the CD non-uniformity effects of the exposure tool or process2.

Contour maps of the reticle and wafer CD data are plotted to create a “fingerprint” of the reticle contribution to the overall intrafield CD distribution. Figure 3 is the contour plot for the isolated vertical line feature on the reticle. It is clear from this plot that the CD variation on the reticle is not purely random, but it has a strong radial distribution. This CD variation is most likely a signature of the wet process used on the mask. Figure 4 is a contour plot of CD variation of the same feature as printed on the wafers. The CD variations on the wafer also exhibit a radial component, but its distribution is lopsided. To isolate the contribution of the stepper, we removed the reticle CD data from the observed variation of CDs printed on the wafer. Figure 5 is a contour plot of the wafer data with the reticle CD error removed. Figure 5 shows that after the radial component of reticle variation is compensated, a linear component is clearly visible on the plot. This linear CD distribution can be attributed to the stepper and processing of the wafer.

Wafer CD: Reticle CD/4.1: Vertical Iso 25 15 10 5 0 -5 -10 -15 -20 -25

For this experiment, a standard test reticle with CD metrology cells located in a uniform array across a square field was used. First, a set of 0.25 µm features on the reticle was directly measured with a CD SEM. The test reticle was then used to expose a set of test wafers. Next, the corresponding 0.25 µm features on each stepper field on the printed wafer were measured using the CD SEM. These CD measurements were used to examine the impact of systematic reticle CD variations on the estimate of the CD non-uniformity of a stepper projection lens.

Wafer CD: Verticle Iso 285 280

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Figure 5. Compensated CD contour, wafer – reticle/4.

The CD SEM results presented in this article illustrate a method to measure reticle CDs. Separating the reticle CD component from any stepper-induced CD variation allows for a more accurate assessment of the sources of CD non-uniformity. It is possible to reduce the apparent stepper field uniformity by carefully extracting the reticle contribution to the overall measured field distortion. Using the reticle-compensated CD data can yield better correction inputs to the stepper and provide better lithographic performance. circle RS#037

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Acknowledgements: Special thanks to David Witko, Shawn Cassel, James Foster, Geoff Anderson and Richard Elliott. The author would also like to thank Raymond Yip for assistance with data analysis and contour plotting.

255 250 245 240 235

Figure 4. Wafer CD contour plot, vertical isolated line.

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1. J.P. Kujiten, et.al., “Analysis of Reticle Contributions to CD Uniformity for 0.25 µm DUV Lithography”, Presented at SPIE, Feb. 1998.

2. G. Anderson, et.al., “Intrafield CD Uniformity study in 0.25 µm Lithography”, Presented at Olin Interface ’98.

Test reticles for lithography and process evaluation

FOCUS

EXPOSURE

PROXIMITY EFFECTS

PROCESS DEFECTS (COAT/DEVELOP/RESIST)

DEFECT SENSITIVITY (OPC and nnoonn--OOPPCC))

Leading fabs throughout the world rely on Benchmark test reticles to quickly and accurately evaluate their steppers...

Shouldn t you?

LENS HEATING/ASTIGMATISM/COMA HEATING/ASTIGMATISM/COMA

RESOLUTION

FIELLDD TILT/CURVATURE TILT/CURVATURE

OVERLAY/MATCHING OVERLAY/MATCHING

ILLUMINATION ILLUMINATION UNIFORMITY/COHERENCE UNIFORMITY/COHERENCE

WAFER WAFER CHUCK CHUCK FLATNESS FLATNESS

Benchmark TECHNOLOGIES

To learn more about Benchmark products, contact us at (781) 246-3303, or visit our Spring 1999

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New Processes Present Yield Loss Issues In efforts to utilize strategic improvements in production equipment rapidly, engineers at MiCRUS Corp. (Hopewell Junction, NY) are rapidly identifying causes of yield degradation in evolving photolithography processes. As reported at KLA-Tencor’s Yield Management Solutions Seminar at Semicon/West, Paul Klymco explained how new resist materials, new equipment with unknown fail histories, processes with relatively narrow process margins and process modifications with limited exercise in a production environment lead to a variety of defectivity mechanisms. Expeditious identification and eradication of these defect sources are key to enjoying the benefits new equipment and materials technologies afford.

by Laura Peters, Senior Editor, Semiconductor International

• Second Pareto of KLA-Tencor data, • Tracing defects to specific process tools, • Increased sector particle monitoring, • Controlled or stressed process experiments, • Process step partitioning and • Physical or chemical particle analysis.

Goals in choosing such actions include desire to minimize production disruption and gain enough understanding to prevent recurrence of the defect event. In this case, a developer module with excessive N2 driving pressure caused the 44

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defects. Another example reveals how a new design exposes process limits. A new category of catastrophic defects appeared on the isolation level during initial volume ramp of logic products.

The defects occurred variably by lot and density and favored the wafer’s outside edge, more common in dense pattern area.

Corresponding particle levels on monitor wafers in photo and metal etch were not detected.

The approach isolated defects by photo tool and extensively reviewed tool parameters. Post-photo screening using the 2132 system was performed on indicated photo tools.

SEM and EDX analysis of the batch on the defects revealed carbon material deposited over images. Resist contamination, which redeposited out of the developer, also showed a pH shift at the rinse step. To remedy the problem, the engineers increased the exhaust flow rate and replaced water in the initial rinse process with clean developer.

Klymco further traced the problem to the thick resist used in the n-well

Yield Management Solutions

1st Level Metal KLA-Tencor Yield, 4B Logic 2.5

% Defective KLA-Tencor Sample Area

The MiCRUS fab uses overlapping technologies, with KLA-Tencor 2132 and 2135 product monitoring tools at key process points, along with sector-based particle monitoring of tools and films on unpatterned silicon wafers to reveal causes of yield loss.

For instance, partial development of photoresist caused different types of yield problems. Depending on the problem, follow-up actions could include:

Short In Ins. Damaged Ins. Part. Under Metal Part. In Metal Bridge

2 1.5 1 0.5 0 APR

MAY

JUNE

JUL

AUG

SEP

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Figure: Yield management defect density pareto feedback

implant mask, which provides a heavy load on the developer puddle.

He said the n-well implant mask generally is considered “non-critical” and typically monitored less closely than other mask steps.

Finally, a wavy short problem — sharp spikes of small metal-level bridges — began to appear during production. Monitoring of resist film contamination pointed to a resist application problem, with consistently small-sized particles. Particle EDX, resist lot changes to accelerate the problem and complete disassembly and inspection of the precision resist pump showed no resist aging but a

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Yield Management Seminar Series A valuable venue for innovative ideas

KLA-Tencor’s Yield Management Solutions Seminars (YMS2) focus on value-added, integrated solutions for yield management and process control. Key topics are already lined up for this year’s SEMICON/West YMS, including CMP, lithography, in-line monitoring and yield strategies, with an emphasis on copper. It promises to be one of the most interesting seminars in KLA-Tencor’s history.

residue on the drip control piston surface. The residue was identified as diazo-based PAC by infrared spectroscopy. Drip control suction caused particle build-up on the piston and contamination of the resist line. Periodic cleaning of the piston surface addressed the issue, while less-susceptible resists were later implemented.

Klymco emphasized that “the benefit of new equipment or processes can be long delayed without equivalent attention to their specific weaknesses.” He found early intensive review of defects with 2132 and 2135 tools key to rapid identification of new problems and critical elimination of defect recurrences.

Reprinted from SEMICONDUCTOR INTERNATIONAL, October 1998. Copyright 1998 by Cahners Business Information.

To reserve your space at this year‘s YMS2, please complete and return the enclosed business reply card.

DATE: TIME: LOCATION:

Tuesday, July 13th 9:00 a.m. to 6:00 p.m.

The Argent Hotel (formerly the ANA Hotel)

Call for future papers

Papers should focus on using KLA-Tencor tools and solutions to enhance yield through increased productivity and performance.

Topics of interest include defect inspection, lithography, CMP, film measurement and yield management strategies.

If you are interested in presenting a paper at one of our upcoming yield management seminars, please submit a one page abstract to: Marie Sholar by fax at (408) 875-4144 or email at marie.sholar@kla-tencor.com.

YMS2 at a Glance DATE August 12 August 17 October 20 December 2

LOCATION Hsinchu, Taiwan Singapore Austin, Texas Makuhari, Japan

Spring 1999

ABSTRACT DEADLINE May 3, 1999 May 3, 1999 July 1, 1999 September 1, 1999

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The Role of Standards In Yield Management

by Jim Greed, President, VLSI Standards

Metrology plays a significant role in the management of yield; many measurements of wafer and reticle attributes can be correlated with ultimate device electrical performance, and are therefore used to maintain process control in the fab. Calibration of metrology and inspection tools has assumed increasing importance due to both the requirements of contemporary quality systems and the demands of consistent worldwide multi-site manufacturing. Throughout the process, standards provide the enabling technology to perform these tasks.

An Overview of Standards The term standard can mean either a physical artifact such as a reference material used to calibrate a metrology tool, or a documented procedure or list of attributes used to qualify a product (e.g. a product safety standard,). In the field of measurement science, the uses of this term are usually intertwined as shown in figure 1, which delineates some of the most basic types of standards.

Physical standards have one or more well established properties, and are often traceable to a national authority 1

such as NIST . The certified properties of these standards that make them

In the past, significant confusion and disagreement in measurement science terminology has contributed to an inability to accurately compare data from multiple sources. Due to their universal nature, standards play a key role in defining such terminology on an international scale for a variety of industries.

Terms such as accuracy, precision, repeatability, reproducibility, random and systematic error pervade metrology activities in an often confusing and argumentative manner. Worse yet, there have been significant differences in the statistical treatment of metrology data in the various nations that participate in international commerce.

Consistent application of metrology standards plays a role in semiconductor manufacturing yield, as the effective use of yield data by multi-national companies depends on a cohesive and consistent understanding of metrology technology and standards worldwide.

suitable for instrument calibration are often determined through the use of

Resolving measurement uncertainty

standard test methods that are written

In the early 1990â&#x20AC;&#x2122;s, worldwide adoption of an ISO2 protocol, â&#x20AC;&#x153;Guide to the Expression of Uncertainty in Measurementâ&#x20AC;?, began to address this issue. This protocol, developed by an international working group,

rather than physical standards.

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Physical and Certifiable

Weights and Measures

Properties of Materials

Written

Product Quality/Safety

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In the process of physical standards certification, the result of the certified measurement is called the measurand. The measurand consists of the value of the property (for example, film thickness or defect size) determined by certified measurement and the degree of uncertainty. In a successful calibration process, the instrument being calibrated reports a measurement result that is within the range of the uncertainties of the calibration standard.

Standards

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Figure 1. A taxonomy of standards.

resulted in significantly greater order in the use of terminology and uniformity in the treatment of measurement data. By defining a consistent method for reporting the results of measurements, the protocol forms the foundation for the internationally accepted definition of traceability in measurements. As defined by the International Vocabulary of Basic and General Terms in Metrology (VIM; 1993), traceability is:

One simplistic way to view the concept of uncertainty is to consider a measurement process which consists of a series of repeated trials where the arithmetic average (mean) of the measurements is recorded for each of the trials. The dispersion of these mean values characterizes the uncertainty of that measurement process. Uncertainty should not be confused with error, as it is an expression of the statistical nature of the measurement process.

The value of measurement data in establishing acceptable yield parameters depends on calibration with a low uncertainty. Consider, for example, a 4 nm gate oxide which has a process tolerance of 0.2 nm.

In order to have a 4:1 ratio of measurement capability to process tolerance, calibration standards must have an uncertainty of less than 0.05 nm. This is approximately one tenth of the spacing of silicon atoms (the lattice constant).

â&#x20AC;&#x153;The property of the result of a measurement or the value of a standard whereby it can be related to stated references, usually national or international standards, through an unbroken chain of comparisons all having stated uncertainties.â&#x20AC;?

Traceability is of value to the semiconductor industry as it provides a tangible benchmark for measurement from an impartial third party arbiter of high level technical capability. An IC manufacturer can invoke the use of traceable standards in the process of acceptance testing a new metrology or process tool. Similarly, an IC manufacturer can use traceable metrology data to certify the quality of the products that he ships.

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Calibration challenges

“The semiconductor world is shrinking!” This is the preamble to virtually every presentation today concerning semiconductor manufacturing, but consider how true this statement is: • Gate oxides are approaching 4 nm, and are forecast to be perhaps 2 nm before a material change becomes necessary — this puts thin film growth and measurement dimensions in the realm of a few atomic layers.

• Particle and defect detection are often done optically at dimensions far below the wavelength of light employed by the detection tool, but how can we identify the source of the particle or deduce its size?

standards models will be used for calibration of all types of advanced metrology and inspection tools. As achieving acceptable semiconductor yield levels continues to become increasingly dependent on highly accurate metrology and inspection, such calibration standards will play a correspondingly significant role

in our future world of atomic dimensions.

1. The National Institute of Standards and Technology, Gaithersburg, MD, USA. 2. International Organization for Standardization, Geneva, Switzerland.

4 out of 5 Perfectionists Insist On VLSI’s Thin Film Metrology Standards.

Clearly, these rapidly accelerating changes continue to demonstrate the need for accurate, precise and repeatable measurements. With the international nature of the semiconductor industry, such measurements must be traceable to reliable and universal standards.

What the future holds

The semiconductor industry is now focused on, among other things, an organized, international, cooperative forecasting of our technical needs for the future and likely solutions, formulated into industry-wide roadmaps. This international effort provides an opportunity to understand the needs for both advanced metrology tools and the calibration standards to verify them. In addition, the underlying need for advanced education of measurement science technologists continues to be clear.

A shared vision among technologists around the world is emerging, where a combination of physical standards and consensus-based

NOW: ny”

n New “Ski s for d Standar 5nm 4.5 & 7. ss!

Thickne If you’re responsible for thin film thickness measurements, you want them to be right. And you definitely don’t want to be embarrassed by a metrology tool that decides to driftat a critical time.

That’s why perfectionists insist on VLSI’s suite of thin-film metrology standards. For silicon dioxide and silicon nitride. The broadest selection in the industry.

And now,oxide standards are available for 4.5nm and 7.5nm! It’s a VLSI exclusive.

So if you’re a metrology perfectionist, flaunt it! Call now for your free “Good Enough ISN’T” button along with your free VLSI catalog...

VLSI Standards: (800) 228-8574.

Or on the Internet: www.vlsistd.com

The Measurement Standards for the Industry.

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Q&A Answers to your questions about KLA-Tencor and the Year 2000 issue.

KLA-Tencor takes the Y2K issue very seriously from both a product readiness and business continuity perspective. We understand the magnitude of this issue for our customers and for our business. We are committed to doing everything we can to ensure a successful transition to and through the Year 2000.

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What is KLA-Tencor doing to address the Y2K issue?

processors, operating systems and third party software have also been evaluated.

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How many KLA-Tencor tools are affected by Y2K?

KLA-Tencor has a Year 2000 readiness project team and program well under way to identify and address all of the main areas of concern: KLA-Tencor yield management systems, internal business systems and services, internal networking and tooling, and critical suppliers. Each product group has an assigned Y2K product owner to coordinate and drive the product-specific Y2K issues, and to work closely with the Y2K program team. Senior management is closely monitoring the program to ensure that it receives the appropriate priority and resources.

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What is KLA-Tencor doing to make its products Y2K ready?

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Through our participation in the SEMATECH Year 2000 Readiness Supplier Survey, we have evaluated all our current products with the SEMATECH recommended version 2.0 test scenarios.

The results are reported in KLA-Tencor's Product Readiness Matrix, which is available to customers through KLA-Tencor sales and service personnel. In addition, C and C++ code have been inspected for date-related code. BIOS, embedded

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Because KLA-Tencor’s worldwide installed base is approximately 17,000, including retired systems and products that are no longer sold, the company faces a substantial challenge in addressing the Y2K issue. While many of our products are not affected by Y2K and many customers are not electing to upgrade all tools, we estimate that between 8,000 and 9,000 tools will be upgraded by the program’s completion.

Field audits, where service engineers determine the product hardware and software configurations, enter that information into our Y2K database and generate recommended Y2K upgrades, will be substantially complete by the time this article is published. Where product obsolescence or other issues prevent KLA-Tencor from providing Y2K support, customers are being notified.

Q

Will there be charges for these Y2K upgrades?

A

As companies in every industry are discovering, the magnitude of the Y2K Spring 1999

program makes it impossible to fund all changes internally. There is typically a range of potential solutions for a given equipment set, reflecting individual customer characteristics and preferences, and necessitating the customer’s involvement in determining the appropriate solution set. Costs are determined by which solutions are chosen and, very significantly, by whether the system is covered by contract or warranty. For billable customers, how current their system configurations are would drive costs as well.

KLA-Tencor’s policy is not to treat Year 2000 as a revenue enhancement opportunity. We expect Y2K revenues will only partially offset our program costs.

Q

Will KLA-Tencor’s internal systems be ready as well?

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The company has assigned dozens of people to inventory, evaluate, and remediate our internal business systems and tooling. Activities are well along in all these areas. We anticipate completion of these activities, as well as evaluation of our suppliers by mid year.

For more information contact your local account team or representative for product status, availability and pricing of Y2K upgrades.

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Product News AIT II In-Line Defect Inspection System

The industry’s first 300 mm bridge tool for sub-0.18 µm design rules, the AIT II offers exceptional defect sensitivity, high throughput and low cost-of-ownership for fast and accurate feedback on process tool performance as well as advanced line monitoring for films, CMP, non-critical etch and photo modules. The AIT II detects particle and pattern yield-limiting defects at up to 40 wafers per hour at maximum sensitivity, independent of device type. Further, the system’s MultiSpot™ feature provides tremendous inspection flexibility by offering multiple, operator-selectable sensitivity setting options — large, medium, and small spot — that can be optimized based on whether the inspection system is used for line monitoring or tool monitoring. circle RS#030

2401 Automated Macro Defect Inspection System

KLA-Tencor’s 2401 system is the industry’s first fully automated inspection system designed to detect yield-killing macro defects (50 µm and larger) generated in the lithography process. Replacing current manual after-develop inspection (ADI) methodologies where operators miss up to 80 percent of photo-related defects, the 2401 enables reliable and repeatable detection of critical macro defect types, preventing further investment in low-yielding wafers and dramatically reducing scrap/yield loss further downstream in the manufacturing process. In addition, the 2401 system allows advanced production and engineering analysis never before possible using manual macro ADI, enabling continuous process improvements for maximum ROI in minimum circle RS#034 time.

FabVARS 500 Digital Image Management System

To serve the current image management requirements in the semiconductor industry, the FabVARS 500 stores and retrieves images generated from a broad variety of on-line and off-line image generating systems. While previous generation systems accepted and stored images only in analog format, the recent migration of many image producing systems to a pure digital format has rendered this capability inadequate. The FabVARS 500 accepts and stores both analog and digital images in a digital format, enabling the system to be connected to a wider variety of tools and yield enhancement systems. This in turn allows wider deployment within manufacturing facilities for faster resolution of yield problems.

SEMSpec Random Mode

KLA-Tencor’s SEMSpec advanced e-beam inspection system enables faster time to results with its unique voltage contrast capabilities and 0.1 µm sensitivity for sub-0.25 µm fabs. It meets the challenges of today’s high aspect ratio structures, new materials and damascene processing. Engineers quickly identify killer defects with advanced SEM-based inspection in Array mode. For increased capability and additional flexibility, SEMSpec now offers Random mode, or die-todie comparison. Without being limited to repeating array features, a larger part of the device can be inspected. With increased capabilities in advanced e-beam inspection, SEMSpec continues to add value and a strong competitive edge for process development, process transfer, and line auditing in leading-edge fabs. circle RS#010 50

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Yield Management Solutions

8100XP-R Advanced Reticle Metrology System

The 8100XP-R CD SEM is the newest addition to KLA-Tencor’s 8100 family of CD SEMs. In addition to its outstanding wafer metrology and imaging capabilities, the 8100XP-R is optimized for reticle-specific applications. The XP optics, combined with ACE™ (Advanced Charge Elimination), provides a stable, repeatable imaging system for chrome-on-glass and phase shift masks.

The enhanced resolution of the 8100XP-R enables the accurate characterization of optical proximity correction features, and extends the linear range of measurements to below 0.15 µm, thus providing precise measurements into the sub-100 nm realm. The 8100XP-R is the advanced reticle metrology solution for tomorrow's reticles. circle RS#037 5300 Overlay Metrology System

KLA-Tencor’s 5300 overlay metrology system enables metrology and lithography engineers to control lithography tools down to the 0.13 µm level. It is the first system of its kind to meet these design criteria. A bridge tool designed to handle both 200 and 300 mm wafers, the 5300 enables tighter overlay budgets and improved overlay control. With the fastest time to results, it maximizes utilization of expensive lithography tools by minimizing idle time. The 5300 is the only overlay system that can measure low-contrast targets resulting from CMP and STI processing consistently and reliably, using a single recipe. It also features optional KLASS 4.0 for Windows analysis software for stepper-specific registration control, and recipe database managecircle RS#038 ment (RDM).

StarLight™ SL3UV Reticle Contamination Inspection System

SL3UV is KLA-Tencor‘s new UV-based reticle contamination inspection system for sub-wavelength (low k1) lithography. Sub-wavelength lithography has increased reticle defect printability, created new UV-specific defect classes, and accelerated advanced reticle deterioration, threatening yield and profitability.

The SL3UV is the first UV contamination inspection system to detect new defect classes, including transmission defects and wavelength-dependent contaminants such as organic defects and gallium stains. The SL3UV can also inspect Tri-Tone PSMs and reticles with advanced OPC assist bars as well as provide the sensitivity and minimum linewidth required for the inspection of reticles for 4X lithography design rules at 0.18, 0.15 and 0.13 µm.

363UV Reticle Pattern Inspection System

KLA-Tencor recently added the 363UV model to the 300UV Series of Reticle Inspection Systems to increase inspection productivity and turn time for many advanced DUV reticles where slowdowns were occurring with the previous 353UV model. The 363UV model includes a 300 MHz Sun Microsystems Ultra60 workstation with 68 GB of available hard disc storage for faster data preparation. Also included is a C3 or C5 rendering hardware upgrade from the previous C2 or C4 to improve inspection times for some high figure count reticles. KLA-Tencor is offering: new systems, field upgrades of a 353UV, or exchanges of an older generation 351.

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©1998 KLA-Tencor, Inc.

Defect excursions and yield busts can be such a tragedy. But fortunately, now there’s professional help.

It’s our fully integrated and automated Intelligent Line Monitor solution. By detecting, classifying and analyzing yield-killing defects in real time, it lets you make instant, targeted process and equipment corrections.

Enhance baseline yield. And ultimately, increase revenue.

As the industry’s only truly integrated line monitoring system, ILM delivers a complete solution for each process step. It starts with industry-leading brightfield and darkfield inspection technologies that cover every application, from advanced engineering

M O N I T O R I N G

analysis to line monitoring, process tool monitoring, and wafer and equipment qualification.

And it combines all this with production-proven on-line and off-line automatic defect classification software. As well as the industry’s first fully automated yield analysis system.

All of which results in quicker access to better information. Faster responses to process excursions. Reduced defect density. And substantially improved baseline yields.

There. Aren’t you feeling better already?

For more information, or to get a free copy of our book “When Bad Things Happen To Good Wafers,” please call 1-800-450-5308, or visit www.kla-tencor.com.