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Application of Automatic Defect Classification in Photolithography

by Gary Stinson, Microchip Technology Inc. and Bo Magluyan, KLA-Tencor Corporation

This paper presents two applications of Automatic Defect Classification (ADC) to monitor and control defect density in photolithography processing. These techniques can also apply to any process module. Many defect types are only generated when wafer pattern is present, while other yield impacting defects are detected only on monitor wafers due to a low signal-to-noise ratio on product wafers. The use of ADC in both cases to find root cause solutions is a powerful tool enabling quick time to results and reduced yield risk in the manufacture of integrated circuits.

ADC is a powerful technique that has truly come into its own in recent years.

Envisioned as a logical progression of defect inspection and review, the ADC concept has been faced with serious technical challenges that have taken time to overcome. Its primary focus is to replace the manual review of defects detected by the inspection systems. Classification accuracy, speed, and cost are all significant factors relating to the justification of ADC, especially for fabs that already have manual classification systems in place. In this paper another perspective concerning the justification of ADC over manual review is presented.

Identifying a defect and finding the piece of equipment or process module that is generating the defect is only the first part of improving yields. Eliminating the root cause is always a difficult task that often requires designed experiments to identify the defect mechanism. When designed experiments are used to solve a defect issue, the output response is the number of the defect type of interest. Depending on the complexity of the process, many wafers may need to be inspected and reviewed to determine the statistical validity of the changes made. Additionally, the confidence level of

results generated from such a study is directly dependent on the accuracy and purity of the classification of the defect.

Microchip’s ADC program, consisting of KLA-Tencor’s IMPACT ADC, 2135 inspection system, and Klarity Data Analysis is used extensively in this engineering role.

Case 1: Problem description

Yield trends for a new device were trending below expectations. One of the primary failure modes for the device was high standby current. Failure analysis revealed a trench from metal to substrate causing the high standby current failure (Figure 1).

Figure 1. SEM image of device failure.

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The spatial signature of the defect showed a higher density in the center of the wafer. Analysis of multiple die failing for the same bin found that there was a tendency for the defect to occur around specific types of structures. The source of the defect appeared to be between the second poly silicon level and first metal deposition. The crack would travel along the edge of the poly2 until it found relief.

To investigate further, a newly installed KLA-Tencor 2135 with IMPACT ADC was brought on-line. Initial inspections prior to Metal1 deposition detected the defect, which appeared to be a stress-relieving crack in the dielectric. This was allowing the remaining etch processes to trench into the silicon substrate causing the current leakage. Since the dielectric was identical to previous technologies, which were not experiencing the problem, it was suspected that the defect had to be patterned on the wafer in the contact photo step and subsequently etched through to the substrate.

Inspection of wafers after the contact photo step detected the stress crack in the resist as suspected. SEM images showed that the contacts were not distorted, but lifted from the wafer intact (Figure 2).

ADC on product wafers

After the defect was found patterned in the photoresist, the process module was shut down until a solution could be found. Photo engineering evaluated all lithocells qualified for the process to ensure that specifications were being adhered to. All systems were functioning normally and in control. After the setup parameters were verified, monitor wafers were processed with individual photo process steps and film stress measurements were made. Although the stress measurements were tensile, consistent with the formation of these types of cracks, the data failed to indicate a part of the process causing the defects (Figure 3).

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Figure 3. Film stress data.

While these experiments were being conducted, an ADC classifier based on the initial wafer inspection data was being developed. This rudimentary classifier was constructed from only two wafers from one lot, but since the defect features were unique, the accuracy and purity were high.

ADC was used to generate results for the next designed experiment, which focused on various modifications of the process. Data from the ADC bin for resist cracks was able to show that the number of cracks were reduced on each of the non-standard splits, but were not eliminated entirely (Figure 4).

If manual review utilizing defect sampling were used, it is possible that split #5 could have given a false good result. Not only did ADC return information more quickly, but the data was also more accurate.

Figure 2. SEM image of resist crack.

The sequence of events in the investigative process, from the failure analysis results to locating the defect in the resist took a relatively short period of time.

Solving the problem without significantly changing a critical photo process appeared to be a much more difficult task.

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Since the first tests reduced the number of cracks but did not eliminate them entirely, the root cause was still to be determined. Several process splits were generated, varying the resist thickness and coat procedures. Again, ADC was used to review all the defects detected. This time the data showed the stress cracks to be eliminated on all splits except the standard process. The standard

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Figure 4. ADC results of first experiment.

The quickest and best solution was to leave the resist thickness unchanged and implement the changes to the dry step. Within hours, production was resumed with an ADC wafer inspection implemented. After the process change, the ADC classifier detected no additional cracks.

Inspections continued until yield data could be gathered using the new process. A dramatic yield improvement in the form of reduced variation confirmed the data already available from the ADC classifier (Figure 6).

Case 2: Problem description

The second case applies to an incident of contaminated photoresist. A simple EPROM device has historically been used as a defect monitor since it has relatively high circuit density and significantly larger die than the majority of other microcontroller products. Yield

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Figure 5. ADC results of second experiment.

trends on this device had not been meeting expected goals. Several failure analysis attempts to identify the cause pointed to 0.5 Âľm to 1.0 Âľm Poly2 bridging between adjacent memory cells, but visual and laser scattering inspections were not able to find the defect Resist Crack Eliminated

Number of Parts Passed

process used a high spin speed for an extended period of time to accomplish both the cast (step used to get the proper thickness) and dry (step used to allow solvents to evaporate). The ADC data showed conclusively that by slowing down the dry step or by increasing the resist thickness, the defect was eliminated entirely (Figure 5).

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Lot Number Figure 6. Parts Passed trend chart shows case 1 yield improvement.

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in-line. A sharp downturn in yield for this device and others relating to the same defect mechanism raised the priority for eliminating the defect.

A KLA-Tencor 2135 inspection system was brought on-line and quickly detected the defect. Resist precipitates that were not being developed away were protruding from the resist lines causing the blocked poly etch (Figure 7).

The defect density was very high indicating that something had gone wrong with the resist quality. All product lines using this resist were shut down until the problem could be solved.

promising. The first experiment was to put the old filter type back on line to see if it would get the problem under control so that production could continue.

Product wafers were processed and inspected using the ADC classifier to measure effectiveness. Although there was a decrease in defect density, it was not significant enough to resume production. More tests were attempted with a new bottle of resist, hand dispensed resist, new resist lines, new resist pump, etc. The defect density and defect size were reduced with each test as the resist delivery system was purged of the contamination.

Production was resumed and the inspection with ADC was used to monitor the defectivity level.

As the precipitates became smaller, it became obvious that background nuisance defects in the underlying poly silicon were causing confusion. A better solution had to be found to monitor for additional excursions.

The product inspection was replaced with a daily patterned resist monitor. The use of monitor wafers brought about new types of defects not seen on product, but since the poly silicon was not present, the accuracy and purity of the classifier were much improved. Monitoring the defect level of the resist ADC bin was successful in measuring additional improvements and monitoring for excursions.

Figure 7. Resist precipitate.

The Photo Group’s efforts to find the source of the defect focused on several possible causes. Photoresist handling and storage techniques were verified to be in spec. Particle tests for contaminated batch also proved to be within the manufacturing tolerances. Yield data vs process dates were analyzed showing the downturn to loosely correlate with a change in resist filter type.

Since the precipitates were larger than the filter rating, and the particle counts of the resist were in spec, there had to be more to the problem than the filter issue.

ADC on monitor wafers

While photo engineering was investigating the resist, an ADC classifier was developed using the initial data that detected the defects in the resist. Overall setup of the classifier took only a few hours and appeared very

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Additional tests indicated that an interaction was occurring between the resist and the pumping system, causing the precipitates to form downstream of the filter. Since no other resist in use was showing the problem, the root cause solution was determined to be a resist change. Qualification of a new resist can take a considerable amount of time especially for a critical layer like Poly2. Using the ADC classifier, a maintenance procedure was identified to control the defectivity until a new resist could be qualified. This procedure was incorporated in the scheduled quarterly PM and involved changing the pump, filter, and chemically cleaning the delivery lines. By having a cleaned pump ready at all times, the time required to perform the procedure did not significantly increase downtime.

As the monitor wafer procedure was fine-tuned, it became possible to control the defectivity by using the raw counts from the inspection. The defect mechanism proved to follow a predictable failure cycle that was controllable through a scheduled maintenance procedure. Defect images captured using the ADC system were still useful to verify the defect type, but the control charts were changed to total counts for simplicity.

Device yield for all products using the resist increased by a step function in response to the actions taken. The resist monitors were changed from daily to weekly as confidence in the maintenance procedures increased (Figure 8).

Summary

In this paper two examples of the use of ADC to find root-cause solutions for yield limiting defect excursions have been presented . The first utilized ADC on product wafer splits since the defect was generated only on wafers with topography. The second example showed that ADC’s capability can be extended beyond the inspection noise level inherent in product inspections by using monitor wafers. By using ADC, useful information from the wafer inspection data was generated faster and with improved signal to noise than if manual review were used. This technique demonstrates the natural extension of ADC from the production-monitoring arena into complex engineering studies to eliminate defects and improve yields.

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Resist Defect Eliminated

Lot Number Figure 8. Parts Passed trend chart shows case 2 yield improvement.

Presented at 10th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop (ASMC), September 8-10, 1999, Boston, MA.

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