Summer03 effective litho

L

Inspection I

T

H

O

G

R

A

P

H

Y

Effective Lithography Defect Monitoring Ingrid Peterson, Louis Breaux, Andrew Cross, and Mike von den Hoff, KLA-Tencor Corporation

As minimum dimensions and process windows decrease in the lithography area, new technologies and technological advances with resists and resist systems are being implemented to meet the demands. Along with these new technological advances in the lithography area come potentially unforeseen defect issues.

Introduction

The latest lithography processes involve new resists in extremely thin, uniform films, exposing the films under highly optimized focus and illumination conditions and, finally, removing the resist completely and cleanly. The lithography cell is defined as the cluster of process equipment that accomplishes the coating process (surface prep, resist spin, edge-bead removal and soft bake), the alignment and exposure, and the developing process (post-exposure bake, develop, rinse) of the resist. Often, the resist spinning process involves multiple materials such as bottom anti-reflective coating (BARC) and/or top anti-reflective coating (TARC) materials in addition to the resist. The introduction of these new materials Too Wide EBR together with the multiple materials interfaces and the Exposure tightness of the process Non-Uniformity windows lead to an increased variety of defect mechanisms in the lithogSolvent Drips raphy area. Defect management in the lithography Residues area has become critical to successful product introduction and yield ramp.

Striations The semiconductor process itself contributes the largest number and variety of defects, and a significant

portion of the total defects originate within the lithography cell. From a defect management perspective, the lithography cell has some unique characteristics. First, defects in the lithography process module have the widest range of sizes, from full-wafer to sub-optical, and with the largest variety of characteristics. Some of these defects fall into the categories of coating problems, focus and exposure defects, developer defects, edge-bead removal problems, contamination and scratches usually defined as lithography macro defects (Figure 1). Others fall into the category of lithography micro defects (Figure 2). They are characterized as having low topography such as stains, developer spots, satellites, and very small defects such as micro-bridging, partial micro-bridging, micro-bubbles, CD variation and single isolated missing or deformed contacts or vias.

Scribe or Array Placement Resist Bubbles

Field Tilt

Comets

Particles

Hot Spots

Off-Center Resist Dispense

F i g u re 1. Examp les of lithogra phy “mac ro� defects.

Summer 2003

Yield Management Solutions

39

L

I

T

H

O

G

R

A

P

H

Y

support that step in production, and involved the examination of two resist types. In addition to this work, defect density reduction on the actual product Developer Satellite Spots Partial Micro-bridging at this process level in general Spot (not necessarily related to lithography) was performed. The results show the significant impact that advanced lithogLow Contrast raphy processes can have on Spots Bridging the overall defect density for a critical process layer. The data collected from the various monitors was used to build a model for these fabs to analyze Micro-bubble Missing/Distorted Residue Micro-bridging the sampling and methodology Contact CD Variation and to determine the most costF i g u re 2. Examples of lithography “micro” (µ) def ects. effective implementation of the monitoring going forward.

Lithography is the only area of the fab besides CMP in Due to the complex nature of the modeling — owing to which defect excursions can be corrected by reworking the variety of defect types in lithography and the variety the wafers. The opportunity to fix defect problems of monitoring methods potentially available — the without scrapping wafers is best served by a defect Sample Planner 3™ cost model was applied. The Sample inspection strategy that captures the full range of all Planner 3 model was developed by KLA-Tencor in relevant defect types with a proper balance between the partnership with UC Berkeley, Carnegie-Mellon costs of monitoring and inspection and the potential University, and Stanford University. This model has the cost of yield loss. In a previous paper1 it was shown capability of analyzing the cost effectiveness of defect that a combination of macro inspection and high management strategies for the lithography area. numerical aperture (NA) brightfield imaging inspection technology is best suited for the application in the case The data collected from the monitors included the of the idealized fab modeled. In this article we will variety of defect types, their occurrence level and the report on the successful efforts in implementing and frequency of excursions, if any, by each defect type. The validating the lithography defect monitoring strategy potential severity of the defect types was determined by at two existing 200 mm factories running 0.15 µm and the transfer rate to post-etch visual defects, as well as 0.13 µm design rules. the average number of die impacted by the occurrence of these defects both in the baseline circumstance and the excursion events. The modeling was constrained to Lithography area monitoring consider only those sampling options that conformed Lithography area monitoring was implemented in two to the currently available inspection time on the leading-edge 200 mm fabs using five basic methods of inspection tools used. monitoring: unpatterned wafer monitors for resist coatonly using darkfield inspection, patterned test wafer The results of this model for these two fabs and fab cost “micro” photo-cell monitoring (µPCM) with brightfield structure indicate that an optimum strategy strongly high resolution inspection, product monitoring with relies on automated macro product inspection, patterned automated “macro” inspection, product monitoring test wafer µPCM monitoring and µADI. In spite of the with brightfield high resolution or darkfield “micro” significant differences between this model and the preafter develop inspection (µADI), and a daily test wafer vious idealized model, 1 the relative conclusions remain monitoring for exposure tool hot spots and gross remarkably similar for one of the fabs; µPCM monitordefocus conditions. ing and frequent automated macro inspections provide substantial benefits in spite of the costs of performing In both fabs, the monitoring was done for the gate them. The results also show that it is important to lithographic step and the lithography cells used to 40

Summer 2003

Yield Management Solutions

L

optimize the implementation of these methodologies to obtain the optimum benefit.

Furthermore, the contribution of lithography processes to defect density for the latest generation technologies is typically underestimated as a result of the current lack of high sensitivity in many lithography area monitoring schemes as well as the difficulty in properly sourcing defect mechanisms.

Components of the lithography module defect inspection

A block diagram showing the defect inspection points performed in both fabs and tools used, is shown in Figure 3. The inspections include the use of automated low sensitivity (greater than 50 µm) macro and micro inspections (brightfield high resolution or darkfield inspection) on product wafers. These inspections are usually called macro and µADI, and they are photoresist inspections prior to etching the wafers. In addition, we performed patterned photoresist test wafer inspections used for “lithography cell qualification” such as µPCM6, 7. µPCM provides high signal-to-noise defect detection to monitor the lithographic processes as well the health of the individual equipment components constituting the lithography cell. We also include VETM (Viper Exposure Tool Monitor), another patterned test wafer monitor, which is an extension of current exposure tool qualification techniques that rely on (subjective) visual macro inspections.8, 9 The automated macro inspection tool used in VETM enables fast, objective, automated monitoring and qualification of exposure tools in a variety of situations, including routine tool monitoring, prior to committing critical product lots, and/or after stepper maintenance.

The use of unpatterned wafer inspection is limited to performing inspections on resist-coat wafers only.

Unpatterned backside inspection was not considered in this work.

I

T

H

O

G

R

A

P

H

Y

Determining the impact of lithography micro defects on pattern transfer

Defect source analysis (DSA), is a commonly-used engineering analysis method performed on product or short-loop wafers to isolate the process step where different defect types originate. This method is also required to determine the impact of known lithography defects on the pattern transfer. The impact of lithography defects depends on the characteristics of the different defect types, the film characteristics under the photoresist and the subsequent process step conditions after the lithography process (etch, resist strip etc.).

Lithography defects such as those which cause closed contacts may cause significant yield loss, whereas the same defect type may have less or no impact on a gate pattern due to differences in the etch process used.

In order for a defect density monitoring and reduction strategy to be effective, it is important not only to understand the different defect types and sources, but also to estimate their yield impact (kill ratio) as this enables prioritization of the defect reduction work. The yield impact of the different defect types will also influence the sampling strategy as described in the next section (sampling plan optimization).

As described earlier, high sensitivity inspections are required for the detection of low topography, subtle color variation and very small (less than 0.3 µm) defect types (see Figure 2). The sensitivity of ADI inspections on product wafers is limited by low signal-to-noise due

F i g u re 3. Components of t he lithography modul e defect ins pection stra tegy.

Summer 2003

Yield Management Solutions

41

L

I

T

H

O

G

R

A

P

H

Y

to the high noise level from previous layer defects.

Moreover, additional previous layer defects may be detected after the etch step in areas where the etched film has been removed. Therefore, short loop experiments have shown substantial benefits when investigating the impact of lithography defects on pattern transfer. When performing short loop experiments, it is important to reproduce the exact process topography present on production wafers as shown in Figure 4, representing a gate stack for 0.15 µm technology. The green boxes in the table are the different layers required for the short loop as well as the inspection and review requirements for each process step. It is important to emphasize that processing of the short loop wafers requires the same process parameters as those used on product wafers.

F i g u r e 4. Fil m stack for poly gate sh ort loop.

Short loop experiments are very useful when evaluating the impact of lithography defects and understanding interactions of the lithography process with its underlying material. Due to the complexity of this methodology and the cost of the test wafers required, this method is generally not recommended as a monitoring procedure in the lithography area. Instead, it should be used at each critical lithography step to verify and understand the impact on yield of the different defect types detected by the µPCM. Sampling plan optimization

The goal of sampling optimization is to achieve the optimum balance of total fab costs with regards to defect excursion and control costs. The problem of inspection sampling optimization covers a variety of questions for the defect engineer — how to inspect, what to inspect, how much to inspect, what information to collect, how to use the data — with answers to each question working together to provide an overall sampling 42

Summer 2003

Yield Management Solutions

strategy. An inspection sampling strategy is ideally optimized based on minimizing the cost-based risk of yield loss associated with missed defect excursion events relative to inspection costs.

In an effort to answer this problem in an objective manner, KLA-Tencor, in collaboration with UC Berkeley, Stanford, and Carnegie-Mellon University, developed the algorithms and platform to model the cost components associated with the sampling optimization issues in a fab. This project was initiated in late 1993 as part of the Sloan CSM focus study and has resulted in three iterations of the tool to reach its current form.1-4 Sample Planner5 has been extensively used and validated for optimization of sampling strategies for defect inspection in both line monitor and module inspection scenarios.

An optimal inspection strategy must identify the minimum overall cost based on the inspection costs (capital depreciation, test wafer costs, direct/indirect labor costs, service costs, facility costs and false alarm costs) and the excursion costs (the lost revenue opportunity due to increased lots at risk to excursions and the costs of investigating/fixing the excursions). Optimizing defect inspection frequencies is particularly challenging in the lithography module, considering the large number of macro and micro defect types (Figures 1-2). The optimum inspection strategy minimizing the impact of defect density excursions is normally seen to be a mixture of inspection techniques of patterned wafers and product wafers as described previously.1 Increased sampling will most often decrease the potential financial loss due to excursions; however, it will result in increased cost to perform the sampling. To determine the cost of sampling, we quantify equipment sensitivity to each defect type, inspection tool throughput, inspection tool costs (ownership and operation), and queuing/transit times. A stochastic algorithm uses this information along with the excursion data, yield impact of each defect type, and financial data to calculate the overall cost. Iterating through several operationally feasible sample plans, the algorithm determines the most cost-effective inspection strategy.

This rigorous analysis has been performed for the gate module at two production fabs, both providing similar answers in terms of the most valuable inspection techniques and frequencies, despite the very different average sales price (ASP) and wafer values for the products produced.

L

I

T

H

O

G

R

A

P

H

Y

Case studies

FAB A: 0.16-0.13 µm LOGIC This example reports on the successful efforts in implementing and validating the lithography defect monitoring strategy in an existing, leading-edge 200 mm fab running 0.16 µm and 0.13 µm design rules. The data was collected and the modeling done for the gate lithographic step and the lithography cells used to support that step in production. The devices modeled were logic devices with relatively large die sizes (approximately 200 die per 200 mm wafer) and high ASPs. Lithography area monitoring was implemented using five basic methods of monitoring: product monitoring with automated macro inspection, product monitoring with brightfield high resolution micro inspection, unpatterned wafer monitors for resist coat only using darkfield inspection, patterned test wafer µPCM with brightfield high resolution inspection, and monitoring of exposure tool “hot spots” and defocus conditions using pattern test wafers and an automated macro defect inspection tool (VETM or macro hot spot). Data was collected over a period of three months from these inspection and monitoring methods.

Table 1. Defec t t ypes and their overall kill rati os f or the 200 mm logic fab li thography area samplin g model .

would be considered the maximum potential yield impact of an excursion event of that defect type. The die affected during excursions would then be multiplied by the overall kill ratio to obtain the actual yield impact of each defect type used in the model. The major restriction was the available time for use on the brightfield high-resolution inspection tools. The range of sampling scenarios considered for each monitoring method is given in Table 2. Included in these studies is the potential risk for not performing any monitoring at all.

The data collected from the monitors included the variety of defect types, their occurrence level, and the frequency of excursions, if any, by each defect type. The potential severity of the defect types was determined by the transfer rate to post-etch (described in “Determining the impact of lithography micro defects on pattern transfer” on page 51). From this, a kill ratio per defect type was applied, since etch carry-over is not in itself a necessary predictor of yield impact. The kill ratios applied were estimated by either visual determination or by relative size of the defects. Visually, the defect occurrence in either patterned areas that affected pattern or in open spaces provided the estimate of kill ratio.

Small defects (less than 0.1 µm) were given a low kill ratio of between 1percent-5percent. The etch carry-over multiplied by the estimated kill ratio gave the “overall kill ratio.” Table 1 gives the defect types seen in this study and in the model and the overall kill ratios corresponding to them.

The final yield impact was determined by calculating the average number of die impacted by the occurrence of these defects both within the baseline or “in-control” population and in the excursion or “out-of-control” population.

The difference in those populations

With the matrix in Table 2, scenarios were run for each monitoring methodology in a “stand-alone” mode to see what the optimum sampling rate would be if each methodology were the only one available. This was then compared to scenarios where a mixture of all of the methodologies was allowed in order to demonstrate the effect of a comprehensive strategy.

Tabl e 2: Sampling frequencies consid ered in the cost m odeling of th e li thograp hy area for the fi ve moni torin g m ethods.

Summer 2003

Yield Management Solutions

43

L

I

T

H

O

G

R

A

P

H

Y

The outputs of the model for each scenario were: 1) inspection costs of performing the monitoring—which is the sum of capital equipment costs (five-year depreciation) and direct and indirect labor costs; 2) test wafer costs—which are the sum of test wafer materials and processing costs (if applicable); and 3) “excursion costs” —which is the potential revenue lost due to yield loss from excursion events not captured, or the number of die negatively impacted by excursion events that were not recoverable (by rework, for instance). The costs were annualized in some cases, producing a yearly costs summary. The goal is to minimize the inspection costs, test wafer costs, and excursion costs to achieve the lowest excursion costs with the least added operational (inspection and test wafer) costs. For this article, the costs are represented as normalized to the maximum risk represented by no monitoring. Rework capability in the model was allowed, thus providing for recovery in yield (or reduction in lots affected) by capture of excursion events in time.

In addition to the cost outputs, the model outputs the estimated hours/week of tool time usage. For the tool usage estimates, the inspection times per wafer are

Tabl e 3. Wafer inspection ti mes used in model.

needed and are shown in Table 3. Only the brightfield tool usage is shown where relevant in subsequent results since the other tool usage times were relatively insignificant. The stand-alone monitoring method results are shown in Figure 5.

For the comprehensive lithography area strategy, the model was run with all of the five methodologies to determine the impact on the sampling recommendations and overall cost or risk reduction. Figure 6 shows the results from several of the comprehensive strategy scenarios including the minimum cost scenario out of the initial conditions considered. A summary of the results for the optimum scenarios is provided in Table 4. The analysis performed in this case study clearly illustrates

F i g u re 5. a) Cost minimization for µPCM monitoring only; b) Cost minimization for µADI monitoring only; c) Cost minimization for macro ADI monitor ing only; d) Cost minimization f or macro hot s pot (V ETM) monitoring only.

44

Summer 2003

Yield Management Solutions

L

I

T

H

O

G

R

A

P

H

Y

While this model is based on the particular circumstances and defect types observed at this site, some general observations can be made in light of similarities found to earlier, more generic studies. 1 These observations are the following: 1) Macro ADI inspections can have a large impact on the overall costs when included in the comprehensive strategy with a relatively small impact on inspection costs.

A high sampling frequency is optimum.

F i g u re 6. Modeling results using diff e rent combinati on of all inspection methods.

the complexity of determining how best to implement the various defect density monitoring methods (available to the lithography engineer and yield engineer). The Sample Planner algorithm clearly provides an effective tool to facilitate this decision. Since many of the monitoring methods “overlap” in their ability to detect defect types, while differing considerably in their use of inspection resources, it is necessary to utilize a model which is able to integrate all of the factors involved.

2) Expensive inspection tool usage can be minimized for optimum risk reduction with a comprehensive model.

3) The implementation of product-based µADI inspections can be minimized (but not eliminated) with the use of µPCM and other monitoring methods.

Some level of µADI is desirable.

4) The µPCM and µADI methods are strongly dependent on a high sensitivity inspection in order to capture the defect types of interest. Loss of capture rate by sensitivity reductions for throughput considerations could add considerable cost (risk).

FAB B: 0.15 µm Memory

Tabl e 4: Summar y of the results of modeling the l ithography are a defect monitoring s trat egy for bot h the “sta nd-alon e” conditions and the compreh ensive combinati on of monitoring methods .

The second example studied was a high-volume memory fab with a low ASP product. The optimization was performed using micro (brightfield high resolution and darkfield inspection) and macro (automated macro inspection) ADI, µPCM (with brightfield high resolution inspection), unpatterned wafer coat monitor, and exposure tool qualification monitor with automated macro inspection. The defect types occurring and the capture of these defect types for each inspection method/tool were assessed, and estimates were made of the yield impact of each type. The defect types and inspection tool ability to capture an excursion of a particular defect type are shown in Table 5. In this table the crosses represent no capture of the defect type. No one inspection method is sensitive to all defect and excursion types, with the possible exception of µPCM; however, we must also consider the cost of Summer 2003

Yield Management Solutions

45

L

I

T

H

O

G

R

A

P

H

Y

Table 6. Summar y of the r esults of modeling t he lithogra phy are a defect moni torin g s trategy - reduction i n overall cost.

Table 5. Defec t ty pes and tool abil ity to capture th e defect type.

each inspection method to determine which provides the greatest value.

Data was collected for the contribution of each defect type to both the in-control and out-of-control Paretos for each of the inspection methods considered. The impact of each method on the optimum sampling frequency was modeled individually based on the actual excursion data collected, to assess its ability to identify excursions of the different defect types identified, and therefore reduce excursion costs. This Pareto is shown in Figure 7, in terms of excursion delta (the delta between no inspection and the optimum sampling frequency), and total return on investment (ROI), defined as the excursion delta minus the inspection costs. Here, although µPCM provides the biggest excursion cost reduction, when we include the cost of inspection it is, in fact, macro ADI that provides the biggest return on investment, followed by µADI, and µPCM is third in the Pareto using this measure. However, it is possible for more than one inspection method to capture a particular excursion and, therefore, we would effectively over-sample if such a strategy was implemented. A DOE was, therefore, performed using this initial optimum sampling frequency based on the individual monitor method as the center points for a two-level factorial design incorporating the four inspection methods.

46

Summer 2003

Yield Management Solutions

F i g u re 7. Insp ecti on met hod imp act Pareto. Optimum sampling f requency — meth ods treated indepen dently.

This provided a total of 17 ‘runs’ for optimization of the inspection strategy. After the optimization, several scenarios were run to identify and confirm the overall optimum inspection strategy. The results of these simulations can be seen in Figure 8. The observations of these results are as follows: 1) Macro inspection is seen to be the most efficient monitoring method, providing the largest return on investment when implemented with a high sampling frequency (100 percent lots) 2) µPCM and µADI are essential parts of a comprehensive strategy. It may be possible to reduce their sampling frequencies when used in conjunction with macro ADI. 3) For the lowest cost of inspection, an inspection strategy must be considered as a system for

L

I

T

H

O

G

R

A

P

H

Y

F i g u re 8. Modeli ng r esults usi ng dif f e rent combinati on of a ll inspection meth ods.

optimization, as multiple inspection methods can detect excursions of particular defect types. These results were then validated using data collected from a second critical photo layer to ensure a similar strategy could be used for all critical photo stages.

In this case study, µADI was seen to provide a greater return on investment than µPCM. This is very much dependent on the defect types and their relative excursion frequencies and impact. Calculating the relative benefit of each must be assessed on a case-by-case basis.

Some of the benefits of implementing a µADI inspection on product wafers includes no test wafer usage, capture of process integration defect types, and the correlation to yield impact. The sensitivity of inspections on product wafers is limited due to previous layer pattern and defect “noise.” As a result, the sensitivity to certain critical photo defect types is reduced. Nevertheless, this monitor method provides a method to capture and monitor unique defect types and provides significant value when part of a lithography defect monitoring inspection strategy. µADI can be implemented on product with either brightfield inspection technology (such as a KLA-Tencor 21XX/23XX) or darkfield inspection technology (such as a KLA-Tencor AIT tool). Simulations 1 and the

previous case study have shown that high sensitivity brightfield inspection at low sampling frequencies provides the greatest return on investment in identifying lithography defect excursions compared to darkfield inspections at moderate sampling frequencies. An example where dark-field inspection is beneficial occurs when previous layer defects dominate the after develop inspection results, this being the case in this study. In order to improve the inspection results, a new generation brightfield (23XX platform) tool was evaluated.

The 23XX provides unique features allowing high sensitivity, high through-put inspection and nuisance filtering. Different optical configurations can be used to enhance the sensitivity of relevant photo defects and to eliminate noise sources. In addition the 23XX uses an integrated automatic classification (iADC) technology to classify all detected defect types during the inspection.

To understand the capability of this technology several tests were performed on wafers at ADI. The results demonstrated significantly higher sensitivity and iADC enabled the elimination of nuisance defects such as previous layer defects and small resist profile variation while maintaining the full sensitivity to the critical photo defects.

Summer 2003

Yield Management Solutions

47

L

I

T

H

O

G

R

A

P

H

Y

Summary

While these models are based on the particular circumstances and defect types observed at each site, some general observations can be made in light of similarities found to earlier, more generic studies.1 These observations are the following: 1) In both cases macro ADI inspections have the largest return on investment; they can have a large impact on the overall costs when included in the comprehensive strategy, with a relatively small impact on inspection costs. A high sampling frequency is optimum, preferably 100 percent inspection of the lots.

2) In the first case study, the implementation of µADI inspections could have been minimized (but not eliminated) with the use of µPCM and other monitoring methods. A five percent inspection of the lots at µADI was found to be the optimum inspection frequency. However, in the second case study, a much higher frequency of µADI (25 percent of the lots) was found to be more cost effective. In addition, the darkfield inspection technology had advantages for µADI in the second case due to its sensitivity to the defects of interest and insensitivity to previous layer background noise. The brightfield µADI inspections did capture unique defect types missed by darkfield, but these were not considered as critical.

3) The effectiveness of µPCM inspections is strongly dependent on high sensitivity to capture the defect types of interest. Loss of capture rate by sensitivity reductions for throughput considerations can add considerable risk (cost).

4) In both case studies, unpatterned wafer inspection showed very limited value, but these inspections are commonly used for trouble shooting the individual components of the lithography cluster.

5) The VETM or macro hot spot monitor is most effective at a relatively low-level of sampling (once or twice a week) but will replace the typical manual daily check and can be run daily.

From these observations we can conclude that a costeffective and comprehensive lithography area monitoring plan should include macro ADI, µPCM, and µADI at a minimum. Unpatterned wafer monitors are less effective and more frequent monitoring beyond once a day results in test wafer costs that counter the positive impact.

Likewise, the VETM or macro automated hot spot monitor has a small impact, and a frequency beyond twice a week is counterproductive due to the cost of test wafers. It is interesting that for many fabs the standard lithography area defect-related tool qualifications are the unpatterned wafer tests and a hot spot check (manual).

More fabs are implementing µPCM and µADI at the advanced design rule nodes due to the recognized ineffectiveness of traditional methods. From these studies, it is suggested that more emphasis should be placed on the latter methods, including macro ADI for effective lithography area defect monitoring.

References 1 . L. Breaux, Ingrid Peterson, Mer yl Stoller, Dadi Gudmundsson, Raman Nurani, Scott Ashkenaz, Comprehensive C o s t - E ffective Photo Defect Monitoring Strategy, Proceedings ISSM 2001, p. 67 (2001).

2 . Ruj Nasongkhla, J. George Shanthikumar, Raman K. Nurani, Mike McIntyre, Multivariate Control Approach: A Means to Reducing and e rrors in In-line Detection of Yield Excursions, P roceedings ISSM98, p.253 (1998).

3. Raman K Nurani, Ram Akella, Andrzej J. Strojwas, I n - l i n e Defect Sampling Methodology in Yield Management: An Integrated Framework, IEEE Transactions on Semiconductor Manufacturing, vol. 9, No. 4, November 1996.

4 . Raman K. Nurani, Meryl Stoller, Dadi Gudmundsson, J. George Shanthikumar, Evaluating Inspection Strategies Using Advanced Statistical Methods, K L A - Tencor Intern a l Publication (1999).

5 . Trade Mark of KLA-Tencor Corporation.

6 . Ingrid B. Peterson, Defect Reduction Methodology in the Lithography Module, SPIE, p.520 (1999).

7 . Kay Ledere r, Barry Saville, Ingrid Peterson, A u t o m a t e d M i c ro Defect Monitoring for 300mm Lithography, I N T E RFACE 2002, (2002).

8 . Iain Rutherf o rd, Brian Haile, Tony Dibiase, P ro d u c t i o n QC and Tool Monitoring Using an Automated Macro ADI Defect Inspection System, SEMICON/Europa Yield Management Solutions Seminar (2000).

A version of this article originally published in the 2003 SPIE Microlithography proceedings 5041, SPIE Micro l i t h ography Conference, February 2003, Santa Clara, California, USA.

48

Summer 2003

Yield Management Solutions