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Microeconomics of Yield Learning in Semiconductor Manufacturing Kevin M. Monahan, KLA-Tencor Corporation

Simple microeconomic models that directly link yield learning to profitability in semiconductor manufacturing have been rare or non-existent. In this work, we review such a model and provide links to inspection capability and cost. Using a small number of input parameters, we explain current yield management practices in 200 mm factories. The model is then used to extrapolate requirements for 300 mm factories, including the impact of technology transitions to 130 nm design rules and below. We show that the dramatic increase in value per wafer at the 300 mm transition becomes a driver for increasing metrology and inspection capability and sampling. These analyses correlate well with actual factory data and often identify millions of dollars in potential cost savings. We demonstrate this using the example of grating-based overlay metrology for the 65 nm node.

Introduction

Most yield loss is caused by random defects and systematic process errors. For the 130 nm design-rule generation, random defects and parametric process errors are roughly equal contributors to yield loss. At the 90 and 65 nm nodes, parametric losses are expected to dominate. Factory managers will be forced to make an economic trade-off between yield and density in order to achieve minimum die cost. Widespread use of sub-wavelength lithography with resolution enhancement technologies is shrinking both the pattern registration and critical dimension process windows.

Consider a specific example. Currently, overlay yield entitlement is no longer unity due to poor correlation of traditional box-inbox overlay targets with in-device features.

In addition, shrinking design rules are narrowing the overlay process window, creating a looming overlay yield problem for the 65 nm technology node. Models predicting overlay yield loss and subsequent die-cost increases are shown in Figures 1 and 2. The

ITRS 2001 Roadmap has identified the 65 nm generation as a showstopper for overlay, with no known solutions. In this work, we describe an innovative solution using a grating-based target technology that decreases total measurement uncertainty and dramatically increases the yield-relevance of overlay metrology at the 65 nm node.

In Figures 3 and 4, we show the effect of mean-shift and control-loss, the two primary mechanisms for overlayrelated yield loss in semiconductor manufacturing.

Figure 5 shows the overlay control requirements for the 250 to 45 nm technology nodes at constant yield. The contours are approximate solutions to the integral equation (1) In this equation, y is the yield-error curve, E is the overlay error distribution, x is the error, and Ďƒ is the Gaussian width of the error distribution.

The economic consequences of yield loss are readily computed if the factory economic model is known. In Figure 6, we show the particular case for DDR SDRAM in a large factory where a 6-nm overlay error could result in nearly $30 million of revenue loss. The problem is Summer 2003

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F i g u re 1. Overlay yield component versus gate overla y error for the

F i g u re 2. Die-cost increases versus gate overlay erro r, showing explosive

250 to 45 nm technology nodes, calibrated to factory data at 250 nm.

g rowth in die-cost at the 65 nm node due to overlay-related yield loss.

F i g u re 3. Overla y yiel d loss distr ibution resulting from a 6 nm mean

F i g u re 4. Overlay yiel d l oss distribution resulting from a 6 nm loss of

shif t. Pr od uct of yield error curve and shifted Ga us sian error distrib ut ion

c o n t rol. Product of y ield error cur ve and broa dened Ga ussian erro r

derived from ITRS speci fications .

di st rib uti on d eri ved from I TRS specifi cations.

F i g u re 5. Model sho wing 3-sigma overl ay control re q u i rements at

F i g u re 6. 400MHz 256Mb DDR SDRAM revenue los s model for

constant yield, compared to IT RS 2001 spec ifications. Control must be

con sta nt d evi ce overlay off sets. At 6 nm, l osses in a lar ge factor y

tigh ter to guar antee acceptab le yiel ds.

could be as much as $30 mil lion per year.

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F i g u re 7. Tradi tio nal box -in-box tar get s h ave large open areas an d

F i g u re 8. Advanced gr ating targets have l ow sensitivity to CMP and

a re sensitive to CMP-ind uced distor tion and pattern noi se. They exhibit

p a t t e rn noise . At or near the design rul e, they exhibit high device cor-

low device cor relation an d h igh re s i d u a l s .

relation and i mproved model a ccuracy.

that 6 nm offsets from the true device overlay are likely to be common using current box-in-box overlay targets.* These offsets cause small losses now, but they will have devastating yield consequences at the 65 nm node. As shown in Figures 7 and 8, the solution is to change the paradigm for overlay targets and migrate from box-in-box to grating targets. Since the new targets work with the existing overlay metrology platform, the implementation risk is low and the return on investment is in millions of dollars per year.

In the case of parametric process defects, we can show that yield losses are functions of measured parameters such as overlay and critical dimension, or other parameters, such as exposure variation and local defocus, which are observed indirectly in the form of CD excursions. For the remainder of this work, the traditional separation of systematic pattern-transfer and parametric defects (Y s) from random process-induced and contamination defects (Y r) will be ignored in favor of a new parsing based upon knowable causes (yk) and unknowable causes (Y u), so that

A unified yield model for lithography Of course, overlay is only one component of a unified yield model for lithography. The multitude of yieldaffecting process variations can be characterized by the probability that they will result in a non-functional die. We can model this behavior as a product of survival probabilities given by (2) Here, λ is the yield-loss due to defects of type i, n is the number of defects per die of type i, and N is the total number of defect components. The accuracy of the yield model can be improved by identifying those defects with the highest loss potential and those that pose quantifiable economic risk. 1 For lithography, the principal yield components are associated with CD, overlay, macro, and micro defects. *

M. Adel, et al., “ P e rf o rmance Study of New Segmented Overlay Marks for Advanced Wafer Processing” and “Characterization of Overlay Mark Fidelity”, P roc. SPIE, Vol. 5038 (2003).

(3) In this new parsing, yield is fundamentally limited by unknowable causes, e.g., those that lie beyond the metrology capability of a given factory. The correlation of metrology to yield (and hence to profitability) is a strong function of metrology capability. We demonstrate this in the next sections, where we develop a heuristic model linking defect metrology to yield and profitability.

Yield and profitability

The growth of DUV and 193-nm lithography is dramatically increasing and changing the use of inline process control tools. For example, CD and overlay metrology were commonly used in the context of standard statistical process control where an operator or engineer, using a set of well-established rules, decided to change the process based upon a wafer parameter measurement that went beyond process control limits.

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For 130 nm technology and beyond, we are seeing a powerful trend toward both model-based process control and closed-loop control, with a minimum of human intervention. The benefits of advanced process control (APC) include reduced process variation, accelerated shrinks, elimination of send-ahead wafers, fewer monitor wafers, shorter response times, reduced scrap, better tool matching, improved overall equipment effectiveness, faster yield ramps, lower parametric yield loss, better device performance, and easier process transfer from site to site. These benefits translate directly into large improvements in the gross margins for semiconductor products since they simultaneously lower manufacturing cost and increase average selling price.

We can understand these issues by introducing a simplified model2 for profitability, or rate of profit, generated by a semiconductor manufacturing process. Let (4) where R is the factory overhead rate, W is the number of wafer starts, T is the time interval, Y is the yield entitlement limit due to unknowable causes, y the fraction of the entitlement attained, d is the number of dies per wafer, b is the bin yield expressed the fraction of good dies in each performance bin, p is the average selling price per die, C is the manufacturing cost per wafer, i is the product index, and j is the binning index.

This business model represents the gross rate of profit attributable to a factory. It does not include variable costs associated with packaging, marketing, or sales of the product. Some of the basic strategies for maximizing gross profit are discussed below.

The first term represents the fixed costs associated with capital investment, operation, and depreciation of the facility that are independent of capacity utilization. For 130 nm manufacturing and beyond, this investment could include advanced OPC/PSM reticle technology, 193 nm lithography tools, 300 mm wafer handling, copper/low-k interconnect, and factory-wide metrology integration. In the above model, 130 nm factories would lose significant amounts of money before processing a single wafer. The traditional strategy for minimizing the relative contribution of fixed costs is to reduce manufacturing cycle time and operate near maximum capacity. In a supply-limited environment, this means filling the factory with the highest margin products. In a demand-limited environment, this may require loading the factory with some lower margin products. The latter 52

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strategy reduces average margins, but it improves the ratio of profitability to capital investment. The largest single component of the capital investment is currently in lithography, but we expect the copper/low-k component to increase substantially in future generations.

The second term in the profitability equation above represents the rate of profit, adjusted for manufacturing cost per wafer. This variable cost arises from materials, consumables, and other expenses that scale with the number of wafers processed. Offsetting this cost, is the factory revenue, which is calculated from the average selling price per die, scaled by dies per wafer, wafer starts, metrology-limited yield, device yield, and bin yield. Large investments in lithography are currently being used to improve yield and to reduce cost per die by accelerating shrinks; but shrinks are ineffective without a commensurate decrease in process variation to accommodate tighter focus-exposure windows, reduced overlay budgets, and greater sensitivity to random macro and micro defects. Both systematic and random defects can collapse lithographic process windows at the 130-nm technology node and beyond, resulting in long and costly yield ramps. In this paper, we develop a heuristic model for metrology and sampling that can help define the strategy for ramping yield in development and for continuously improving baseline yield in production. We have already discussed the methodology for containing yield excursions in previous work.3 Process tools add value by generating wafer output at a given level of yield, thereby contributing to the “topline” revenue. Defect metrology tools, on the other hand, recover value by increasing yield without increasing costs (C), other than those associated with the metrology itself. In this sense, the benefits of metrology go directly to the “bottom-line” profitability of the semiconductor manufacturing enterprise. We have shown previously that metrology in the factory should be optimized using stochastic models.2 However, the dynamics of metrology, yield, and profitability in the factory are best understood using heuristic response models that are chosen to fit the results of more rigorous stochastic models or actual factory data.

For the single-product response model, we make the simple assumption that, starting at 1-y0, killer defects decline by the same fraction with each cycle of learning n, so that the effectiveness of learning declines exponentially. The incremental cost due to metrology is assumed to scale linearly with the number of cycles of learning, in accord with CoO models. If the capability and cost of metrology scale with α and β, respectively,

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then substituting into the equation for profitability gives us an expression for the value recovered by metrology: (5) In the limit where the metrology-limited yield entitlement (Y) approaches unity, the value recovered is just the improvement in the gross margin of the product.

The number of cycles of learning required to reach peak profitability is given by: (6) We can make a number of qualitative observations with regard to metrology-driven yield improvement, some of which are highly intuitive: • In development, where starting yields are low, the need for metrology is high for all products. Within a single process generation, the optimal allocation of metrology resources is time-dependent.

• In production, high value per wafer and relatively low transfer yield increases the need for metrology (microprocessor). Within a process generation, the optimal allocation of metrology resources is productdependent.

• If metrology capability and cost are scaled proportionately (i.e., if α/β is constant), the design of next-generation metrology tools (N+1 and N+2) will be dominated by the requirement for capability.

The negative impact of cost on value recovery is greatest when the expected revenue per wafer is low (memory).

• Value recovery is greatest when metrology tools are fast (low β), sensitive (high α), and responsive to all yield-limiting defect types (high Y). In virtually all cases, these are conflicting requirements that argue for multiple-tool metrology solutions. An optimized multi-tool solution can reduce cycle-times, drive steeper yield ramps, and achieve higher yield entitlements.

The above results make a strong case for increasing the variety and extending the capability of metrology tools in the semiconductor manufacturing process. Economic drivers are behind a number of observable trends. For example, many semiconductor manufacturers are now

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adding e-beam-based wafer inspection to the complement of optical inspection tools in their factories. Others are augmenting traditional optical film-thickness metrology with advanced C-V metrology that measures both the electrical thickness and the contamination of gate dielectrics. In lithography, CD and overlay metrology is increasingly used for closed-loop, model-based process control. In the case of traditional defect metrology, automated defect classification and adaptive sampling are being used to minimize metrology costs, and SEMbased review tools are replacing optical tools.

Results and discussion

In Figures 9 to 14, the value-recovery model shows gross margin improvement (Y=1) for two virtual products: commodity memory and high-end microprocessors.

These products are assumed to have ASPs of $5 and $500 per die, respectively. The respective densities are 2000 and 500 dies per 300 mm wafer. Development yields are assumed to start at zero, while production yields at transfer are scaled to account for chip size and product complexity. In Figures 9 and 10, metrology capability and cost are estimated for both current (N+0) and future (N+2) generations of metrology equipment.

Capability and cost are assumed to double while going from generation N+0 to N+2. Capability is scaled in inverse proportion to die density, decreasing as chip size increases.

In the case of high-volume production, the model results are strongly differentiated by product type. For commodity memory on 200 mm wafers (Figure 9), the achievable yield is limited primarily by cost. In the case of commodity memory on 300 mm wafers (Figure 10), the additional value per wafer justifies a higher level of metrology (e.g., N+2), resulting in faster baseline yield improvement and a higher yield entitlement (nearly 2 percent higher in this case). Larger gains will occur as commodity memory manufacturers migrate to embedded logic, DSP manu- facturers develop system-on-chip products, and microprocessor companies compete for the highestASP market segments.

Due to higher average selling price, larger chip size, and lower transfer yield, the economic model for microprocessors is strikingly different. Substantial investment in advanced metrology capability may be justified well into high-volume production. Microprocessor margins are extremely sensitive to metrology capability and relatively insensitive to cost, justifying more cycles of learning, as shown for the “line monitor” case in Figure 11.

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F i g u r e 9. Commod ity memory — 200 mm wafers .

F i g u re 10. Commo dity memory — 30 0 mm wafers .

F i g u re 11. Integrat ed met rology — micro p ro c e s s o r.

F i g u re 12. Integrated metrology — memory.

F i g u re 13. Copper yield ra mps — logic c ompanies.

F i g u r e 14. Ca lib rated model — d iverging yields.

Taken as a whole, this analysis brings up some significant economic issues:

threat for smaller semiconductor manufacturers that cannot afford to build 300 mm factories.

• Assuming optimized metrology capability, 300 mm factories should enjoy not only economies of scale but also higher yields and gross margins. This creates an opportunity for the larger silicon foundries and a

• In the case where multiple products are manufactured using a similar process, monitor reduction strategies intended for the lowest-value products can lead to unacceptable economic risk. Ideally, sample plans

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should increase for high-value products manufactured on 300 mm wafers.

• In the case where multiple factories are equipped identically (copy exact), the benefits of metrology innovation may never be realized, severely limiting the ultimate yield entitlement. Ideally, 300 mm factories should be designed to support seamless upgrades of existing metrology equipment and the introduction of newer metrology tools, with minimal disruption to the process and material flow (copy smart). Given the high cost of labor and the potential for operator error, these introductions may require remote e-diagnostics, e-applications, and e-training for both metrology and process tools.4 Multiple tool solutions for process module control

Our models generally support multiple-tool solutions for the optimization of yield and profitability. Most copper lines, for example, use a combination of darkfield, brightfield, and e-beam wafer inspection to accelerate yield ramps. In the litho module, a combination of macro inspection and brightfield micro inspection can sometimes be more cost-effective than a single-tool darkfield inspection. With the further segmentation of metrology tools into stand-alone, clustered, integrated, and in-situ systems, the optimal metrology strategy seems less clear, until we consider the economic impact of these technologies.

Integrated Metrology Consider the case of integrated metrology. We assume that these systems will have lower sensitivity, respond to fewer defect types, but enjoy higher sampling rate in comparison with traditional stand-alone line monitors.

The value-recovery calculations for production of microprocessors and commodity memory are shown in Figures 11 and 12. In this example, transfer yields start at 0.60 and 0.90, respectively. Based on results for integrated, line-monitor, and combined solutions, we can make qualitative observations about the use of integrated metrology for improvement of baseline yield: • In the case of microprocessors, integrated metrology appears to enhance the effectiveness of more sensitive, stand-alone line monitors by freeing them for more demanding applications. The wafer-to-wafer sampling capability of integrated tools reduces exposure to gross yield excursions.

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• The use of integrated metrology as a “single-tool” solution creates unacceptable economic risk, especially in a high-volume ramp, since many integrated tools are “blind” to a large fraction of killer defects. In general, factories would not achieve entitlement margins and would risk exposure to non-root-causable yield excursions.

• In a supply-limited market, silicon foundries that currently enjoy a “wafers-out” business model, are likely adopters of integrated metrology. However, in a demand-limited market, foundries that do not acquire the most capable metrology tools, will lose customers to foundries with efficient “dies-out” business models or “wafers-out” business models with predictable yield boundaries. Yield prediction is critical to meeting production requirements without creating excess inventory.

Copper Yield Ramps Copper pilot lines provide another example of success with multiple-tool solutions. Most copper lines use a combination of darkfield, brightfield, and e-beam wafer inspection for tool monitors, station monitors, line monitors, and engineering analysis. This “use-case” scenario illustrates a more general trend toward complete process-module control solutions that include multiple metrology tools, 5 networked analysis software, and optimized yield strategies.

The normalized copper yield ramps of several leadingedge semiconductor companies are shown in Figure 13.

In Figure 14, we use some of this data to calibrate our microeconomic model, thereby enabling a root-cause analysis of the yield divergence between Companies A and F. By fitting the model first to Company-F data and then forcing it to achieve Company-A yield levels, we identified the likely causes of divergence. The model parameters indicated that Company A had newer, more capable metrology tools and significantly greater capacity, matching our audit of actual installations.

Adding metrology capability goes beyond upgrading or replacing older optical tools. E-beam inspection, for example, is not only more sensitive to many physical defect types but is also uniquely responsive to new classes of buried electrical defects (e.g., voids and incomplete vias) that are frequently observed in the copper damascene process. As a consequence, e-beam inspection increases the aggregate metrology capability (α and Y), enabling shorter development cycle-times, accelerated yield learning, and higher yield entitlements.

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F i g u re 15. Effect of dies per wa fer — memor y.

F i g u re 16. Ef fect of sen sitivity/capacity d efic its .

Some of this discussion applies equally to the challenges of the 300 mm-wafer and 130 nm-technology transitions.

In the case of memory, the advantages of shrinking design rules and increasing wafer size are fairly obvious, as shown in Figure 15. The economic leverage of metrology is especially evident with the assumption of relatively low transfer yield (0.30) and rapidly eroding average selling price (-30 percent CAGR). In Figure 16, we show the impact of insufficient metrology capability and/or capacity for 300 mm wafers in the 130 nm-technology generation. Optimized metrology clearly has the potential to extend the cycle of profitability for memory and other cost-sensitive products.

(Equation 6). A doubling of capability, for example, could cut development cycle-time in half. In Figure 17, we show the four key areas of lithographic process module control where metrology capability is important.

These areas are micro, macro, CD, and overlay defect metrology, respectively.

Dominance of metrology capability

Perhaps the most striking prediction of the heuristic model is the dominance of metrology capability when capability and cost are scaled proportionately. With ι/β and all other factors held constant, the number of cycles of learning required to achieve optimum profitability will be inversely proportional to metrology capability

The range of micro defects6 in lithography is represented in Figure 18. For a relatively mature process with small randomly distributed defects, the yield-loss function tends to follow the Poisson model: (7) Here, D is the density of killer defects and A is the critical area. Capability extension in micro defect metrology is focused on increasing defect sensitivity and pixel throughput (speed). Consider the case of a generic brightfield inspection tool. If inspection wavelengths

F i g u re 17. After-develop inspection (ADI) in the lithograph y module

F i g u re 18. Examples of p rimar y micro defects that can affect yield in

can b e parse d into four types.

a g g ress ive lithography.

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F i g u re 19. Examples of th e primar y mac ro d efects tha t can aff ect yield in

are scaled down from 500 to 350 and 250-nanometers, respectively, the image pixel sizes must be scaled accordingly to achieve improvements in sensitivity. Each successive generation will require a two-fold increase in pixel throughput to sustain the same wafer throughput.

A similar argument might be applied to darkfield laser-scanning tools, where sensitivity improves with smaller spot size. Consider the case of a generic darkfield inspection tool. If minimum spot sizes are scaled from 5.0 to 3.5 and 2.5 micrometers, respectively, the scanning speed must increase two-fold for each generation. In the transition to 300 mm wafers, both the brightfield pixel throughput and the darkfield scanning speeds must double again to sustain equivalent wafer throughput.

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of clustering, while a value greater than 50 produces a yield-loss function that closely approximates the Poisson model.7 Capability extension in macro defect metrology is focused on defect sensitivity and automation (speed).

Consider the case of a generic macro inspection tool. If sensitivity is improved from 100 micrometers (approximate human-eye capability) to 50 and 25 micrometers, respectively, we can expect to detect a much larger number and variety of defects more consistently than we could with a human operator. Since typical line yield aggr essi ve lithography. improvements are on the order of one percent or less, our heuristic model would suggest that macro tools must be both inexpensive and fast in order to substantially increase gross margins. In the transition to 300 mm wafers, macro tools that utilize whole-wafer scanning may have an advantage in sustaining high wafer throughput at full sensitivity. In cases where operator access is restricted because of factory automation, advanced macro inspection may become a clear requirement.

Capability extension in overlay metrology is focused on enhancing tool performance and improving correlation

The range of macro defects in lithography is represented in Figure 19. For a relatively immature process with large clustered defects (e.g., many defects associated with resist coating, resist development, scratches, or gross contamination), the yield-loss function tends to follow the negative binomial model: (8) Here, δ is the cluster factor. A value close to unity indicates a high degree

F i g u r e 20. Die-level an alysi s of overl ay error sh ows cor relation wi th man ufacturin g yiel d l oss.

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F i g u re 21. Wa f e r-to-wafer analysis o f CD error showing a systema tic drif t th at affected bin yield.

to yield. The example of overlay (OL) defectivity8 is shown in Figure 20. This die-level overlay analysis was essential to separate overlay-induced yield losses that were confounded with other systematic yield losses, particularly those with a radial dependence across the wafer. Note that typical overlay-induced yield losses9 may be on the order of a few percent. If the losses are small and well-behaved, they can be expressed using Taguchi’s quadratic loss function:10

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dimension (CD) defectivity is shown in Figure 21. This wafer-level analysis of CD data shows that a combination of feed-back and feed-forward techniques (FB and FF) can be used to shift the mean and reduce the spread of gate CDs in microprocessors, thereby improving speed and average selling price. The strategy is to squeeze CD distributions as close to the gate-leakage threshold as possible without incurring unacceptable losses in device yield. In such cases, the yield loss function is single-sided and approaches unity for small gate dimensions. It can be approximated by means of logistic regression11 if we let: (10)

where X is the critical dimension, X0 is the yield-loss threshold, and a is a constant determined by the regression fit. To achieve a better fit, we can introduce more and higher-order terms on the right-hand side of Equation 10.

(9) where X is the critical overlay parameter, X0 is the optimum overlay value, and a is the scaling constant determined by the regression fit. To account for asymmetric behavior, such as that observed in Figure 12, we can introduce higher-order terms. Further, the above analysis can expand to include multiple regression on more complex models.

Capability extension in CD metrology is focused on enhancing tool performance, improving correlation to yield, and utilizing data more efficiently. An example of critical58

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F i g u re 22. CD defect signature analysis can impro ve the aggregat e CD metrology cap abi lity.

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F i g u r e 23. Examp le o f i ncreased capability (Îą and Y) provided by sp ectroscopic scattero m e t r y or SCD. SCD is a relatively new technology and its capability is incre a s i n g .

Increasing metrology capability

Increasing the capability of metrology in a factory can be accomplished by developing new tool technology, by improving the analysis of data, and by creating a higher level of integration with process tools. The parameter Îą in Equations 5 and 6 is clearly a function of defect detection, classification, analysis, and correction strategies.

If we take CD metrology as an example, the addition of profile and image correlation on CD SEMs has dramatically increased the ability of these tools to influence yield, principally by allowing detection of excursions in profile and shape that are not necessarily reflected in CD data. Further, the CD data itself can be analyzed using generalized ANOVA models12 to detect excursions with predetermined spatial signatures (Figure 22). This analysis is especially important for de-confounding spatial from temporal excursions.

More recently, the development of spectroscopic CD scatterometry has enabled the measurement of critical dimension, profile, and height of features in grating targets (Figure 23). The long-term stability of these measurements can meet ITRS lithographic metrology requirements for the 45 nm semiconductor manufac-

turing generation. In addition, SCD is non-destructive and suited for metrology on sensitive materials, such as 193 nm resists. Advanced process control, with standalone or integrated SCD, benefits from the simultaneous availability of profile and height information.

Beyond improving the metrology tools and analysis software, aggregate metrology capability can be increased by creating higher levels of integration with process tools and improving correlation to device performance.

Metrology integration does not necessarily imply a physical connection between metrology and process tools, although this is one means of implementation. In Figure 24, for example, we show a case of metrology integration for a stand-alone overlay metrology tool. • In the off-line case, using monitor wafers, factory-wide systems can link CD and overlay data to analysis software that provides automated CD process window matching and overlay analysis, respectively. The key economic benefit is removal of in-situ focal and registration tests from $20-25M photo modules to less expensive metrology tools. Another benefit is more accurate and precise monitoring of focal and registration data due to improved metrology capability.

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F i g u re 24. Metrology integration i ncreases aggregate cap ability. The Arc her AIM over lay tool in a factory n etwork uses device-cor relat ed gra ting tar gets an d comp rehensive analysis to r educe total measurement unc ert a i n t y, enabling overlay control at the 65 nm technology nod e.

• In the inline case, using product wafers, factory-wide systems link CD and overlay tools to analysis software and advanced process control applications within an APC framework (e.g., SEMI-E93 Specification).

Through the framework, adjustments are fed back or forward to the process tools to maintain CD and overlay control. The key economic benefits are improved yield for all products and improved speed binning for microprocessors.

Conclusions

In this work, we have introduced a simple microeconomic model that links metrology, yield, and profitability in semiconductor manufacturing. Our core findings are summarized below: • Our grating-based overlay example clearly showed that yield-relevant metrology (high Y) is a critical enabler for technology node transitions. Without good device correlation, “corrections” fed to APC systems could actually generate process error and subsequent yield loss.

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• The dramatic increase in value per wafer at 300 mm justifies an increase in metrology capability, despite a concomitant increase in metrology cost. The value recovered by metrology depends on process maturity, product type, metrology capacity, and metrology tool generation.

• The microeconomic model strongly supports optimized, multiple-tool solutions for improvement of yield and profitability. Integrated monitors, for example, can enhance the effectiveness of stand-alone monitors but are generally not viable as the sole metrology solution in a factory.

• We have shown that success in yield ramps and technology node transitions depends on yield-relevant process control capability (high α and Y) despite higher levels of metrology investment (higher β).

• The aggregate metrology capability of a factory can be increased by developing new metrology tool technology, by improving the analysis of data, and by creating a higher level of integration with process tools.

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Acknowledgements

We would like to acknowledge the contributions of Sam Harrell, Tom Long, Scott Ashkenaz, Yosef Avrahamov, Arun Chatterjee, Xuemei Chen, Georges Falessi, Greg Gray, Matt Hankinson, Eric Kent, Sung Jin Lee, Marius Lupan, Amir Lev, Ady Levy, John Miller, Yoel Moalem, Raman Nurani, Ingrid Peterson, Moshe Preil, Richard Quattrini, Michael Richie, Mike Slessor, Meryl Stoller, Craig Stone, Umar Whitney, and Aaron Zuo. A version of this article originally published in the 2003 SPIE Microlithography proceedings 5043, SPIE Microlithography Conference, February 2003, Santa Clara, California, USA. References 1 . K. M. Monahan, P. Lord, C. Hayzelden, and W. Ng, “An Application of Model-based, Lithographic Pro c e s s Control for Cost-effective IC Manufacturing at 0.13 micron and Beyond”, P roc. SPIE, Vol. 3677, p. 435 (1999).

2 . K. M. Monahan, S. Ashkenaz, X. Chen, P. Lord, M. Merrill, R. Quattrini, and J. Wiley, “Accelerated Yield Learning in A g g ressive Lithography”, P roc. SPIE, Vol. 3998, p. 492 (2000).

3 . R. Williams, D. Gudmundsson, K. M. Monahan, R. Nurani, M. Stoller, and J. G. Shanthikumar, “Optimized Sample Planning for Wafer Defect Inspection”, P roc. ISSM’99, p. 43 (1999), Santa Clara, Californ i a .

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4 . M. Locy, “On-line Diagnostics as a Key Part of Pro c e s s Module Contro l ” , P roc. ISSM 2000.

5 . C. Hayzelden, et al., “ P rocess Module Control for Low-k Interlevel Dielectrics”, P roc. ISSM 2000.

6 . A. L. Swecker, A. J. Strojwas, A. Levy, B. Bell, and S. Ashkenaz, “Detection of Critical Process Defects Using In-line Bright-field Inspection Technology”, Proc. ISSM’98, p. 261 (1998), Tokyo, Japan.

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60 (1990).

8 . M. E. Preil and J. F. M. McCormack, “A New Appro a c h to Correlating Overlay and Yield”, Proc. SPIE, Vol. 3677, p. 208 (1999).

9 . R. Martin, X. Chen, and I. Goldberg e r, “Measuring Fab Overlay Programs”, Proc. SPIE Vol. 3677, p. 64 (1999).

1 0 . D. M. Byrne and S. Taguchi, “The Taguchi Approach to Parameter Design”, Quality Pro g ress, p. 19 (1987).

1 1 . P. McCullagh and J. A. Nelder, Generalized Linear Models, 2nd Edition, Chapman and Hall, London (1989).

1 2 . R. C. Elliott, R. K. Nurani, S. J. Lee, L. Ortiz, M. Pre i l , J. G. Shantikumar, T. Riley, and G. Goodwin, “Sampling Plan Optimization for Detection of Lithography and Etch CD Process Excursions”, Proc. SPIE, Vol. 3998, p. 527 (2000).

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