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Gate Process Control

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Profiling the Gate and Improving Speed J. Scott Hodges, Yu-Lun (Chris) Lin, Dale R. Burrows, and Ray H. Chiao, Texas Instruments Incorporated Robert M. Peters, Srinivasan Rangarajan, Kamal Bhatia, and Suresh Lakkapragada, KLA-Tencor Corporation

Tighter control of gate profile parameters at 130 nm and below is the key to maximizing product yield and transistor per formance. Furthermore, the ability to correlate physical inline profile measurements taken at gate patterning process steps to back end of line device parametric test results enables semiconductor manufacturers to accurately screen out-of-spec product early in the process flow and minimize the cost per good die. Historical methods of inline metrology — low voltage scanning electron microscopy, atomic force microscopy, and electrical critical dimension metrology all face limitations with regards to precision, correlation, and throughput. Texas Instruments’ DMOS 6 300-mm fab utilized spectroscopic ellipsometry-based CD metrology for inline process control and product disposition at the gate lithography and etch process steps on 130 nm generation logic devices.

Introduction

The ability to control the cross-sectional profile of polysilicon gate structures on semiconductor devices is paramount to maximizing product yield and transistor performance.

Tighter control of gate profile parameters leads to a tighter distribution of transistor speeds, resulting in more optimized and consistent device performance. The performance of the transistor is only fully confirmed during electrical testing after interconnect and metallization have been completed. However, the process steps that define the physical dimensions of the polysilicon gate occur much earlier in the process flow. Typically, there is a lag time of days, or even weeks, between the gate patterning steps, and electrical test of the transistor performance. As a result, the ability to accurately measure physical profile characteristics of the gate inline at the patterning steps, and subsequently correlate those measurements to back-end electrical test results, is critical for ensuring proper disposition of production material, in order to maximize yield and minimize overall cost per good die. This importance is underscored by the significant increase in the number of chips on today’s 300-mm wafers.

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For the past several years, the predominant metrology methods used for inline control of the gate process have been: 1) top-down measurement of the width (referred to as critical dimension, or CD) of the polysilicon gate using a low-voltage scanning electron microscope (CD SEM); and 2) Electrical CD (ECD) measurements conducted via a parametric test system immediately after gate etch completion. Both methods have proven to give precise measurement with relatively high throughput. However, both methods are limited in their ability to provide metrology or process characterization beyond the one-dimensional CD value.

Other metrology techniques such as atomic force microscopy (AFM) and cross-sectional tunneling electron microscopy (TEM) are able to provide full twodimensional profile metrology with requisite precision for proper control of advanced gate patterning processes.

However, throughput for both techniques is inadequate to allow for proper statistical sampling necessary to control a volume manufacturing line. TEM has the additional drawback of being a destructive process.

This article describes the use of a CD metrology technique based on spectroscopic ellipsometry to provide fast, accurate, and precise two-dimensional profile information on polysilicon gate structures. This metrology technique, which is the basis of KLA-Tencor’s SpectraCD™, is cur-

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rently being utilized for inline process control and product disposition, at the gate lithography and etch process steps, on 130 nm generation logic devices manufactured in Texas Instruments’ DMOS6 300 mm wafer fabrication facility. A brief description of the SpectraCD measurement theory and measurement solution for both gate litho and etch will be provided. Precision results will be presented for CD, height, and profile sidewall angle that demonstrate the capability of SpectraCD to control a 130 nm node process.

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F i g u re 1. Schematic of spec troscop ic ell ipsometr y-based CD ( Spectra CD) measur e m e n t .

Correlation results of inline gate etch SpectraCD measurements, to post-metallization transistor drive current (IDrive) will be shown. A comparison between SpectraCD and existing inline electrical CD measurements was completed, and the ability of SpectraCD to provide gate etch process control will be demonstrated.

By coupling full two-dimensional profile information with high throughput, SpectraCD has also proven to be a valuable tool for detecting process excursions. Examples of process excursions, ranging from etch profile changes to gate oxide punch-through, have been detected by SpectraCD. Spectroscopic ellipsometry based measurement technique

The SpectraCD measurement technique based on spectroscopic ellipsometry is described below. A typical setup for a spectroscopic ellipsometer is shown in Figure 1.

Light from a broadband light source is reflected off the sample of interest. The polarizer and the analyzer determine the state of polarization of the incident and the reflected beams respectively. A prism separates the wavelengths in the reflected light and the intensity is measured using an array detector. To conduct a typical ellipsometry measurement, the intensity of the elliptically polarized light is measured for the wavelength range from 220 nm to 800 nm, at different orientations of the polarizer or analyzer. Ellipsometry offers both amplitude and phase information, in relation to reflectometry which only provides amplitude information.

Spectroscopic ellipsometry technique is widely used in the semiconductor industry for thin film metrology. In the SpectraCD technique the sample of interest is the grating targets added to the wafer, usually in the scribe

line. The grating targets are comprised of line/space features of uniform period, with the linewidth (CD) and period designed to represent the physical device feature that is being controlled.

A typical SpectraCD measurement process consists of an offline library generation process, and an on-tool profile measurement using the library. The offline library generation involves using the process information (dispersion properties and nominal thickness of all films in the grating region) and the grating information (pitch, nominal CD, HT) to create a theoretical model of the grating geometry. The library is a compilation of theoretical spectral signatures, obtained by varying the grating parameters. This library is then linked to the recipe on the metrology tool. As the gratings are measured, the experimental spectra are compared against the theoretical spectra in the library (Figure 2).

The best match between the measured spectra and the theoretical spectra determines the parameter values that best describe the grating.1 Measurement models

A schematic representation of the measurement models at both the gate litho and gate etch steps are shown in Figures 3 and 4. For the gate litho process, the structures of interest are resist lines/spaces — which sit on top of an anti-reflective coating layer — on top of blanket polysilicon, gate oxide, and bulk silicon (Figure 3). For gate etch, the structures of interest are etched polysilicon lines/spaces on top of gate oxide, and bulk silicon (Figure 4). In both cases, the lines in the grating structures were modeled as single trapezoids in the library. The library generation time for both the cases was less than half an hour. Cross-section TEM analysis of representative gratings confirmed that the single simple trapezoid model closely approximates the Summer 2003

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Poly-Si Gate Ox Silicon

Figure 4. Schematic of gate etch trapezoid model.

litho and etch layers, the wafers measured were patterned with a focus-exposure (FE) matrix encompassing a process window of Âą20 percent from nominal. A total of 16 fields per wafer (see Figure 5), and two sites per field were measured. One site was a grating from a doped region of polysilicon; the other site was a grating from an undoped region of polysilicon.

Figure 2. SpectraCD measurement and librar y match.

actual resist and etched poly profiles. Gratings with line:pitch ratios varying between 1:3 and 1:7 were used to monitor the litho and etch processes. The aspect ratios on the lines in the gratings are approximately 2.3:1 for gate litho, and approximately 1.6:1 for gate etch.

During the two-week period, a five-cycle short-term dynamic precision test was repeated six times for a total of 30 measurements at each site. The variance of each set of 30 measurements was calculated, and then the average variance for the 16 doped, 16 undoped, and the combined 32 sites were calculated. From these values, a pooled 3 sigma was calculated as three times the square root of the mean variance, for each of the profile parameters.

Results are shown in Figure 6 and Figure 7. For both the gate litho and gate etch processes, precision on CD and height parameters is well below 0.5 nm, and

Precision results

In this section we are going to present the long-term precision results generated by measuring the same wafers repeatedly over a two-week period. For both the

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Poly-Si Gate Ox Silicon

- Focus + Figure 3. Schematic of gate litho trapezoid model.

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Figure 5. Wafermap layout for long-term precision testing.

- Exposure +

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F i g u re 6. Gate li tho lon g-t er m precision resul ts.

F i g u re 7. Gate etch l ong -term p recision re s u l t s .

precision on sidewall angle is below 0.1 degree. These precision values generate precision-to-tolerance ratios (P/T) well below 0.1, providing sufficient capability to control a 130 nm node process.

measure a test structure in the scribe that simulates the actual device. While ECD has historically provided good correlation to I Drive, at the 130 nm process node, some challenges have been encountered with maintaining this correlation. While ECD provides relatively high throughput compared to other metrology techniques, it does face some limitations. Therefore, there is motivation to find a viable metrology alternative that provides better correlation to I Drive, with higher throughput.

SpectraCD correlation to drive current

One of the most important parameters for determining device performance is the transistor drive current (IDrive).

IDrive cannot be measured until after metallization process steps have been completed. However, one of the primary contributors to determining IDrive is the physical gate length defined by the width of the polysilicon line (Gate CD). Therefore, the ability to correlate a physical measurement of gate length measured inline at post-gate etch, to IDrive, is critical to provide meaningful process control and product disposition that will maximize yield and minimize cost-per-good-die.

Figures 8 and 9 show the results of a study comparing the correlation of ECD and SpectraCD measurements to IDrive. The limitations of the ECD measurement are clearly seen. SpectraCD shows a much higher level of correlation to I Drive (0.67-0.68), for both minimum contacted pitch (MCP) structures and isolated structures.

The slope and correlation of SpectraCD versus IDrive demonstrate that I Drive can be controlled and modified through the use of inline SpectraCD measurements.

Historically, electrical measurements of the gate CD have provided the best correlation to IDrive. The ECD measurement is completed immediately after the gate etch process step, using a parametric test system to

Figures 10, 11, and 12 reflect an actual production case, further demonstrating the capability of SpectraCD to correlate and affect I Drive distribution. Figure 10

F i g u re 8. Correl ation of electrical C D to I D r i v e .

F i g u re 9. Correl ation of SpectraCD BCD t o I D r i v e .

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F i g u r e 10. Gate etch Sp ectraCD SPC char t .

F i g u re 11. Gate etch ECD SPC Char t.

is a production SPC chart for SpectraCD gate etch measurements. A shift of roughly two percent in the CD distribution is seen to the right of the vertical line on the chart. Figure 11 shows the corresponding ECD SPC chart for the same production lots. No shift in CD is picked up by ECD. Figure 12 is the corresponding chart showing I Drive distribution for the same group of lots. The two percent shift in SpectraCD measurements correlates to roughly a five percent shift in IDrive.

detection and response time for process excursions.

Process excursion detection with SpectraCD

An additional benefit seen with the use of SpectraCD, is its capability to detect a variety of process excursions. The ability to generate full two-dimensional profile information has provided additional sensitivity to process changes.

The high throughput of SpectraCD (<4 seconds/site move-acquire-measure time) allows for a significant increase in production sampling. This leads to faster accumulation of statistically significant data, which reduces

Sidewall angle and CD shift detected after etch chamber PM One example is shown in Figure 13 below. After routine preventative maintenance (PM) was performed on an etch chamber, SpectraCD SPC charts for both sidewall angle and CD parameters reflected a two percent shift in the process means from the pre-PM baseline condition.

Due to the high sampling rate afforded by SpectraCD, the excursion was reliably detected within a handful of product lots. TEM analysis confirmed the process shift seen by SpectraCD. Follow-up maintenance was performed on the etch chamber to return the process to its baseline.

Prior to SpectraCD implementation, this process excursion would have almost certainly gone undetected for a longer period of time. Figure 14 highlights where ECD did not detect any shift in the process. Furthermore, while the process shift was confirmed by using TEM, if TEM alone was used, confirmation and reaction time to the excursion would have been greatly increased due to turn-around-time and sampling rate limitations of TEM.

Gate oxide punch-through detection

F i g u r e 12. nMOS I D r i v e c h a rt reflecting 5 percent s hif t.

F i g u r e 13. Etc h chamber post-PM excursion detected b y SpectraCD.

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The ability to detect gate oxide punch-through is an area where SpectraCD has demonstrated unique capability.

Gate oxide punch-through is a yield-limiting defect that has proven difficult to detect in low levels using optical and/or CD SEM inspection. In the example shown

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Conclusions

F i g u r e 14. Etc h chamber post-PM excursion not detected by ECD.

in Figure 15, very low levels of gate oxide punch-through were detected by monitoring the goodness-of-fit (GOF) of the SpectraCD measurements.

When the measured spectrum from a grating target is compared against the theoretical library, SpectraCD generates a GOF value, which mathematically represents how closely the measured spectrum matches the solution from the library. The small holes in the gate oxide underneath the grating target scatter the incident SE beam, introducing random noise into the measured spectra, leading to a decrease in GOF. The plot in Figure 15 shows a clear decrease of 0.020.06 in GOF from a mean value that is typically stable to within ±.01. Subsequent CD SEM inspection of the grating targets highlighted the small holes representing the gate oxide punch-through.

As a result of the reliable method of detection with SpectraCD, an inline CD SEM inspection has been eliminated, saving cost without sacrificing reliable detection of punch-through defects and proper disposition of production material.

In this article we have presented the results obtained from the SpectraCD spectroscopic ellipsometry-based metrology tool being utilized at the Texas Instruments DMOS6 production facility for inline process control and product disposition at the gate lithography and etch process steps. The results demonstrate the capability of this technique in providing accurate and precise profile information of the polysilicon gate structures. The long-term precision results for the gate litho and etch structures, show that SpectraCD is capable of meeting the precision requirements for the 130 nm node of the International Technology Roadmap for Semiconductors.

A critical parameter in determining device performance is the transistor drive current, which can be measured only after the metallization process steps have been completed. SpectraCD measurements of the grating target in the scribe line show good correlation with the transistor drive current, thus providing an inline measurement technique at the gate etch step, which can be used to perform effective process control and product disposition. Process excursions caused due to the etcher PM and oxide punch-through were captured by SpectraCD measurements, which would have otherwise gone undetected for a longer period of time.

References 1. J. Allgair, D. Benoit, M. Drew, R. Hershey, L. Litt, P. Herrera, U. Whitney, M. Guevremont, A. Levy, S. Lakkapragada, “Implementation of Spectroscopic Critical Dimension (SCD™) for Gate CD Control and Stepper Characterization,” P roceedings of SPIE, Volume 4344-57, March 2001.

2. H. Tompkins, W. McGahan, S p e c t roscopic Ellipsometry and Reflectometry, John Wiley & Sons, 1999.

A version of this art i c l e originally published in the 2003 SPIE Micro l i t h o g r aphy proceedings 5038, S P I E Mi c r o l i t h o g r a p h y Conference, February 2003, Santa Clara, Calif o rnia, USA.

F i g u re 15. SpectraCD GOF plot with corr esponding SEM images conf irmin g detectio n of gate oxid e punch-thro u g h .

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