Gate Process Control
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Profiling the Gate and Improving Speed J. Scott Hodges, Yu-Lun (Chris) Lin, Dale R. Burrows, and Ray H. Chiao, Texas Instruments Incorporated Robert M. Peters, Srinivasan Rangarajan, Kamal Bhatia, and Suresh Lakkapragada, KLA-Tencor Corporation
Tighter control of gate profile parameters at 130 nm and below is the key to maximizing product yield and transistor per formance. Furthermore, the ability to correlate physical inline profile measurements taken at gate patterning process steps to back end of line device parametric test results enables semiconductor manufacturers to accurately screen out-of-spec product early in the process flow and minimize the cost per good die. Historical methods of inline metrology — low voltage scanning electron microscopy, atomic force microscopy, and electrical critical dimension metrology all face limitations with regards to precision, correlation, and throughput. Texas Instruments’ DMOS 6 300-mm fab utilized spectroscopic ellipsometry-based CD metrology for inline process control and product disposition at the gate lithography and etch process steps on 130 nm generation logic devices.
Introduction
The ability to control the cross-sectional profile of polysilicon gate structures on semiconductor devices is paramount to maximizing product yield and transistor performance. Tighter control of gate profile parameters leads to a tighter distribution of transistor speeds, resulting in more optimized and consistent device performance. The performance of the transistor is only fully confirmed during electrical testing after interconnect and metallization have been completed. However, the process steps that define the physical dimensions of the polysilicon gate occur much earlier in the process flow. Typically, there is a lag time of days, or even weeks, between the gate patterning steps, and electrical test of the transistor performance. As a result, the ability to accurately measure physical profile characteristics of the gate inline at the patterning steps, and subsequently correlate those measurements to back-end electrical test results, is critical for ensuring proper disposition of production material, in order to maximize yield and minimize overall cost per good die. This importance is underscored by the significant increase in the number of chips on today’s 300-mm wafers. 6
Summer 2003
Yield Management Solutions
For the past several years, the predominant metrology methods used for inline control of the gate process have been: 1) top-down measurement of the width (referred to as critical dimension, or CD) of the polysilicon gate using a low-voltage scanning electron microscope (CD SEM); and 2) Electrical CD (ECD) measurements conducted via a parametric test system immediately after gate etch completion. Both methods have proven to give precise measurement with relatively high throughput. However, both methods are limited in their ability to provide metrology or process characterization beyond the one-dimensional CD value. Other metrology techniques such as atomic force microscopy (AFM) and cross-sectional tunneling electron microscopy (TEM) are able to provide full twodimensional profile metrology with requisite precision for proper control of advanced gate patterning processes. However, throughput for both techniques is inadequate to allow for proper statistical sampling necessary to control a volume manufacturing line. TEM has the additional drawback of being a destructive process. This article describes the use of a CD metrology technique based on spectroscopic ellipsometry to provide fast, accurate, and precise two-dimensional profile information on polysilicon gate structures. This metrology technique, which is the basis of KLA-Tencor’s SpectraCD™, is cur-