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The Engineered Substrate’s Balancing Act: Performance Gains versus Greater Costs and Increased Yield Risks Katherine Derbyshire, Thin Film Manufacturing

The substrate is the foundation of an integrated circuit, the stable base on which the entire process rests. Polished to the edge of perfection, these triumphs of the crystal grower’s art flow through semiconductor fabs by the thousand. In 2003, wafer production exceeded 1.3 billion square inches. Few, if any, industrial materials can match device-grade silicon’s combination of high purity and high volume.

If the substrate is the foundation of the process, it is also the weak link. Critical parameters like device mobility and resistance depend on the wafer properties.

Wafer defects can undermine even the most well-controlled fab processes. As fabs stretch the capabilities of CMOS, they are moving beyond the familiar polished wafer. Silicon-on-insulator, strained silicon, and other engineered substrates bring substantial performance benefits, but also greater costs and increased yield risks.

Old standby faces new challenges Commodity devices like DRAMs generally rely on polished bulk silicon wafers, grown by a process that has remained essentially unchanged since the 1960s. A single crystal seed provides a template for the slow growth of a crystal boule from a crucible of molten silicon. Wafers are simply polished slices from this boule. This Czochralski (CZ) growth technique has survived transitions from 150 mm to 200 mm and now 300 mm wafers, but may be approaching its ultimate limits. Larger wafer diameters increase the weight of the growing crystal. Since mechanical considerations limit the maximum crystal weight, Summer 2004

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large diameter crystals are shorter.

The thermodynamics of cooling tend to concentrate impurities in the lower portion of the crystal boule. As the wafer diameter increases, the lost material at the upper and lower ends of the boule accounts for a larger share of the total crystal weight. Uniform, defect-free cooling and dopant distribution become more difficult as the wafer diameter increases, too.

Fabs are switching to 300 mm wafers in order to improve productivity. Maintaining the industry’s historical productivity curve will, according to the authors of the 2003 International Technology Roadmap for Semiconductors (Roadmap), require the introduction of 450 mm wafers in 2011, and 675 mm wafers in 2020. Significant crystal growth and handling issues will need to be addressed if such large wafers are to become a reality. The high cost of the 300 mm transition suggests that increasing productivity by increasing wafer size alone may no longer be cost effective.

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Still, wafer manufacturing technology continues to advance. Smaller devices place ever more stringent constraints on the starting material, demanding lower levels of such wafer defects as stacking faults, crystal-originated pits (COPs), and SiO2 precipitates.

Advanced lithography demands more stringent flatness specifications as the depth of focus budget dwindles.

Specifications for parameters such as epitaxial structure defects are limited by metrology as well as by the wafer manufacturing process.

Despite more than 40 years of experience, the industry still doesn’t have a reliable model relating wafer defect levels to device yields. The ideal yield model would consider both the probability of failure due to a particular defect or parameter value, and the likelihood of the value’s occurrence. Such a model would allow customers and suppliers to relax specifications for defects with a low risk of yield loss, while aggressively targeting defects with high kill ratios. With such a model, it would be possible to judge the cost of “perfect” wafers against the yield risks associated with a less stringent, and less expensive, specification. Without it, wafer manufacturers must strive to meet ever more stringent definitions of perfection.

By the 70 nm technology node, the 2003 International Technology Roadmap for Semiconductors expects

Not only are specifications becoming more stringent (Table 1), but they are becoming more stringent over multiple length scales. For example, wafer bow and warp vary on scales of centimeters or tens of centimeters, while site flatness may vary over micron distances. Nanotopography varies over submicron distances.

Adequate characterization of wafer flatness requires both large area measurements of the wafer shape and a high density of data points to capture local variations. Metrology techniques that are appropriate for large area measurements may not have enough throughput or resolution for local area characterization.

Table 1: Wafer Technology requirements, polished and epi wafers Year of Production

2003

Technoogy Node DRAM 1/2 Pitch (nm) MPU/ASIC Physical Gate Length (nm) General Characteristics (99% Chip Yield) Front surface particle size (nm) Particles per cm2 Site flatness (nm) Nanotopography, peak to valley Polished Wafer (99% Chip Yield) Oxidation stacking faults (DRAM)(per cm2) (OSF)(MPU)(per cm2) Epitaxial Wafer (99% Chip Yield) Large epi structure defects (DRAM) (per cm2) Large epi structure defects (MPU) (per cm2) Small epi structure defects (DRAM) (per cm2) Small epi structure defects (MPU) (per cm2)

100 45

2004 hp90 90 38

≥90 ≤0.35 ≤101 ≤25

2005

2006

80 32

70 28

2007 hp65 65 25

≥90 ≤0.35 ≤90 ≤23

≥90 ≤0.35 ≤80 ≤20

≥90 ≤0.18 ≤71 ≤18

≥90 ≤0.18 ≤64 ≤16

≥90 ≤0.09 ≤57 ≤14

≥90 ≤0.09 ≤51 ≤13

≤1.9 ≤0.6

≤1.6 ≤0.5

≤1.4 ≤0.4

≤1.2 ≤0.3

≤1.0 ≤0.3

≤0.8 ≤0.2

≤0.7 ≤0.2

≤0.007 ≤0.003 ≤0.014 ≤0.006

≤0.009 ≤0.003 ≤0.018 ≤0.006

≤0.012 ≤0.003 ≤0.024 ≤0.006

≤0.008 ≤0.003 ≤0.017 ≤0.006

≤0.010 ≤0.003 ≤0.021 ≤0.006

≤0.008 ≤0.003 ≤0.015 ≤0.006

≤0.010 ≤0.003 ≤0.019 ≤0.006

Source: International Technology Roadmap for Semiconductors, 2003 edition Table 1: Wafer Technology requirements, polished and epi wafers

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2009

57 23

50 20

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Silicon-on-insulator helps isolate devices

Military and aerospace applications requiring radiation resistance have used silicon-on-insulator (SOI) wafers for years. In these wafers, the thin silicon device layer offers a low impact cross section to alpha particles, while the insulating layer blocks the movement of free charges generated in the wafer bulk.

Recently, cost improvements and the need to reduce parasitic capacitances have helped bring SOI into the mainstream of IC manufacturing.

In a conventional polished or epi wafer, parasitic junctions exist between the highly doped wells of the transistor structure and the background doping of the wafer.

These junctions add to the total capacitance of the circuit, increasing power consumption and degrading switching speed. Parasitic junctions between adjacent transistors can lead to latchup. SOI insulates the device layer from the bulk of the wafer. In combination with shallow trench isolation, SOI wafers place each transistor in a well of insulator, eliminating latchup. According to Suresh Venkatesan, Motorola’s director of

CMOS platform development, SOI can reduce circuit capacitance by 15%.

The first SOI wafers used ion implantation to create a buried oxygen layer. With annealing, the implanted oxygen reacted with the surrounding silicon to create SiO2.

The process was very expensive: creating a thick enough oxide layer required a lengthy and expensive high-energy implant. The insulating layer must be thicker than the gate oxide. Thus, smaller feature sizes have reduced the necessary thickness and the wafer cost.

Meanwhile, research at Oak Ridge National Laboratory found that a secondary implant allowed oxygen to diffuse from the exposed surface to the buried oxide layer. This additional oxygen pathway cut the implant time, the largest contributor to SOI wafer cost, by a factor of ten, Ibis VP of engineering Julian Blake said. SOI became cost effective for high-performance applications

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such as microprocessors.

An alternative method of SOI fabrication, wafer bonding (Figure 1), recently achieved comparable cost reductions. Wafer bonding grows a high-quality oxide layer on the surface of one prime silicon wafer, then bonds another silicon wafer to the oxide. Etching or mechanical grinding thins the top wafer to the desired active layer thickness. This approach consumes two prime silicon wafers to make one SOI wafer. Its successor, the layer transfer method, uses a helium implant to create voids below the bonding surface of the top silicon wafer. Annealing causes the voids to coalesce, splitting the wafer at the implanted layer. A thin layer of silicon remains bonded to the oxide. The rest of the top wafer can be used as the substrate for another SOI wafer. A brief polish perfects the exposed silicon device surface.

Both implanted and layer transfer SOI suppliers claim that they can A

1. Initial silicon

2. Thermal oxidation

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B

A H+

3. Hydrogen implantation

4. Cleaning & bonding

A

B

5. Splitting

A

Performance-oriented logic devices already use epi wafers, which grow a thin epitaxial layer of silicon on top of a polished wafer. Epi wafers build on the polished wafer’s crystal template, but protect the device surface from defects present in the wafer.

With fewer surface defects, epi wafers are less prone to latchup and soft errors.

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A

polished wafer users will demand the use of defect engineering methods. For example, COPs are agglomerations of point vacancies. High temperature annealing can help eliminate them, while control of the silicon melt can help confine them to relatively small areas of the wafer.

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B 6. Annealing & CMP Touch polishing SOI WAFER 7. Wafer A becomes new A

Figure 1. Process flow for Soitec's SmartCut layer transfer method. Image courtesy of Soitec.

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achieve defect levels comparable to bulk silicon. SOI wafers still cost three or four times as much as bulk silicon, Venkatesan said. However, they simplify the process flow by eliminating deep well implants.

Better device isolation lets designers pack transistors more closely.

Overall, the finished device cost of SOI is only 10-15% more than that of bulk silicon.

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according to the Roadmap, there are no known defect inspection solutions.

reduce the distance carriers must travel, high dielectric constant (k) gate dielectrics degrade silicon mobility. High-k dielectrics will be needed by the 65 nm node, at which point oxide dielectrics thin enough to control the channel will allow unacceptable levels of gate leakage current. While many semiconductors have better mobility than silicon, only silicon is compatible with the industry’s existing CMOS infrastructure. Fortunately, silicon’s mobility changes with lattice strain.

The physics involved are still a matter of some debate among researchers, but it appears that strain splits the conduction band, reducing the carrier effective mass.

Typical wafer defects like COPs are less common in SOI wafers because of the surface preparation technology.

Particles remain a concern, however, and are more difficult to detect because of interference effects at the buried oxide layer. Dislocations, epitaxial growth defects, and other structural faults are more difficult to detect, as are thickness variations.

Roughness at the oxide/silicon interface can compromise thickness measurements and cause local variations.

Voids, bonding failures, and other interface defects can lead to 100% yield loss.

By 2008, the Roadmap expects the most advanced devices will probably turn to fully depleted SOI, in which the silicon device layer is only as thick as the transistor depletion region (Table 2). These wafers require silicon layers less than 20 nm thick.

Moreover, the thickness controls the dopant concentration, and therefore many of the transistor properties.

Strained silicon accelerates carriers

Metrology of SOI wafers is extremely difficult. The two oxide/silicon interfaces can interfere with conventional optical inspection measurements.

After the 90 nm technology node,

Though SOI reduces device resistance, it offers no help with the most fundamental barrier to transistor speed: the mobility of carriers in silicon. While shrinking devices

Many different methods have been used to strain the silicon lattice both at the wafer level and at the microscopic level of individual devices.

The most common approach to wafer-level strain uses SiGe to create a template for the silicon device layer. Silicon and germanium have

Table 2: Wafer Technology requirements, silicon-on-insulator wafers Year of Production

2003

2004

2005

2006

hp90

Technoogy Node

2008

2009

hp65

DRAM 1/2 Pitch (nm)

100

90

80

70

65

57

50

MPU/ASIC Physical Gate Length (nm)

45

38

32

28

25

23

20

Starting silicon thickness (partially depleted)

78-133

67-115

58-100

53-91

48-83

44-76

40-70

Starting silicon layer thickness (fully depleted)

24-43

21-39

20-36

19-34

18-33

17-31

16-30

Buried oxide (BOX) thickness (fully depleted)

68-112

56-94

48-80

42-70

38-64

34-56

30-50

Large area SOI defects, (DRAM)(per cm2)

≤0.007

≤0.009

≤0.012

≤0.008

≤0.010

≤0.008

≤0.010

Large area SOI defecta, (MPU)(per cm2)

≤0.003

≤0.003

≤0.003

≤0.003

≤0.003

≤0.003

≤0.003

Small area SOI defects, (DRAM)(per cm2)

≤0.137

≤0.173

≤0.221

≤0.142

≤0.178

≤0.116

≤0.146

Small area SOI defects, (MPU)(per cm2)

≤0.154

≤0.156

≤0.159

≤0.159

≤0.159

≤0.159

≤0.159

Source: International Technology Roadmap for Semiconductors, 2003 edition Table 2: Wafer Technology requirements, silicon-on-insulator wafers

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the same lattice structure; the lattice constant of their alloy varies linearly with the germanium concentration according to Vegard’s Law:

where aSi is the lattice constant of silicon (5.4307 Å), aGe is the lattice constant of germanium (5.6579 Å), and x is the germanium concentration in the alloy.

Silicon grown on top of this SiGe layer will “stretch” in order to maintain the silicon crystal structure while bonding to the underlying SiGe. At about 20% germanium, Soitec chief technology officer Carlos Mazuré said, the biaxial strain in the silicon layer is about 1.5 GPa. Electron mobility under these conditions is approximately 1.6 times greater than in unstrained silicon.

Hole mobility is about 1.2 times greater than in unstrained silicon, substantially less enhancement than predicted by theory. The reasons for the discrepancy are not yet fully understood.

Crystals tend to nucleate dislocations in order to relax the lattice under applied strain. At some critical layer thickness, the strain energy is greater than the energy needed to create a dislocation. Rather than risk spontaneous changes in lattice strain during thermal processing, most wafer-level strained silicon approaches seek to create a fully relaxed SiGe “virtual substrate” for subsequent silicon deposition. One typical approach begins with a prime silicon wafer. As Mayank Bulsara, chief technology officer of Amberwave, explained, a graded SiGe deposition gradually increases the germanium concentration from zero at the silicon interface to the desired value, usually 15-25%. The sublayer deposited at each composition step is thicker than the critical

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thickness for that composition.

Thus, each sublayer nucleates dislocations to accommodate the strain due to the changing lattice constant.

The top surface is fully relaxed, ensuring that only strain due to lattice constant mismatch will propagate to the silicon device layer. The final silicon layer is less than the critical thickness. No dislocations nucleate, and the silicon carriers see the full effect of the lattice strain.

The complete buffer layer structure (Figure 2) is typically two or three microns thick, Bulsara said.

Deposition of such thick epitaxial layers is slow, and makes a significant contribution to the total wafer cost. Many researchers are trying to develop thinner structures, while still fully relaxing the SiGe strain.

One variation, developed at IMEC, relies on the observation that carbon doping reduces the energy barrier to dislocation formation. At the 2004 Materials Research Society Spring Meeting (MRS; San Francisco), IMEC’s Roger Loo explained that a very thin (about 5 nm) layer of SiGe doped with carbon helps the structure achieve complete relaxation at a lower SiGe thickness.

Misfit dislocations in the SiGe layer do not affect the characteristics of the silicon. However, the ends of misfit dislocations are threading arms, which propagate perpendicular to

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the wafer plane. Graded SiGe layers distribute the misfit dislocations vertically, making them less likely to interact. Long misfit dislocations form, minimizing the number of threading arms. Still, Bulsara said, even the best strained silicon wafers have very high dislocation densities on the order of 105 dislocations/cm2, more than four orders of magnitude more than in silicon-on-insulator wafers. As long as the dislocations are uniformly distributed, such high defect levels appear to be tolerable.

As devices shrink, the risk that a dislocation will fall in a critical region like the transistor channel becomes very small. In fact, according to Bulsara, Amberwave’s development efforts are focusing on cost and uniformity, rather than dislocation density.

Dislocations do not tend to be distributed uniformly, however. Instead, they tend to cluster together, creating regions of very high defect density. In the SiGe layer, these dislocation pileups create lattice distortion and surface roughness. In the silicon layer they can have serious consequences for any devices unfortunate enough to land on them. Since the industry is only beginning to consider materials with very high dislocation densities, it is only beginning to examine appropriate metrology and inspection techniques. Materials researchers often use selective etch-

SiGe Regrowth Layer SiGe Cap Layer SiGe Graded Buffer Layer Si Substrate Figure 2. Schematic (a) and TEM cross section (b) of strained silicon with strain-relaxed SiGe buffer layer. Dislocations in the SiGe help dissipate strain. Images courtesy of AmberWave.

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ing to decorate defects and make them visible to optical microscopy, but this approach is clearly not suitable for wafer or circuit production.

The behavior of an individual transistor depends on the strain field seen by that transistor. Strain at the wafer level and even the individual die level is relatively easy to measure. X-ray diffraction allows direct measurement of the lattice constant, and therefore the lattice mismatch.

Spectroscopic ellipsometry can be used to map germanium content and film thickness uniformity.

Still, deposition irregularities and thermal variations can cause strain fluctuations on a much smaller length scale. For small spot (one micron) strain measurements, Raman spectroscopy may be the most appropriate technique. Raman measures the vibrational wavelength of chemical bonds in the material.

Si-Si, Ge-Ge, and Si-Ge bonds all have characteristic wavelengths.

These wavelengths shift as the length of the bond changes.

Strained silicon on insulator adds advantages

As noted above, strained silicon and SOI have complementary effects on device properties. Strained silicon helps mobility, but it does little to reduce parasitic capacitances. Most researchers therefore view strained silicon on insulator as the most likely substrate for advanced manufacturing.

Growing strained silicon on an SOI substrate wafer is straightforward, comparable to growing strained silicon on a silicon wafer. However, both the layer transfer and ion implant approaches to SOI support other growth paths as well. For example, strained silicon on implanted SOI can take advantage of the preferential oxidation of silicon relative to germanium. If oxygen is 30

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implanted into the SiGe layer, the germanium will segregate out of the growing SiO2. This approach confines the germanium to a welldefined layer, preventing diffusion into the wafer bulk. However, the high-temperature annealing needed to consolidate the SiO2 layer places an upper limit on the germanium concentration.

According to Mazuré, the risk of germanium diffusion sharply reduces the available process window. In silicon devices, germanium can create interface traps and weak spots in the gate oxide. It can cause p-n junction leakage, as germanium atoms create a conduction path with a smaller band gap than silicon’s.

With layer transfer wafers, it is possible to avoid these issues by leaving the SiGe layer behind altogether.

Placing the void-inducing helium implant just below the silicon device layer detaches it from the SiGe strain layer, transferring only strained silicon to the oxidized substrate. A selective etch removes any excess SiGe. This approach avoids the process impact of germanium entirely.

According to Mazuré, these structures are stable up to temperatures of at least 1100°C. As noted above, strain has a much smaller impact on hole mobility

than electron mobility. Researchers are still trying to understand the difference, but it appears that hole mobility is affected primarily by uniaxial stress in the <110> direction. Orienting PMOS transistors in that direction can help equalize performance. Another alternative is to apply additional strain in the local area of the PMOS transistor, either instead of or in addition to the wafer level strain.

Strain engineering, one transistor at a time

Local strain has always been present in transistor structures. Until recently, manufacturers have tried to minimize it. Now that it has become desirable, proposed methods include addition of a strain layer to the gate stack, selective epitaxy, and replacement of the source and drain with a strain layer. All require substantial changes to the process and precise strain measurements at the individual transistor level. Mazuré explained that researchers are still trying to determine the optimum balance between wafer-level strain, which requires fewer process changes, and local strain, which allows optimization of individual transistors.

In an MRS presentation, Scott Thompson described Intel’s approach

Figure 3. TEM micrographs of 45 nm p-type and n-type MOSFET. Image courtesy of Scott Thompson, Intel.

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to strain engineering.* PMOS transistors replace the source and drain wells with SiGe “squeezing” the silicon channel (Figure 3). A 17% germanium concentration applies 600 MPa of stress to a 45 nm channel. NMOS transistors use a silicon nitride cap to apply the desired strain.

Most manufacturers are skeptical of any approach that requires substantially different processes for NMOS and PMOS transistors. Dual devices potentially double process complexity, cost, and yield risk. Yet it isn’t clear that they have a choice.

Though transistor-level optimization

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of strain appears to be a radical change, it is actually the next step in a long series of substrate improvements. From the first polished wafers to the most advanced strainengineered substrates, the industry’s past and future have always rested on a state-of-the-art foundation. Each new technology has appeared radical when introduced but has quickly become indispensable.

business forces and technology advances. Previously, she was Managing Editor of Semiconductor Online from 1998 to 2001, and Chief Technical Editor of Solid State Technology from 1994 to 1998. She has engineering degrees from the Massachusetts Institute of Technology and the University of California, Santa Barbara.

About the author

* Dr. Thompson is now at the University of Florida, but he performed the reported work while at Intel.

In 2001, Katherine Derbyshire founded Thin Film Manufacturing, a consulting firm helping the industry manage the interaction between

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