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Yield Management

S O L U T I O N S Yield Acceleration Strategies for the Semiconductor Industry

SPECIAL ISSUE: A Focus on Cu/low-κ 15 15 COVER COVER STORY STORY — — A ANOTHER NOTHER D DAY AY,, A ANOTHER NOTHER Y YIELD IELD L LEARNING EARNING C CYCLE YCLE 8 8 VOIDS, PITS,

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Voids, Pits, and Copper Achieving a void-free copper process flow requires a tried and tested defect inspection strategy.

31 The Best Laid Plans of 300 mm Fabs Insufficient yield management planning can handicap your 300 mm initiative.

42 Time-to-Detect Frames the Integrated Debate To integrate, or not to integrate? That is the question facing many 300 mm fab planners today.

54 CMP: Where Does It End? In-situ copper CMP endpoint detection shortens process development.

59 The Dollar Value of Accelerated Shrinks In most cases, metrology-driven shrinks are the most economic and effective means for reducing die-cost in demand-limited DRAM markets.

Cover image by Carlos Hueso, KLA-Tencor

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15 Another Day, Another Yield Learning Cycle A revolutionary new approach to yield learning speeds technology innovation and development.

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66 TeraStar SLF77 Reticle inspection system (die to database) TeraPro HP All-in-one reticle pattern, contamination, and MBB border inspection capability Viper 2430 300 mm automated macro-defect inspection system 67 Surfscan SP1 Backside Inspection Automated, non-destructive backside inspection system µLoop Inline, non-contact, electrical inspection solution

Yield Management Solutions is published by KLA-Tencor Corporation. To receive Yield Management Solutions, contact Corporate Communications at:

Sections

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Editorial: Copper—The Technology Marathon Enabler

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Q & A: Talking Yield—An interview with G. Dan Hutcheson, CEO of VLSI Research Inc.

KLA-Tencor Corporation 160 Rio Robles San Jose, CA 95134 Tel 408.875.3000 Fax 408.875.4144 www.kla-tencor.com

30 Spotlight on Lithography

For literature requests, call: 800.450.5308

53 Yield Management Seminar Series

©2002 KLA-Tencor Corporation.

All rights reserved. Material may not be reproduced without permission from KLA-Tencor Corporation.

Products in this document are identified by trademarks of their respective companies or organizations.

58 KLA-Tencor Trade Show Calendar 65 Got a Litho Question? Ask the Experts

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Copper—The Technology Marathon Enabler Like moths to a flame, humankind is irresistibly drawn toward technology. Its pull is so strong, yet so innate, that we often don’t even question why we push so hard at testing its limits. Take Moore’s Law, for example.

Why has the semiconductor industry continued to keep pace with it, as if engaged in a marathon? Certainly, no one questions the benefits of device scaling. Smaller chip designs enable more—and more complex—ICs per wafer, which leads to increased profits for the device manufacturer. If we take the 30,000-foot view, more complex and better-performing devices lead to new technology innovations that literally reshape the world we live in—from exploring the furthest reaches of our solar system or unlocking the secrets of the human genome, to redefining how we communicate with our friends and family, or even view our role in the universe.

We test the limits of technology because the pros far outweigh the cons. Technology is THE driving factor in improving our lives. Faster and lower power-consuming chips will one day, very soon, help replace the gas-guzzling automobile with the environmentally friendly electric car. Supercomputers that were developed for military and defense purposes are used today to develop advanced drugs that will help impede the progress of ravaging diseases. In the not-too-distant future, microfluid biochips will be used for clinical diagnoses, and the list goes on.

Without continued technology investments, however, many such futuristic advances may remain embryonic ideas. Let’s look at how this perspective applies to the technology trends we’re seeing today in advanced semi-

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conductor fabrication. If you look at chip manufacturing, you can essentially break it down into two segments: front-end-of-line, or FEOL (the transistor), and backend-of-line, or BEOL (the interconnect). Within these, two key technology inflections are occurring. In the front end, Intel’s newly announced depleted substrate transistors (DSTs) or silicon-on-insulator (SOI) materials are being introduced that promise to enable faster, lower-power switching. In the back end, however, no amount of innovation can improve device performance – it can only minimize any losses that you might have. All the improvement you’ve achieved in the front end can be lost in the back end, and what’s the point of having a faster-switching transistor that consumes less power if you have a poorly performing interconnect? That’s why copper and low-κ materials are so important to semiconductor innovation: because they help to minimize your losses in the back end so you can reap the performance gains of the front end.

While copper has revolutionized chip manufacturing, it has also placed incredible challenges and pitfalls in front of us. For example, we’re hearing people talk about void-free copper fill and deposition, but what do they mean? The reality is that there is no such thing as “void-free”; we need to know what’s statistically acceptable to achieve this designation. It is not enough just to make decisions about what accelerants and suppressants to use and hope to achieve a “void-free” copper fill. We need to ask ourselves many other important questions as well. What aspect ratios are involved, and at what design rules? What are the defect density requirements? Can we have one bad via

Yield Management S O L U T I O N S

EDITOR-IN-CHIEF Uma Subramaniam MANAGING EDITOR Siiri Hage CONTRIBUTING EDITORS Aparjot Dehal Indira Rangarajan

per thousand vias, or only one per trillion? It’s not enough to just have a hypothesis.

We need a basis from which we can accurately and rapidly measure the success in improving our copper processes, so that we can say with 95-percent certainty that the copper fill is statistically healthy or robust enough to meet our manufacturing requirements. No longer can we wait until BEOL—we now need to conduct root-cause analysis at FEOL or else place our investments at risk, stall our efforts to advance our processes from development to maturity, and fail to achieve manufacturing success.

With this perspective in mind, I think our YMS Magazine readers will truly enjoy the articles featured in this issue, including our cover story on µLoop, which represents a fundamental change in how one can statistically evaluate the meaning of “void-free” copper fill. As you go through these articles in your quest to successfully face the “Brave New World” of copper/low-κ, remember that technology sets high goals for us that we may not always achieve, but will always strive to reach. And, in the end, we become all the wiser because of it. We’ve set ourselves on this path, and having done so, we’re loath to stray and risk losing the advancements and benefits we’ve come to take for granted.

ART DIRECTOR AND PRODUCTION MANAGER Carlos Hueso D E S I G N C O N S U LTA N T Michael Garnica COPY EDITOR Dave Hattorimanabe C I R C U L AT I O N E D I T O R Nancy Williams

KLA-Tencor Worldwide C O R P O R AT E H E A D Q U A R T E R S

KLA-Tencor Corporation 160 Rio Robles San Jose, California 95134 408.875.3000 I N T E R N AT I O N A L O F F I C E S

KLA-Tencor France SARL Evry Cedex, France 33 16 936 6969 KLA-Tencor GmbH Munich, Germany 49 89 8902 170

Peter D. Nunan Vice President Yield Technology Solutions Group

KLA-Tencor (Israel) Corporation Migdal Ha’Emek, Israel 972 6 6449449 KLA-Tencor Japan Ltd. Yokohama, Japan 81 45 335 8200

Peter Nunan graduated from Lehigh University with a B.S. in Engineering Physics and a M.S. in Electrical Engineering. He began his career in 1979 working on DRAM process development at AT&T (currently Lucent Technologies). He has been involved in all aspects of process integration during his career while working at Siemens (currently Infineon), Sematech, and ST Microelectronics. He came to KLA-Tencor in 1998 to direct strategic alliance activities focused on copper and low-κ. Peter is currently vice president of the Yield Technology Solutions group at KLA-Tencor.

KLA-Tencor Korea Inc. Seoul, Korea 822 41 50552 KLA-Tencor (Malaysia) Sdn. Bhd. Johor Bahru, Malaysia 607 557 1946 KLA-Tencor (Singapore) Pte. Ltd. Singapore 65 782 6788 KLA-Tencor Taiwan Branch Hsinchu Hsien, Taiwan 886 3 552 6125 KLA-Tencor Limited Wokingham, United Kingdom 44 118 936 5700

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Q&A Talking Yield with Dan Hutcheson Dan is president and CEO of VLSI Research Inc. He is a recognized authority and well-known visionary for the semiconductor industry, whose career experience spans more than twenty years.

To help assess the impact that KLATencor’s new µLoop technology will have on the semiconductor industry, Yield Management Solutions sat down for a one-on-one discussion with one of the industry’s most well-known and respected independent analysts, G. Dan Hutcheson, CEO of VLSI Research Inc. The following Q&A elucidates some of the key issues chipmakers face with respect to yield management and the yield learning cycle, which µLoop was created to address.

YMS: Dan, let’s start at the beginning. What are some of the market and competitive pressures driving the acceleration of key technology transitions in the industry?

DH: One of the chief issues facing chip manufacturers today is the fact that cycle times are becoming extremely short. At the same time, the cost of bringing new technologies to market, like copper interconnect and 300 mm wafers, has become much greater than ever before.

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Furthermore, to fully leverage your investment, you have to get product to market faster – today, if you miss the market by six months, you can easily lose all the product’s profitability.

YMS: What impact does the convergence of copper interconnect, 300-mm, and subwavelength lithography have on yield?

DH: The impact of all these new technologies on yield has truly been to change the whole ball game. Not only are you no longer looking for surface defects, since many of them are now sub-surface, but the number of true killer defects is incredibly small today. While we used to look at defect densities of five to 10 per square inch, per layer, we are now dealing with small fractions. The fact is, in contrast to 10 years ago, the industry is not chasing particles but, rather, actual process problems. It’s somewhat analogous to looking for a needle in a haystack, within another haystack.

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YMS:

In today’s fab, then, how important is faster yield learning, or time to yield?

DH: It’s very important, simply because fabs are so expensive now.

Chipmakers are spending billions of dollars for these new 300 mm fabs, the time to market is critical, technology must be brought online quickly, designs have to come to market fast – everything has to happen in a much tighter time frame. A good illustration of this is the loss experienced by one of our clients, a chip producer. A yield problem in one of their fabs caused a six-month delay, costing them the entire profit potential for one of their products.

Any senior manager at a chip manufacturer today should understand the importance of yield because if you’re not focused on yield learning, you’re not competitive. At the end of the day, that’s what determines where your costs lie. There is no such thing as constant yield anymore – it’s all about how fast you can get there and how you go about improving it. We

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often talk about cost of ownership, cost of producing the wafer, but if you yield nothing, you have no revenues to offset that cost. The fact is, profits come from the yield part of the equation.

YMS: In your opinion, how does KLA-Tencor’s new µLoop technology stack up against today’s existing technologies aimed at yield learning?

DH: Clearly, µLoop technology is the next step in yield improvement and yield learning because, for the first time, we’re breaking away from visual inspection in the fab and can now do electrical testing in the fab.

The technology brings all of the advantages that you get with electrical test, of identifying true killer defects, inside the fab, so you don’t have to wait until the wafers are out to perform electrical test. That’s not only a revolution in yield management and yield learning – it’s a revolution in getting yield cycle times down.

YMS: Why is that so significant?

DH: If you can’t do that, your fab is going to have a yield learning disorder. Currently, it takes weeks or months to get wafers out and to electrical testing. Ten to 20 years ago, no one would have ever have accepted the notion of test as a means of improving yield in the fab. Yet now, senior executives in chip companies, all the way up to the CEO level, are talking about how they’re using

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electrical test as a way to drive fab yields because electrical test is the only way to sort killer defects from defects that don’t affect your fab. You don’t want to spend a lot of money and waste a lot of engineering effort to find defects in the wafer that don’t cause a problem, that don’t kill the yield – that really don’t matter, either to you or to your customer.

YMS: What’s the disadvantage of waiting until electrical test to identify yield problems?

DH: It’s simple: time is money in a fab. For example, suppose you’re a chipmaker running wafers at the rate of 7,500 per week, and you wait six weeks for those wafers. By the time a yield loss is detected, 45,000 wafers will have already been processed. If there is a yield problem, you must bring the fix into the loop, then wait another six weeks to see if the problem is solved. Now, you’re up to almost a hundred thousand wafers processed – if you lost, say, $10 per wafer, you’ve lost over $1 million. We’re talking about potential losses of hundreds of millions of dollars if you extrapolate that out across all of the products and product lines.

So, if you can shrink these long cycle times that cost you hundreds of millions of dollars by using µLoop technology, you can save those costs and expenses by simply bringing those revenue streams back in. Or, you can transfer

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the lower cost to your customers directly, allowing them to satisfy their customers faster. Either way, you win in the marketplace because it makes you more competitive, and makes your customers more competitive.

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How would you rank µLoop against the various yield-management advances you’ve seen over the last couple of decades, based on its potential?

DH: The last big thing in yield management was yield management.

Chipmakers went from looking at wafers with microscopes to automating defect inspection and classification. µLoop is really the next big step because it’s a new paradigm for improving learning and yield in the fab. It’s really an interesting new way of doing things. Instead of looking at an optical image, which has been done before, you’re looking at a SEM-based voltage contrast image.

The difference is that when you look at it electrically, it tells you whether a product is good or bad, or if a defect is really a killer. That has always been the promise of e-beam probing in this space, but the problem with e-beam is that it is classically too slow. That’s the big challenge that has to be overcome – and that’s really the promise of µLoop. It’s more significant than a lot of the other things we have seen in the past because at the end of day, yield is everything.

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Voids, Pits, and Copper Judy B Shaw, Richard L. Guldi, Jeffrey Ritchison, Texas Instruments Incorporated Steve Oestreich, Kara Davis, Robert Fiordalice, KLA-Tencor Corporation

As circuit features have scaled below 0.25 micron, the resistivity of aluminum has become an obstacle to integration. With forty percent higher conductivity than aluminum – and far more resistance to electromigration—copper holds the key to dramatic improvements in circuit density, speed and reliability. Integrating copper into the IC manufacturing process, however, is extremely challenging. Copper can diffuse into silicon and dielectrics, causing shorts or leakage, which can impact device performance and yield.

The introduction of copper dual damascene processing into integrated circuits has brought about a host of new defectivity issues, especially those related to voiding and pitting. These defects must be understood and eliminated to achieve competitive manufacturing yields and assure device reliability.

Surface pit

Void characterization in copper processes

As part of a joint development copper program to develop 100 nm logic processes, KLA-Tencor and Texas Instruments worked together to develop new defect inspection strategies.

The most important yield limiting defect types with copper are voids. Almost naturally, copper voids seemed to group into two distinct categories: optically detectable voids that are on the surface of the copper layer, and sub-surface voids, which are detectable using e-beam voltage contrast inspection (Figure 1).

Sub-surface void

Figure 1. The most critical copper voids can be grouped into two categories—optically detectable pits/voids on the surface of the copper, and sub-surface voids not obser vable from the surface, but detectable using e-beam voltage contrast inspection.

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Void formation may stem from electroplating, annealing, or polishing steps. It is important to identify appropriate inspection tools to characterize the process steps responsible for void generation in order to quickly determine root causes and optimize process capability, process control, and tool maintenance.

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An advanced 0.13-micron, copper dual damascene process was used at Texas Instruments’ Kilby Development Center (KFAB) to generate the samples in this paper.

The gallery of defects generated by this type of process (Figure 2), shows some embedded and surface particles, but primarily voids or pits dominating the defect Pareto.

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At the time that Texas Instruments and KLA-Tencor undertook the studies of copper defects, the process of record had brightfield inspection as part of the process loop, and this was done after copper CMP. Although brightfield inspection revealed many defects—some yield limiting and some less important—the sheer numbers of defects and the presence of patterning and underlying defects made surface void source partitioning difficult.

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using KLA-Tencor’s AIT III, was utilized to partition the source of patterning and underlying defects.

To partition the source of these defects, a darkfield inspection was carried out using a KLA-Tencor AIT III, and the first inspection was performed after CMP. Immediately, a high defect count and an obvious swirl pattern of voids were noted. The defect Pareto revealed the highest two categories to be voids and long pits, which are essentially another form of voids. Together, these two categories Copper Defect Gallery accounted for well over 70 percent of SEM the Pareto. Based on knowledge of the Images process and the process tool, the void formation appeared to show a CMP sigProcess Step nature (Figure 3). The first step in moving towards understanding the voids ILD Dep (5 Step) was inspection after electrochemical Seam From Topography ILD CMP (Optional) deposition (ECD). Post ECD inspection showed the swirl pattern to be subtler; Via Photo voids and pits were also present, albeit Defective Via Etch smaller and shallower than after CMP. Via Embedded The next step was to overlay ECD and Particle Trench Photo CMP defects on the wafer map using Trench Etch analysis software. Defect overlay con(BARC, Trench, Etch Stop) BARC firmed that the post-CMP voids in the Under-Etch swirl pattern had their root cause in the Barrier/Cu Seed Dep Void/Rip Out ECD, and were enlarged and revealed by Cu EP polishing and post-CMP clean (Figure 4).

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Figure 2. This figure shows a galler y of typical defects generated during copper dual damascene processing. Voids or pits dominate the defect Pareto, although a few other surface-type defects are present at a lower level.

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In this and other examples we have seen that darkfield inspection is quite successful for rapid and focused engineering analysis in the copper loops.

This is because oblique illumination minimizes the detection of previous Yield Management Solutions

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Figure 5. Sub-surface voids have many potential causes and are electrical in nature. These sub-surface voids were detected using the eS20XP’s voltage contrast methodology.

Figure 4. Defect overlay confirmed that the post-CMP voids in the swirl pattern had their root cause in ECD and were simply being enlarged by polishing and post-clean. Darkfield inspection is quite successful for rapid engineering analysis in the copper loops, because oblique illumination minimizes the detection of previous layer issues and other “noise,” enabling effective focus on current layer problems.

layer issues, as well as other inspection “noise,” so that we effectively focus just on the current layer.

Eliminating sub-surface copper voids

The second type of copper void is very different. It is a sub-surface void and, generally, these types of defects are related to materials or process integration issues. It is absolutely essential, during the technology development phase, to have a tool that finds these sub-surface voids, enabling screening experiments and quick elimination of these voids. This is critical to ramping a copper damascene process, because voids must be eliminated before the process flow is set, and before it is qualified. If the metal lines contain copper voids, they stand the risk of becoming opens, resulting in device failure.

In order to capture these voids at this very important juncture, KFAB used KLA-Tencor’s eS20XP e-beam inspection tool (Figure 5).

Random or array mode: when it works There are a number of techniques for implementing e-beam inspection to inspect sub-surface voids. The first option is random mode inspection of the logic areas on the product chip. This inspection is very useful to perform, as it provides considerable information. However, 10

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due to the random nature of the pattern, it is quite difficult to perform an effective analysis of root cause. It would be quite time-consuming for a failure analyst to take this information and determine the defect that caused the electrical opens.

The next option in implementing e-beam inspection is to utilize the array mode to inspect the memory areas of an SRAM chip. Array mode analysis is easier than random mode, because the defects of interest readily stand out in a voltage contrast SEM, but failure analysis is still non-trivial because of slight variation in SRAM design among different products or different technology generation, requiring considerable skill and time to perform the failure analysis. The most useful analytical technique is array mode inspection of defect density test die, which affords straightforward failure analysis, since the analyst can e-beam scan the defective chain along its length to precisely locate the electrical failures and then port those locations to a focused ion beam (FIB) microscope for cross-sectioning (Figure 6).

The work shown in the remainder of this paper is focused on the array mode inspection of a defect test chip. The test chip is grounded using a contact mask as the first pattern. This method makes it very easy to see where the defective via is. In the normal case, when the e-beam inspector scans the wafer, the grounded structure will appear bright due to the secondary electron emission. However, if a via void is present, the secondary electrons are effectively extinguished and that portion of the chain will appear dark. The inspection system’s extraction field attracts the secondary electrons.

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previous metal level.

eS20XP’s voltage contrast methodology enables easy detection of defective vias.

Experiment 1 – Evaluating via integrity at the wafer level

They are replaced from ground in the grounded structure and the floating structure charges positively. Secondary electrons from the floating structure have a lower net energy and are attracted to the positive surface charge, limiting the number that make it to the detector.

Hence, these defects look dark (Figure 7). In the case of Figure 8, a surface SEM detected nothing physically wrong, but voltage contrast imaging suggested that there was an electrical open below the surface. That is exactly what the FIB cross-section revealed—a void in the previous layer metal, the via landing pad.

Experiment 1 was conducted to evaluate via integrity at the wafer level using the eS20XP under various interconnect process conditions. Three process variables were screened: the ECD seed conditioning, the pre-ECD rinse conditioning, and the post-ECD anneal. The experiment was designed for 0.13 µm dual damascene copper/low-κ via structures. Wafers were inspected using the eS20XP. The outcome clearly showed that the same result could be achieved with the eS20XP inspection that otherwise would have only been detected with electrical via resistance testing at final test (Figure 9).

Screening Experiments After the practicality of e-beam inspection was established, this technique was applied to two experimental problems. The first experiment investigated the effect of ECD seed conditions, pre-ECD rinse, and post-plating anneal on voids, while the second examined the effect of seed thickness and post-plating anneal.

The experimental data show that the post-ECD anneal conditions drove the experimental results. Anneal B had several times as many defects as anneal A. The other two process variables—the ECD seed condition and the pre-ECD rinse condition—had negligible effect on the defect counts. Another valuable piece of

eS20XP Defect Scan Summary Anneal "B"

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Figure 9. This summarizes the results of the first experiment, which Figure 7. In this example, top surface inspection showed nothing

compared the effect of ECD pre-conditioning anneal, pre-ECD rinse,

physically wrong; however voltage contrast e-beam inspection and

and post-ECD anneal on copper voids. The vast majority of defects

subsequent FIB revealed the presence of a high-resistance, sub-surface

found by the eS20XP were voltage defects as opposed to surface or

connection due to a void in the previous layer metal at the landing pad.

particle defects.

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Figure 10. Electrical probing confirmed the e-beam inspection results, with anneal B giving a high resistance fail in the via chain cumulative percent fail, compared to the relatively healthy via fail distribution for anneal A.

information was also found in this data—a strong acrosswafer radial dependency of the defect counts. The vast majority of the defects were at the edge of the wafer.

The next step with these same wafers was to probe the via chains; these results were consistent with voltage contrast data. The via chain cumulative percentage plot showed fall-out under anneal B conditions. Anneal A had a relatively healthy, robust distribution of via resistance, whereas anneal B’s distribution was poor, with many outliers. This probing revealed the same sort of voids as seen before. Anneal B had either voided via plugs or voids in the underlay landing pad (Figure 10).

Experiment 2 – Evaluating via integrity under thermal stress

Experiment 2 was conducted to evaluate via integrity under thermal stress using the eS20XP. The experiment was again set up on 0.13 µm dual damascene copper/ low-κ via structures. The wafers were exposed to four thermal cycles post CMP. An eS20XP inspection was performed after each of these cycles. In this screening experiment there was only one process variable—the ECD Cu seed thickness (Figure 11). eS20XP Via Void Evaluation

Defect Count

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A number of results were found in this experiment.

First, there was a strong wafer-to-wafer effect. The same spatial effect of center to edge found in Experiment 1 was seen again. Seed thickness A produced lower defect counts. The defective vias were again confirmed to have subsurface voids. Seed Thickness A wafers have the most consistent counts as well as the lowest defect counts after four anneals. Seed thickness B wafers had much wafer-to-wafer variability, generally with higher counts.

One seed thickness B wafer, wafer 5, had very high counts. Counts increased greatly with the number of anneal cycles. Wafer 5 was then taken to the FIB tool (Figure 12) and, for the third time, it was demonstrated that voids were induced by anneals, both in the plug as well as in the underlying pad.

Moderate Void

Voltage Contrast Example

Moderate Void

Extensive Void

Figure 12. This figure shows FIB cross-sections of three different voltage contrast voids after the fourth anneal. It was found that intermediate temperature annealing leads to moderate void formation at the bottom of vias, resulting in voids that are not as fully developed as those arising from higher temperature anneal. However, a few extensive void developments were also seen, as shown in the lower right corner of this figure.

Conclusion

Both optical and e-beam inspection methodologies have proven useful for copper void detection. AIT III inspection, with its oblique angle of incidence, is very effective in detecting surface voids, helping to characterize the ECD process, which is responsible for generating most of the voids. Voltage contrast inspection of defect density test chips using eS20XP has a unique and complementary application: to detect subsurface voids.

The combination of optical and e-beam inspection tools enables faster detection and analysis of copper voids, leading to accelerated learning cycles.

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www.kla-tencor.com/microloop Visit our site for a µLoop webcast presentation.

The Switch Is On.

Accelerating Yield InLine Electrical Inspection • Non-Contact • Killer Defect Identification ©2001 KLA-Tencor Corporation ©2001 KLA-Tencor Corporation

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Defect Management for 300 mm and 130 nm Technologies Part 3: Another Day, Another Yield Learning Cycle

Kurt Weiner, Todd Henry, Akella Satya, Gaurav Verma, Richard Wu, KLA-Tencor Corporation Oliver Patterson, Brian Crevasse, Kris Cauffman, William Cauffman, Agere Systems

The back-end-of-line (BEOL) interconnect process increasingly poses a formidable challenge for yield groups striving to attain high yields and profitability in today’s competitive market. The combination of smaller design rules and vastly more complex processes highlights the need for a radically new approach to yield learning. This article, the third in a series focused on effective defect management, discusses a revolutionary new methodology for yield learning that significantly shortens the yield learning cycle and offers the ability to exclusively capture yield limiting defects. Through its special design, the method combines non-contact electrical test with inline physical defect inspection, significantly reducing the engineering resources required to identify the problematic defect type and establish root cause, and the time it takes to validate a successful fix. This new methodology, which enables unprecedented breakthroughs in yield learning, gives manufacturers tremendous advantages in productivity and substantial cost savings, ultimately speeding the development of future integrated circuit innovations.

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by speeding the yield learning process, especially in the critical development and early ramp phases.

For IC manufacturers and their customers, time-to-market and timeto-profit are limited by the yield learning cycle time and quality of electrical defect data as reflected in its ability to drive learning.

Introduction

Several years ago KLA-Tencor recognized a critical gap in a fab’s ability to minimize the time-to-market for a new technology: the speed and effectiveness of the yield learning methodology for the back-end-of-line. In response, KLA-Tencor developed a new approach based on its powerful e-beam inspection and defect review technologies.

KLA-Tencor’s µLoop technology, which enables faster yield learning, leverages existing engineering resources to allow earlier technology introduction at significantly higher yields. Effective use of this technology also results in an accelerated yield ramp and higher, mature technology yields.

This earlier introduction of technology, coupled with an accelerated yield ramp, results in increased profitability, as semiconductor manufacturers are able to take advantage of the higher margins that are available early in the life of new leading edge technologies.

What are the underlying market and technology factors driving the transition to this new method?

The Value of Accelerated Yield Learning In Figure 1, a typical BEOL interconnect for quarter-micron technologies is compared with a sub-180 nm process to show the qualitative difference in the number of vital connections necessary to produce a working product. The number of interconnect levels—as well as the design complexities—within the sub-180 nm node increases significantly. Compounding the problem, each successive technology generation requires faster time-to-yield to remain profitable. The value of accelerated yield learning is clear: a three-month reduction in the timeto-yield of a process means hundreds of millions of dollars in increased profitability, with the added benefit of the higher selling prices associated 16

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BEOL Challenges at Sub-180 nm Technology Nodes

Figure 1. The number and complexity of interconnects increases significantly in a sub-0.18 µm process compared to a 0.25 µm process.

with leading-edge product versus trailing-edge product. In comparison, the same improvement in yield learning applied to the manufacturing phase equates to only millions of dollars. This difference reflects the philosophy of basic quality improvement processes: namely, trying to fix the defects during the design phase—where it is more cost-effective—rather than waiting to doing this in the production phase. Greater complexity combined with faster time-to-yield can only be achieved

The problem of speeding time-toyield is non-trivial. In current and future deep-submicrometer technology nodes, kilometers of wiring are required at each metal level to interconnect the millions of transistors in an advanced integrated circuit design. For acceptable yields, an electrical defect density (D0) of less than 0.15 defects/cm2 is required.

Achieving and maintaining this D0 necessitates the capture, analysis, and understanding of virtually every yield limiting defect type in the process line. Unfortunately, the critical size of killer defects is decreasing (scaling with the CD of the process) and reaching the size of materials defects such as metal grains and line edge roughness. Finding and eliminating the electrical “short” and “open” defects while ignoring the non-relevant defects induced by material anomalies is particularly

Voltage Contrast Inspection Physical Characterization

Figure 2. Critical subsurface via defects such as this can be detected using e-beam inspection.

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difficult in the BEOL, and yet essential to attaining profitable production yields in a semiconductor manufacturing line.

at which engineers can negotiate through the various sections of this path will directly impact how quickly yield problems can be solved.

A second and equally daunting challenge concerns the 10s to 100s of millions of vias that provide connections between each level of metal interconnect. The vast majority of these vias are not redundant, resulting in a dramatic hit to yield if more than a few vias per billion are electrically defective within a given layer. Some via failures are caused by surface defects that can be detected using conventional inspection techniques. However, a rapidly increasing number are subsurface, as shown in Figure 2, and can only be detected effectively using electrical measurements. Capturing this buried type of via defect has been a major driver for the implementation of e-beam inspection in recent years.

Step 1: Yield Limiting Defect Identification

These new challenges place a burden on the yield and process groups to implement the fastest and most effective BEOL yield learning method possible.

The yield learning cycle

Today, as in the past, all defect issues are resolved through yield improvement methods organized in repetitive sets of steps or yield learning “cycles.” The start of the cycle is typically triggered when yields are running below a target goal. The methodology to resolve most yield problems follows a common path, which includes identification, engagement, hypothesis testing, and implementation (Figure 3). The rate Low yields

Problem identification “what to fix”

Engagement of processing & integration

In this step, a Pareto of the defect types contributing to the yield problem is established. This Pareto of yield limiting defects is used to prioritize yield improvement efforts to insure resources are placed where they will have maximum impact on improving yield performance.

Step 2: Engagement As soon as the yield limiting defect Pareto has been established, the key to success will now hinge on developing a solution that will eliminate the problematic defect type from the overall population. Process and/or integration engineers must be “engaged” in the activity of developing ideas for changes to fix the problem.

Step 3: Hypothesis Testing The impact of the proposed changes are then evaluated through carefully controlled studies designed to assess if the independent variables, which could be process or integration changes, quantitatively reduce the yield limiting defect type and/or improve the electrical performance.

In total, the elimination of the yielddetracting defect requires at least two iterations of these hypothesis-testing experiments (cycles of learning).

Step 4: Implementation Timely introduction of the new process or integration fix is also Hypothesis testing

Implementation of solution

Figure 3. A typical yield learning cycle.

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necessary to accelerate the yield improvement rate.

Current yield learning methods

Currently, three methods dominate the industry for BEOL yield learning: the product loop, the memory (or SRAM) loop, and the short loop.

These are typically applied in steps 1 and 3 of the yield learning cycle.

Product Loop The advantage of using real product for the yield learning cycle is that the output statistic is the one that is of most interest. Engineers want to understand if the proposed changes will result in improved yield performance. Using product for yield learning has several obvious disadvantages: long learning cycle times; difficulty in isolating the yield limiting defect types; and, the fact that large sample sizes are necessary to assess the impact of the process change on improving the product yield. Creation of an accurate yield loss Pareto on product wafers is a difficult and time-consuming—if not impossible—task on logic technologies. First, electrical testing to evaluate the experiment cannot occur until the product is complete, which can take several months, depending on the complexity of the process. Fault identification, which is much more difficult on nonbitmappable devices, is extremely time consuming and may not result in an accurate yield loss Pareto.

Aside from difficulties with fault isolation, product yield performance does not provide an ideal metric for hypothesis testing. While the yield metric is the one that ultimately is needed to validate improved processes, it often does not provide the level of granularity that is needed to assess the effectiveness of proposed process changes. Yield distributions tend to be highly variable,

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due to the impact of many different factors; the influence of the independent variable under test on yield is often hidden by the “noise” created by all these other environmental factors.

The large variation in the distribution necessitates the use of larger sample sizes to validate a quantitative difference between defect populations.

Memory Loop The memory or SRAM cycle functions in a similar manner as the product cycle, except that a chip with bitmappable memory structures is used. The advantage of this cycle is that it provides an approximate location for each of the electrical defects.

The yield limiting defects can be isolated to a specific layer with classic de-processing techniques. Accurate yield loss Paretos can be developed using this procedure if given enough time. Engineers can use this information to “identify” what defect types need to be reduced to improve yield performance.

However, the bitmap information, while useful in problem identification, cannot be used effectively to gauge statistical differences between populations in hypothesis testing experiments. The labor-intensive nature of the de-processing makes it impractical for assessment of hypothesis testing experiments. Therefore, memory loop improvement experiments use yield as the dependent metric to assess improvement, and suffer the same sample size problems and long time to solution as the product loop.

Short Loop Short loops, in contrast, do not include front-end processing and, so, require only 1 to 2 weeks of processing before reaching electrical test.

These loops use defectivity test chips instead of product devices and are typically limited to three lithography layers (two interconnect and one via).

The learning cycle time is much better 18

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than what can be obtained from product wafers (2 to 3 weeks versus 30 to 60 days). Here as with the bitmap loop, the electrical test data may be overlaid with inspection data so that images of potential killer defects may be collected with a SEM review tool. The effectiveness of this process is limited by the sensitivity of the inline inspection tools to capture the yield limiting defect types.

If the spatial correlation between the inline inspection and electrical data is good, an accurate yield loss Pareto can be developed to drive yield improvement efforts and quantitatively assess the improvement at the yield limiting defect level in hypothesis-testing experiments. If the correlation is poor, the technique does not provide the needed information to determine what needs to be fixed. The second problem with this approach is that the short loop process does not capture all problems that arise during the full flow process.

Finally, if the short loop vehicles are not designed with product-like structures, many of the systematic defect mechanisms that are related to layout will not be captured.

A new method for yield learning

Several years ago, KLA-Tencor began design of a new methodology to address many of the issues that limit the efficacy of the commonly used yield learning methods. In particular, the R&D group focused on developing a much faster system that would quickly identify and quantify the killer defects, allowing more time to be spent on fixing the problem than trying to find the source. The following underlying problems were the key drivers: 1. Obtaining the inspection tool sensitivity necessary to capture sub minimum space and high aspect ratio defects;

Yield Management Solutions

2. Separating the yield limiting defects from the total defect population; and, 3. Capturing both the random and systematic defects that are created when the full process flow is run.

KLA-Tencor’s µLoop methodology addresses all of these issues by combining non-contact electrical test with inline physical defect inspection to produce the fastest root-cause analysis method available in the industry today.

This new approach represents an integrated turnkey solution to electrical inspection that increases the speed and effectiveness of root-cause analysis by detecting and imaging electrical defects quickly, while minimizing the engineering resources required to gather and assimilate the root-cause data.

The components and overall process The integrated approach comprises these components: 1. Proprietary test chip designs 2. eS20XP e-beam inspection system 3. µLoop Controller integrated defect characterization, analysis, and reporting system The patented test structures for the chip are designed to meet the customer’s design rule and chip size requirements. Through close interaction with the customer’s design, module, integration, yield, and test engineers, the test chip can be made to address many defect issues related to product layout, as well as specific process-related problems and process window limitations. As a result, the layout and composition of the chip is tailored to the types and densities of random and systematic defect mechanisms of interest to the customer.

The chip can then be included as desired on either test wafers or product wafers, and may be as large as an entire die or small enough to fit within the scribe lines.

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Figure 4. µLoop uses custom test structures, e-beam inspection and an integrated defect characterization and yield analysis system to complete the yield learning cycle.

Figure 4 shows a general schematic of the µLoop cycle. The test chips are manufactured with the standard BEOL wafer processing. Upon completion of the fabrication of each interconnect layer, the eS20XP e-beam inspection system first captures the critical defects, and then the µLoop Controller characterizes the defects and provides customized defect and yield summary reports. These reports either help identify what defect problem needs to be fixed, or help assess the effectiveness of a process and/or integration change on eliminating the problematic defect type (steps 1 and 3 in the yield learning cycle described earlier). Experiments using the µLoop vehicle continue until the yield problem is resolved. Upon resolution of the current problem, resources are refocused on the next item on the Pareto.

of test structures optimized for performance and speed-of-inspection using KLA-Tencor’s e-beam technology (see the sidebar on voltage contrast inspection). By using a set of proprietary Area-Accelerated™ test structures, throughput enhancements of 10 to 25 times that of standard area-based e-beam inspections are available. A simplified example of this new class of test structure is shown in Figure 5. In this structure,

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which addresses interconnect opens and shorts, grounded and floating tines are inter-digitated similar to a comb.

Leveraging the properties of voltage contrast inspection discussed in the sidebar, these new test structures require inspection of only a small region at the bottom of the test structure. Electrical defects present along the length of the tine are transmitted down the tine and sensed through a large voltage contrast defect that appears as a deviation in the normal alternating grounded/floating tine pattern. Through this patented design both shorts and opens can be detected. The CD of the process sets the minimum sensitivity of the test structure measurement. Therefore, the test structures provide high throughput (through sampling) at high sensitivity (through voltage contrast defect amplification).

Grounded via chains are an alternate type of test structure that include large numbers of individual vias, offering a quantitative measurement of any systematic issue that causes a buried open in the via structure (also see the sidebar on random and systematic defect types). These structures are advantageous in that probing of each individual via is not required; again a voltage contrast defect will be detected at the bottom of the test structure if any via is open.

Via Opens (chains)

Via Opens (single)

The test structures and e-beam inspection The µLoop solution is based on the concept of voltage contrast inspection

Figure 5. This new class of test structure takes advantage of the properties inherent to voltage contrast inspection.

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Voltage contrast inspection

Step 1) Assess

Voltage contrast is inherent to all e-beam inspection technologies, but is only created under specific kinds of conditions. During inspection, a conductive material is exposed to a beam of electrons, and a number of the incident electrons collide with the atoms of the metal. A certain fraction of the collisions (depending on the type of metal) produce “secondary” electrons, which are re-emitted from the surface of the conductor at a much lower energy than that of the incident beam. This fraction of secondary electrons is also a function of the incident or “landing” energy of the primary electron beam and can be controlled to be less than or greater than one. If the conductor is isolated or “floating,” the difference in secondary electrons emitted versus primary electrons absorbed produces a net charge over the entire conducting node. When the landing energy is set so that the charge accumulated on the floating conductor is positive (more secondary electrons emitted than primary electrons absorbed), the node builds up a charge until the potential is large enough to inhibit the emission of more secondary electrons, and the node attains a static voltage. Secondary electrons can comprise up to 80 percent of the imaged electrons so, in this situation, the node can appear dark when imaged. In contrast, if the node is connected to a source of electrons (such as a grounded substrate), electrons from the source can flow to neutralize the charge build-up. This “grounded” node never builds a positive potential and so appears brighter than the floating node when imaged. This brightness difference between adjacent nodes can be used to indicate the relative voltage difference between the nodes, and can indicate the presence of an electrical defect.

The assess step is an AreaAccelerated e-beam inspection that quickly identifies the electrical defects across the entire wafer. The throughput of this inspection is maximized through the design of the test chip; due to the nature of voltage contrast, a high-sensitivity inspection is not required, and all of the VC signatures for a particular type of structure can be seen by sampling a small area of the chip. Because the test structure is divided into thousands of individual tines, rather than a large-area comb, the exact location of the defect in one dimension can be quickly identified. During this scan, both electrical and any type of physical defect in the inspected area are detected. Because physical defects are considered non-relevant in this step of the µLoop methodology, they are filtered out by the µLoop Controller, and the final result is a list of the electrical defects and their locations.

Typically, voltage contrast detection is used to complement physical defect detection in an e-beam inspector by providing some electrical information on the product defectivity. Use of voltage contrast defect detection alone to analyze overall product electrical yield is a complex process. However, voltage contrast can be used effectively with specially designed test structures to preferentially detect electrical defects, while rejecting physical defects that do not cause electrical failures. In this mode, voltage contrast defect detection has two important advantages: first, the presence of voltage contrast is an accurate indicator of an electrical failure on the node, providing a means for electrical inspection. Second, because a conductive node assumes the same potential across the entire node very quickly, regardless of size, voltage contrast can be used to both amplify very small physical defects into very large voltage contrast defects and to transmit the defect signature to a common region within the test structure. Using the defect amplification and transmission traits of voltage contrast, a class of test structures that is highly optimized for throughput and sensitivity can be designed.

Another key advantage of this methodology is that it is non-contact. Because there is no need for actual probing, there is less risk of contamination induced by the measurement, and thus the same wafer can be probed at all levels of the interconnect process.

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µLoop Inspection Methodology The complete µLoop inspection uses a three-step process: 1. Assess 2. Identify 3. Classify

Yield Management Solutions

Step 2) Identify The identify step finds the associated physical defects (see Figure 6). The previous step provided the x-coordinate of the physical defect, and although the y-location is not exact, it is bounded by the test structure height.

Using this information, a custom recipe is automatically generated for each wafer that is assessed. To facilitate the identify inspection, the wafer is rotated 90 degrees. This custom recipe provides an inspection test plan that includes only a small region around each defect detected during the assessment scan. Because the number of electrical defects is usually quite low, the total area inspected is very small (typically much less than 1 percent of the total wafer). The small inspected area helps to offset the impact on the throughput of the higher sensitivity conditions required for determining the exact location of the physical defects causing the critical electrical failures.

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types of analyses that quantify the yield killers. µLoop enables the generation of useful Pareto information in a much shorter time than with the conventional loops. The methodology also identifies and classifies 100 percent of the electrical defects on the test wafers. Obtaining comparable information would take prohibitively long using the standard loops and required failure analysis.

Outputs 251.00

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Integrated Analysis and Reporting LW=0.24/LS=0.72

LW=0.24/LS=0.48

Critical to the success of any yield learning cycle is the ability to quickly generate useful information for improving yield. Upon completion of the assess, identify, and classify steps, the µLoop Controller automatically generates a defect Pareto and data reports. In this way, the critical defect types and their quantitative

Figure 6. µLoop finds the physical defect associated with the electrical failure.

Step 3) Classify The classify step uses the information from the previous two steps for confirmation and classification of the electrical and physical defects. The

µLoop Controller takes images of each defect, and the user classifies the defects using an image gallery. All the data is stored and tracked by the µLoop Controller, enabling various

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Figure 7. Various yield analyses provide information to characterize the defect and determine its root cause.

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Root-cause analysis

In some situations, images of a defect are all that are required to know its source. Some yield and process groups have built up expertise over a period of time that allows them to determine root cause accurately based only on a defect Pareto. But in many situations, particularly with new processes and processing equipment, that luxury is not available.

Using the µLoop methodology in conjunction with inline inspections can accurately identify the specific layer at which the killer physical defects occur.

All critical layers of the test wafer are inspected with KLA-Tencor optical and/or e-beam tools, and then µLoop defect locations are overlaid with the inline inspection defect locations to determine the root cause. contributions to yield loss are immediately known, eliminating days, or even months, from the standard yield learning cycle. Analyses are also prepared based on the data stored by the system, including yield summaries, defect densities, defect images, defect size distributions, wafer maps (for spatial signature study), and defect type summaries for multiple wafers (see Figure 7).

These reports are configurable and can be automatically e-mailed to a distribution list if desired.

Application to yield improvement efforts

How should a fab use the powerful data provided by µLoop?

Providing Focus A typical problem less-experienced yield groups run into is having too much data and not being sure which problems to focus on in order to maximize the rate of yield improvement. Other groups become ineffective when they try to resolve all yield problems. The data from µLoop can be used to bring a more systematic and structured approach to yield improvement problems. This new methodology results in a defect type yield loss Pareto that quantifies the largest contributors to yield loss.

The best way to proceed is to use the information and systematically focus on the defects that are causing the 22

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greatest percentage of yield loss. As problems are resolved, the engineer refocuses on the next largest contributors on the yield loss Pareto.

Yield Learning The main use for µLoop (and the one primarily discussed in this article) is the yield learning application, where the goal is to rapidly identify and fix problems. Here, all three steps (assess, identify, classify) are used, along with a full report including the D0, Pareto, images, etc. The case studies in the subsequent sections of this article are all examples of using µLoop for the yield learning application.

Yield Monitoring Inline yield monitoring is another application of µLoop. The other short loop methods do not provide inline electrical testing information; their testing comes at the end of the line, when processing is complete.

The non-contact nature of µLoop allows electrical testing after each complete interconnect level. In this application, the three-step methodology is abbreviated to only the first step—the assess step—which gives the density of electrical failures. If this density is below a certain value, no further action is needed, and a simple inline monitoring report is generated. If there is an excursion of electrical failures, then the other two steps can be completed, generating the full set of information, with a

Yield Management Solutions

Pareto and images to help find the source of the excursion.

Providing Evidence to Help Engage Process Groups The yield group can use the information from µLoop to thoroughly characterize the primary killer defect type, with the ultimate goal of persuading the appropriate process and/or integration group(s) to engage and dedicate resources to fix the problem. The difficulty of convincing the process groups to assist should not be underestimated as a potential hurdle in the yield improvement process.

Often, the only way to accomplish it is to have thorough and quantitative characterization data showing specifically what percentage of the yieldlimiting defects came from that group’s process or equipment. The main results from the µLoop methodology (number of physical defects causing electrical failure, and a Pareto of those defect types) provide the convincing evidence needed.

Tuning Inline Inspections Another use for the uLoop data is to evaluate inline optical inspection recipes for their ability to capture yield-limiting defects. The defects, captured with inline optical and laser inspections can be characterized and compared with the yield limiting defects captured with the µLoop process. Inspection recipes can be optimized for use on product wafers to maximize the capture of top yield limiting defects capture with the µLoop process.

(See the sidebar on root cause analysis for further information about the integration of µLoop with inline inspection techniques.)

Comparison of the new method to previous methods

Agere Systems in Orlando, Florida, participated in a joint development

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project with KLA-Tencor to help develop the µLoop technology. The work was initiated because of the long cycle times the yield group had experienced with the standard methods it had used for BEOL yield learning.1 These methods included: • Product wafers used with bitmapping and failure analysis de-processing • Short loop comb and serpentine structures used with electrical testing, manual SEM review to locate the defects, and failure analysis de-processing • Short loop zone tester vehicles with combs and stitch test structures where killer defects were identified by overlaying electrical test and inspection data Two goals of the development project were to selectively capture only the yield limiting defects, and to minimize the yield learning cycle time. The first goal would speed the creation of an accurate defect Pareto pointing to the areas that need work, and the second goal would speed the hypothesis testing time, allowing for faster implementation of a fix.

Table 1 summarizes how effective each of the methods were in the identification of what problem to fix and the amount of time that was required to generate the information. The preµLoop methods required anywhere from 16 days to over two months to develop the initial Pareto due to deprocessing or data analysis time requirements. For some of the longer and more labor-intensive methods, the Pareto was built using only one or two wafers. The fastest of the preµLoop methods based the Pareto on a much larger sample of 25 wafers, but only captured 5–60 percent of the yield limiting defect population. In contrast, the µLoop method required only four days to create the yield loss

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Random versus systematic defects

Random defects are caused by the environment—the people and the processing equipment. A systematic defect, however, occurs because the process window is too small or isn’t centered correctly. Certain features will be the first to show a systematic layout marginality, so when the problem occurs it will show up in the same place. Historically, these problems have been hard to create and measure on anything but product, but now they can be captured by turning these features into test structures on the µLoop test chip. These systematic or “instance-based” test structures include many individually measurable replications of the feature. The advantage with µLoop is that these large areas of repeated features (for example, an array of vias or line/space features) are not limited in their layout by probe pads.

Another example of a systematic feature is a repetitive SRAM metallization structure. SRAM test vehicles are commonly used by fabs to assess back-endof-line process problems because they provide word and bit address locations of the electrical failures through bit mapping. The disadvantage of these BEOL test vehicles is that they require full processing of the front-end logic to support the bitmap testing. The advantage of using KLA-Tencor’s new methodology is that the same BEOL SRAM metallization structures can be designed into the µLoop test chip and then tested for systematic or random electrical failures without the need for the front-end-of-line (FEOL) processing, significantly reducing the time needed to get results. This is powerful, particularly in development, because often the SRAM vehicles experience FEOL-related yield problems, defeating their usefulness for assessing BEOL yield issues.

The systematic features on the µLoop test chip are beneficial for both current production processes and processes in development. If a current process is experiencing a systematic problem, the test chip features can be designed to simulate that issue. To speed development of a new process, the µLoop systematic structures can be used to project the effect of a design rule change on a worst-case feature set, testing the process window boundaries.

This testing can be made easier with the help of KLA-Tencor’s lithography simulation experts and software (PROLITH™). Utilizing this expertise in conjunction with the µLoop methodology simplifies the complex process of developing a high-yielding process integration module. Simulations allow investigations of the effects of process parameter settings and process errors on CD-limited yield, while the µLoop short loop methodology provides fast yield verification of the simulated results.

Pareto on 25 wafers. Because of µLoop’s use of e-beam inspection and voltage contrast techniques, 95–100 percent of all the yield limiting defects on the wafers were captured.

Further comparison of the different methods can be seen in Table 2, where the goal was minimizing the cycle time for the hypothesis-testing loop.

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The use of product for hypothesis testing was the worst option.

Product cycle times are relatively short but, by the time probing and testing are factored in and results are fed back to the engineer, can result in a 60-day cycle of learning and only provide probe yield results as a metric. The other methods provided

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were performed, and the µLoop Controller was used to characterize the yield limiting defects. The resulting yield loss Pareto, shown in Figure 8a, indicated that two primary defect types—“particles with extra” and “metal stack defects”—were responsible for the majority of the test structure shorts. Several additional repetitions were made with the µLoop process and the true dominant killer defect—“particle with extra”—was singled out. The defect characterization information, including defect images, composition information, and spatial correlation with inline inspection data, pointed to the metal etch process.

Implementation of solution

What needs to be fixed?

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Table 1. Comparison of the performance of various yield learning cycles for creating the initial killer defect Pareto.

metrics more relevant to the defect under study in the form of defect densities and short/open information. The µLoop methodology’s throughput was again far better than that of the other methods, and it was the only method to provide information on 95-100 percent of the defects causing electrical failures.

Overall, the µLoop method provided the capability that was desired and that was deficient in the previouslyused techniques. The µLoop method enables rapid construction of a yield limiting defect Pareto based on a large sample size and containing virtually all the killer electrical defects on the test chip. This technology also enables faster hypothesis testing, and provides a superior quantitative yield limiting defect metric that can be used to assess the success or failure of hypothesis testing studies.

Engagement:

Case study 1: Hypothesis testing on an aluminum process Introduction: One of Agere’s aluminum processes was yielding below the track goal. The problem was isolated to the BEOL using electrical tester data. The tester data, while indicating that the problem was localized to the interconnect level, did not provide information on the yield limiting defects contributing to the overall yield loss.

Problem Identification: One lot of µLoop test wafers were run through the metal 2 process. At the completion of the process sequence, e-beam inspection scans using the eS20XP Yield problem

The quantity of yield limiting defect data, coupled with the characterization information (images and compositional analysis), provided the evidence needed to engage the appropriate metal etch module process engineer.

Hypothesis Testing: This engineer proposed studying the effect of a new type of tool clean on the level of the “particle with extra” yield-limiting defect type. The µLoop data was used to provide the dependent metric for the studies.

An experiment was designed comparing the process of record, which

Yield Engagement learning of processing defect & integration identification

Hypothesis testing

Implementation of solution

Minimize cycle of learning time Case studies

Early versions of µLoop have been used to great advantage in over a year of practical application at Agere Systems. Three case studies of how µLoop was used for yield learning at Agere Systems follow.

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Table 2. Comparison of the performance of the various yield learning cycles for hypothesis testing.

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Figure 8a. Results from µLoop showing the initial yield loss Pareto.

ran on tool A, with the new “in-situ” cleaning process, which ran on tool B. The metric for quantifying the results was the density of “particle with extra” defects on the µLoop test chips. Initially, one lot was split, with the wafer processing spread out over a period of time to evaluate the effect of “chamber time since last major tool clean” on the level of yield limiting “particle with extra” defects.

In contrast, the tool with the experimental new clean did not show any increase over time. The same lot was used again with the µLoop methodology at the next metal layer; and, the additional data confirmed the initial results. Paretos were generated using µLoop before and after this process change was implemented. Figure 8c shows how the density killer defects changed over this time period. The improvement was very clear.

The results in Figure 8b showed degradation in the standard clean tool as more wafers were processed through it, leading to an increase in the “particle with extra” defect density.

Subsequently, “particles with extra” were still the dominant killer defect type on the Pareto, though at a much lower level, but now only a few wafers per lot showed high counts of this defect type. Additional µLoop experiments led to the discovery of a strong correlation between a certain

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process variable and the “particle with extra” defect count as illustrated in Figure 8d. Note, that for the data shown in Figure 8d, the correlation between the total number of killer defects and this process variable was not significant because of an excursion of tungsten puddles; this demonstrates the value of being able to break down the yield loss by defect type. A process adjustment to keep the level of this certain process variable down was devised and proven in using µLoop.

Implementation:

The decision was made to modify the process of record to include the in-situ clean based primarily on the results obtained using the uLoop technology. At the time of the change, the results from product data were inconclusive. µLoop greatly accelerated the implementation phase for this first process change. The second change did not require board approval and was implemented soon after the compelling results from µLoop were obtained.

Summary: µLoop was used to quan-

tify the contributions of the various defect types to the overall yield loss and to pinpoint the area needing the most work. Next, it was used to test several process improvements and their ability to reduce the level of yield limiting defects, and to track their effectiveness over time. This study highlights how the use of the µLoop process offers a cycle of learning at

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each interconnect level for a particular lot. It led to a 4x improvement in the time needed to implement these process changes. With µLoop, these changes were implemented in only one and a half months; using the conventional methods they would have taken at least six months.

Case study 2: Capture of a systematic problem on an aluminum process Introduction: The practice of periodically running µLoops for a number of technologies to track and characterize the BEOL yield loss Pareto was instituted early in 2001 at Agere Systems. Often, these same wafers are also used for hypothesis testing experiments. The ability of the µLoop methodology to break down yield loss by defect type allows the same lot of data to be used for both purposes.

In this example, a systematic problem was detected on the outer periphery of the wafers in an aluminum process for the latter metal levels.

Problem Identification:

The initial full flow µLoop lots for this technology detected significant yield loss at the wafer edge for the metal 4 interconnect level. A wide line, minimum space comb test structure had been placed on the chip in order to test the extreme limits of the design rules. All metal lines tended to be wider at the wafer edge and this particular structure was shorting in what appeared to be random places in this zone. Soon after this discovery, significant product yield drop-out was observed at the wafer edge.

Routine inline inspection of product had not provided evidence of any type of problem; many of these shorts were very difficult to pick up even with a SEM. Cross-section and other characterization work indicated that there was a large variation in the wafer topography around the outer edge of the wafer. This variation, coupled with the limited lithography 26

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depth-of-focus, was enough to cause a printing problem and subsequent metal line shorts.

Summary:

In summary, µLoop provided an inline vehicle to capture a problem that was not captured with inline defect inspection tools and that would typically require time-intensive failure analysis techniques to characterize. The issue was a systematic problem captured with a systematic test structure specifically included to test for it. The only reason this problem had not been detected earlier with µLoop was that the µLoop test chip had only recently been developed.

Secondly, the µLoop wafers, which were processed with the entire process sequence, captured a problem that would not have been captured on a short loop (1- or 2-level) process sequence. The problem also would not have been captured on the normal, nominal line and space test structures. The problem was confined to the wide line/narrow space structures.

Engagement: The wafer topography problem could be caused by one or more process steps used to complete the interconnect process. A team was formed, including process and integration engineers, to develop a solution to the problem.

Hypothesis Testing Experiments:

The team ran several studies to minimize the topography variation across the wafer surface. The µLoop methodology was made available for hypothesis testing and was utilized to evaluate one idea. The ultimate solution was not initially tested with the µLoop methodology since direct measurements of the wafer topography were more appropriate. Once the team had developed an acceptable solution, the µLoop wafer results indicated that the problem of metal line shorts no longer existed around the outer periphery of the wafer.

Case study 3: Early yield learning on a copper process Introduction: Yield learning on new

technologies is especially challenging due to the large number of defects present on wafers as new processes are being developed. Attacking all of the different defect types at the same time diffuses the available resources and results in slow yield improvement.

The key to success is to obtain a yield

Implementation:

The process change, which was a CMP hardware modification, was implemented.

The ensuing yield data from µLoop was one of a number of validations that the outer edge systematic yield problem was eliminated.

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loss Pareto that allows one to focus improvement efforts on the defect types that contribute the most to yield loss. In this example, a yield loss Pareto was developed for wafers processed early in the development phase.

Problem Identification:

A short loop tester containing the µLoop test chip was processed through the metal 1 copper interconnect process.

The µLoop structures were scanned on the eS20XP and the defects were characterized using the µLoop Controller. The Pareto showed that the majority of the wafers had more shorts than opens—an unexpected result—and the most common defects were distortions of the oxide trenches, photo resist bubbles, and flakes.

Based on this information, the yield group was able to prioritize their future improvement efforts to maximize yield learning.

Here the µLoop methodology was used to overcome the common problem of defect noise in the development phase, and enabled the fast separation of the yield killers from the general defect population. µLoop Summary

Fast yield learning for the back-end-ofline has become even more challenging and essential with the introduction of increasingly complex interconnect processes and smaller design rules.

The efficiency of the BEOL yield

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learning process has improved significantly with the introduction of µLoop, which enables (1) a reduction in the time to complete a learning cycle from weeks or months down to days; (2) multiple cycles of learning to be obtained from each µLoop lot; (3) the construction of a yield limiting defect Pareto that provides a quantitative assessment of the yieldloss contributors; (4) characterization of the yield limiting defect with compositional analysis; and (5) the capture and identification of systematic defects that are created by integration issues or are exacerbated by multi-layer topography.

Yield groups can take advantage of KLA-Tencor’s expertise and revolutionary BEOL yield management technology, requiring them to invest fewer resources and less time and money in the complex and difficult process of developing BEOL test chips and yield learning methods.

The benefits they receive in return are tremendous: reaching yield goals faster, getting to market faster, and reaping potentially hundreds of millions of dollars in increased profit.

References 1. Henry, Todd, “Application of eD 0 to Accelerate BEOL Yield Improvement Activities,” KLA-Tencor Yield Management Seminar, October 2001.

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YIELD

There are many paths to yield.

But these days, only the fastest route will do. That’s

in optimizing your manufacturing process. All strategically

why we focus relentlessly on shortening your journey.

formulated to enhance your bottom line. And put you on

With best-of-breed solutions designed to let process

the most efficient road to yield. For more information,

control contribute directly to profitability. Yield

please visit us on the Web

acceleration expertise that’s as deep as it is broad.

at www.kla-tencor.com,

And industry neutrality, for unprecedented flexibility

or call 1-800-450-5308.

©2001 KLA-Tencor Corporation

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eS20XP Receives Semiconductor International’s

2001 Editors’ Choice Grand Award On October 30, 2001, Semiconductor International’s Senior West Coast Editor, Alex Braun, presented KLA-Tencor with the prestigious Grand Award for its eS20XP scanning e-beam wafer inspection system.

Established in 1989, Semiconductor International magazine’s Editors’ Choice Best Product Awards program, recognizes 20 products used in semiconductor and related manufacturing.

This year, KLA-Tencor’s eS20XP system was singled out as the Grand Award winner in recognition of its contributions to the industry in accelerating the development and production ramp of new semiconductor processes, including copper and low-κ dielectrics.

Customers cited the eS20XP’s industry-

leading throughput and sensitivity as key to enabling them to significantly reduce their electrical defectivity and yield-learning cycle times on their latest-generation devices.

“The Editors’ Choice Best Products program differs from other awards in that products must be nominated by users, not by people who make or sell them.

A product that receives this award has been verified to demonstrate superior and proven production capabilities that advance semiconductor innovation and manufacturing,” noted Peter Singer, Semiconductor International editor-in-chief. “This was most clearly the case with KLA-Tencor’s eS20XP ebeam wafer inspection system, which

led our editorial team to select it as the Grand Award winner out of this year’s 20 winners.”

The eS20XP detects electrical defects during front-end-of-line (FEOL) processing at speeds unmatched in the industry. Using state-of-the-art voltage contrast capability, it detects electrical defects during front-end processing, inspecting an entire wafer in little more than an hour compared with days required by previous-generation and competitive e-beam systems. Because it enables fab engineers to find electrical defects at the source layer instead of at back-end-of-line (BEOL) electrical test, the tool dramatically reduces the risk of weeks or months of work in progress (WIP) to exposure to these yield-killing defects.

The eS20XP also detects physical defects as small as 50 nm, as well as defects in high-aspect-ratio structures, which are extremely hard to detect using other inspection techniques.

“It’s truly an honor for us to have received this award,” stated Rick Wallace, executive vice president of KLA-Tencor’s Wafer Inspection Group.

“The eS20XP represents one of the most successful product introductions in KLA-Tencor’s history. It is the most widely adopted e-beam inspection system on the market, with the vast majority of leading logic, DRAM and foundry manufacturers having purchased it for use in their advanced design rule production lines. This proves, once again, that customer satisfaction is the greatest testament of all to our success.”

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Using the Feature Model to Define CD In the last edition of this column I described the feature model, a simple mathematical shape with a small number of parameters that is used to approximate a much more complicated real feature crosssection. Figure 1 shows the most common feature model used for extracting critical dimensions (CDs), the trapezoidal feature model. As I mentioned last time, the necessary use of an overly-simplified feature model to extract a single CD value from a complex resist profile has two fundamental error sources (independent of any measurement error): error in the use of a simplified feature model and errors associated with the method of finding the “best fit� of the model to the actual feature.

Since the choice of the feature model is based both on relevance and convenience, and since the trapezoid is so commonly used for CD metrology, the impact of the feature model choice will not be discussed here.

When fitting the feature model to the data, there are many possible methods. For example, one could find a best fit straight line through the sidewall of the profile, possibly excluding data near the top and bottom of the profile. Alternately, one could force the trapezoid to always match the actual profile at some point of interest, for example at the bottom.

Whenever the shape of the actual profile deviates significantly from the idealized feature model, the method of fitting can have a large impact on the results.

For example, as a lithography process goes out of focus, the resist profile and the resulting feature size will change. But because the shape of the resist Chris A. Mack, KLA-Tencor profile is deviating from a trapezoid quite substantially at the extremes of focus, CD can be a strong function of how the data was fit. Figure 2 compares the measured CD through focus (as simulated with PROLITH) for two different feature model fitting schemes: a best fit line through the sidewall and fitting the trapezoid to match the actual profile at a set threshold (height above the substrate). Near best focus the two methods give essentially the same value since the resist profile is very close to a trapezoid. However, out of focus there can be a significant difference in the CD values (>5%) based only on the fitting method used.

In real metrology systems the actual resist profile is never known. Instead, some signal (secondary electrons versus position, scattered light intensity versus wavelength) is measured that can be related to the shape of the resist profile. This signal is then fit to some model, which ultimately relates to the feature size being measured. Although a bit more complicated, the same principles still apply. Both the feature model and how that model is fit to the data will affect the accuracy of the results.

Figure 2. Using resist profiles at the extremes of focus as an

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Figure 1. Typical photoresist cross-section profile and its corre-

example, the resulting measured feature size is a function of how

sponding "best fit" trapezoidal feature model.

the feature model is fit to the profile.

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The Best Laid Plans of 300 mm Fabs Anantha Sethuraman, Sagar A. Kekare, Raman Nurani, and Dadi Gudmundsson, KLA-Tencor Corporation

The move to 0.13 µm, and the introduction of new materials and processing methods such as copper, low-κ materials, and phase shift reticles, are byproducts of the demand for more powerful ICs. As a result, the yield management challenges are difficult, but somewhat anticipated for a move to a smaller design rule. Some of the associated defect samples planning aspects, such as employing e-beam inspection in addition to optical techniques, have been explored 3. For the first time in recent memory, the semiconductor industry is witnessing the convergence of shrinking design rules, the transition to 300 mm, and implementation of new materials in the interconnect scheme such as copper and low-κ dielectrics. The fact that the 300 mm transition is taking place, along with other transitions, creates unique challenges and opportunities in yield management that warrant a new focus in defect sample planning.

Although the transition to new materials and smaller design rules are definitely technology-enabling endeavors, such efforts are not without their characteristic yield management challenges. However, many of these challenges would have been encountered without the 300 mm transition taking place simultaneously. Supposing no 300 mm transition were taking place, previously established sample planning exercises could be performed effectively, with only moderate changes in focus, to establish effective yield management strategies. This paper has been organized to reflect those challenges and provide some insights to surmounting them. The first half of the paper covers in detail some of the 300 mm process-induced challenges, while the second half covers the classical defect inspection sampling problem from a 300 mm standpoint. The detailed discussion of 300 mm processinduced challenges provides a guideline to where new defect inspection points may emerge. Besides suggesting the incorporation of these potential inspection points into 300 mm sampling plans, the latter half of the paper addresses how sample planning in 300 mm fabs needs to take place alongside layout and automation plans for optimal effect.

300 mm technological & processinduced challenges

Films Module Films processes are generally viewed as two somewhat separate categories: planar films stacked on a substrate, and films targeted towards optimal gap-fill to avoid translation of topography. The planar film-stacks such as STI nitride, gate poly-silicon, or refractory metal for silicidation are mostly affected by defects like particles, flakes, pinholes and voids. In addition to these defects, the gap-fill films may have other unique defects when they fail to achieve their primary function of filling a gap between features. Many times such unique defects may not be captured right after deposition, as they stay hidden deep into the folds of these films. Examples of these films are STI HDP oxide, spacer nitride, PMD doped silica glass, IMD doped silica glass for Al interconnects, etc.

With advent of copper dual damascene technology, a much larger fraction of films in modern fabs have gap-fill function as their prime objective. Absorption and adhesion between each of the films within a desired film stack is a prime factor that controls the continuity and conformity of such film stacks. Electrochemically deposited copper is especially sensitive to the existence of a sputtered seed layer during the nucleation stage for the copper film. Voids are almost the predominant defect in copper films due to this tendency. New methods in Winter 2002

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processing bring about a new set of defects to a module.

The circular motion of the wafer in a non-optimal electrochemical bath may result in concentric swirl patterns in deposition.

Variations in film deposition rate would be magnified with 300 mm wafers. Larger area coverage would accelerate film stress related failures like warping and cracking. Stresses could induce stacking fault type defects at the silicon-STI interfaces near the edges of the wafer.

may result in damage to the substrate, which may be intolerable. Non-uniformity in removal rate may leave behind under-etch residues and stringers.

High aspect ratio features are ubiquitous with the increasing adoption of copper dual damascene technology.

Shrinking design rules combined with high aspect ratio allows for small process drifts to result in gross defectivity such as through under-etch or distorted features.

Difficulty in removal of passivating etch byproducts from the high aspect ratio features is another source of defectivity.

Litho Module Lithography is clearly the most complex process module in modern fabs. Along with the quantum leaps in exposure tools and ancillary systems, this module faces a rapid introduction of new consumables and film substrates. These conditions, combined with radically new mask technologies, present a significant challenge for defect control and yield entitlement.

Etch chamber design has evolved from the baseline 200 mm configuration into the 300 mm configuration.

Gas flow, plasma induction, and location of the exhaust port contribute to the non-uniformity of etch action.

With a larger wafer area, these issues can be expected to remain important, if not grow in significance.

CMP Module Resist backsplash, developer spots, focus hot-spots, missing pattern, resist collapse, etc. are some of the most common defects encountered in the litho module. The integration of the new tools, materials and consumables is a formidable task for litho module optimization.

Photo-resist poisoning from inorganic ARC, thin pattern lines broken due to micro bubbles, CD variation across the chip due to grid snap, OPC errors during mask making, and partial printing of sub resolution assist features are only a few examples of the current defectivity that stem from the integration challenges in the litho module. Process development efforts that combine the parametric and defectivity aspects of module optimization will achieve early yield.

Bake-oven temperature non-uniformity and variation in the focus offset across the wafer are two principle causes for across-wafer CD variation. With the 300 mm wafer size, the oven-related variation should contribute a much larger fraction of CD variation across the wafer.

When combined with sensitive techniques like OPC and phase shift reticles, such variations may become the root cause for a significant portion of litho defectivity.

Etch Module Etching is controlled removal of part of a film stack using exposed photo-resist pattern as the masking layer. Hence many of the defects from lithography will potentially be carried through the etch step. In addition to these defects, etch tools may flake off the passivation layer condensed on the chamber walls. Loss of selectivity 32

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Chemical mechanical planarization was introduced to recover a planar wafer surface through removal of undesirable topographic features. The dielectric layers were amenable to this technique, with tungsten plugs being mostly defined by CMP in the last few device generations. Due to the unique combination of chemical dissolution and mechanical abrasion, the defects generated during CMP were quite unique in themselves.

The defects ranged from the simple residual slurry and scratches to more complex interactions like delayed corrosion and coring of interconnects. Additionally, CMP also brought to light the film defects caused by inefficient gap-fill.

Copper dual damascene technology has shifted the focus of process development from dielectric CMP to metal CMP. Copper CMP is being brought to high volume IC manufacturing for the very first time. This shift in the objectives of BEOL CMP from planarization to full-fledged interconnect definition brings about a slew of defectivity and process control issues. All films in the copper module belong to the gap-fill category.

Moreover the dual damascene features have higher aspect ratios than previously encountered in IC processing.

This gives rise to seams and folds forming along the feature during deposition. CMP exposes these hidden defects in the form of co-axial voids. CMP may also generate voids through the copper grain rip-out phenomenon. Any unbalanced chemistry of the slurry compound may result in delayed corrosion of the copper features.

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When polishing a larger area, however, the preliminary reports seem to suggest that removal rates become more uniform across the wafer. Since multiple techniques of CMP are still in the evaluation phase, it will be difficult to state this observation to be universally applicable.

state of the art stepper/scanner platforms. This validates the need for following the dual-pronged approach to early process development and characterization on the well layers (refer to Figures 1 and 2).

Gate Dielectric Deposition Emerging defect inspection points

N/P Well Lithography The N/P well region masks contain extremes in feature size. In the memory regions, where the wells are placed very close to each other in a very regular array, the mask features are long lines under 2 microns wide, whereas in the peripheral control logic, the mask may feature larger rectangles tens of microns wide on both sides. Typically, the process development for this layer is low priority and a nominal process window is decided with a single data point collected per field from a focus exposure matrix wafer using a CD SEM. Since this data collection point does not truly represent the process windows for the entire range of features on the mask, there is always a risk of some feature falling out of the usable process window with a minimal drift in focus offset. However, with shrinking minimum allowable dimensions of well layer, this risk has assumed a greater significance.

As the operating voltages scale down, power consumption specifications tighten and performance requirements shoot up, and the gate dielectric quality becomes extremely important for the device. The inspection at pre-gate dielectric growth/deposition should focus mainly on the physical phenomenon that affect the dielectric quality. These are crystal-originated pits (COPs), scratches from STI CMP, and any other surface contamination. Although 300 mm wafers handling will be fully automated, the transition from 200 mm to 300 mm

Long thin area

This risk can be mitigated early on during the process development phase. An approach that looks at both, the parametric as well as the defectivity performance of a given process is the correct way to provide early mitigation of this risk.

Older 200 mm-stepper platform designs will be ready to process 300 mm non-critical layers with some additional modifications of the chuck and auto-focus systems.

However, these systems may have a greater challenge in maintaining across wafer focus offset as compared to the

True process window

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Figure 2. Schematic of process window for two distinct features on a given reticle, indicating the overlap region as the true usable process window.

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Weak sites possibly due to COPs

Figure 3. a) A cumulative probability plot of a highly defective gate dielectric indicating unacceptable proportion of weak sites. b) An AFM rendering of cr ystal-originated pit type defects.

may inherently cause the wafer to possess more COPs type of defects as incoming material. Scratches that translate through the STI nitride into the substrate silicon are known to affect the device characteristics adversely. This log point will serve to weed out defective wafers at an early stage in the process, thereby saving considerable processing costs (refer to Figure 3.)

contact resistance levels. An inspection log point at Silicide RTP 2 will capture the evolution of such defects for an early root cause analysis8 (refer to Figure 5).

The above sections have outlined emerging 300 mm processing issues that may point to the need for amended or expanded defect inspection plans in 300 mm processing. Being aware of those issues is one part of the puzzle

N+ / P+ Implant Lithography

Silicide RTP 2 Cobalt silicidation is extremely sensitive to the presence of any oxide on silicon. However, any native oxidation arising from rinse dry spots, etc., is not detectable prior to silicidation. Similarly any remaining inorganic ARC on top of the gate poly-silicon is not detectable prior to silicidation. Yet, these may result in a population of unsilicided sections, each as large as the smallest design rule gate CD. Unsilicided regions usually have high 34

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Tighter process windows warrant stringent process centering

Process Window

Similar to the N/P Well masks, these two masks also contain a large range of feature size. A region of butting implants may not get silicided if each implant is pulled back due to the litho CD widening. Similarly resistance to junction breakdown may suffer if the litho CD is shrunk. An early optimization of process window through a defectivity and parametric characterization will prove extremely beneficial in avoiding these integration roadblocks (refer to Figure 4).

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similar. However, we are not producing one die at a time and, therefore, excursions will occur at shorter intervals then in 200 mm processing. This may require every lot to be sampled at some layers, where that was not justified in 200 mm processing.

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in creating an effective sample plan in a 300 mm fab.

Combining these emerging issues with known inspection points in 200 mm processing, the space of inspection points can be defined (to the extent it is possible without extensive actual 300 mm processing data). Now a larger scale methodology needs to be applied to identify capable inspection equipment, calculate inspection capacity required, and allocate it effectively across the fab. The following paragraphs address these issues.

Defect detection challenges in 300 mm

A variety of new challenges to defect detection are introduced during the move from 200 mm to 300 mm.

First, there is the need for detection over a larger surface area. This requires modification of existing hardware.

Second, and more importantly, is the use of new materials. This will change both the composition and type of defects encountered, requiring new techniques for their capture and automatic classification. Third, the size of “killer� defects decreases with the move to a smaller design rule, requiring an increase in tool sensitivity.

Fourth, new inspection requirements, such as wafer backside inspection, become important, prompting the redesign of inspection tools. Finally, from a broader perspective, there are issues such as the need for seamless information exchange between defect detection and review tools, processing of greater amounts of data, and the need for automation of the defect sampling process, in keeping with the overall fab-automation initiative.

In addition to the above, it is expected, and initial pilot line/ramp experiences confirm, that excursion rates can be higher. To some degree this is merely the fact that excursion frequency is measured in wafers. If one were to measure the frequency in number of dies between excursions, then the rates may be somewhat

The yield management industry is well on its way in providing the tools and techniques necessary to deal with the above-mentioned challenges, but this capability needs to be deployed correctly. With major 300 mm fabs in the planning stages, a unique challenge and opportunity in yield management arises. By including yield management in the planning stage a fab can be predisposed to deliver superior yields. Further emphasizing the need to include yield management in the planning process is the fact that 300 mm fabs will have processing and inspection tools bound together with various automated material handling systems. This will, inherently, make fab layouts and material flow less flexible, and emphasizes the need for setting the fab up correctly the first time. Towards that goal, the following sections address the concepts and methods that should be employed to effectively include defect sample planning in the fab planning stage.

Process integration-induced defectivity in copper interconnects

Spin-on and CVD low-Îş dielectric films are replacing the PECVD doped silicate glass films for BEOL interlayer isolation. These new films possess characteristics that make their integration markedly different. These films do not fulfill a gap-fill role. They are planar films that are patterned with trenches and holes later to be filled with electroplated copper. The patterning is done with DUV process, with alignment of subsequent photo steps gaining critical importance. Electroplated copper is highly sensitive to surface conditions and needs a high quality seed layer of copper for uniform film growth. Copper being a deep level impurity, a thorough encapsulation of all interconnects is necessary to prevent the copper from diffusing into the silicon.

Tantalum nitride or tantalum barrier films are deposited prior to the seed layer to achieve this objective. Once filled with copper, the etched pattern is redefined by planarizing the excess copper through use of CMP. The process steps mentioned above are complex in themselves. In addition to that, they need to be optimized for their combined process margin. One element of this optimization is the need to eliminate possible defect generation through interaction of these processing steps.

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A few striking examples of how killer defects are generated through such interactions are discussed below with schematics in Figure 6 (a) through (i).

Photoresist poisoning from PECVD low-Îş dielectric films

In the dual damascene scheme of etching, the second patterning step is exposed to the dielectric film with- Figure 6a. Missing via. out a capping layer.

The amine radicals from the nitrogen containing film alter the development reaction of the DUV photoresist. This leads to curious defects such as mushroomed or missing vias.

Film discontinuity due to etch profile non-ideality

An overhanging or barreled via profile leads to shadowing in the path of sputtered barrier and seed Figure 6b. Barreled via profile leads to a hidden void in copper. layer films. Absence of seed layer will lead to incomplete filling of copper into via holes. Such a void will remain hidden from optical inspection and will prove to be a truly silent killer defect.

Pattern density dependence of copper polish rate in CMP

Dense regions tend to demonstrate a propensity for slower polish rate. Slower polishing increases the probability of Figure 6c. Copper puddles. copper puddles or residues between a dense array of lines, which may lead to bridging shorts and circuit failure.

Translation of previous layer topography into the current layer

Variation in metal polish rates due to pattern density 36

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dependence may lead to flatness variation in the next inter-metal dielectric layer. Such variations could prove fatal for the already shrinking process windows for DUV lithography. It Figure 6d. Scratch filled with copper. becomes imperative to implement dielectric surface polish steps to bring the overall flatness within an acceptable range. A scratch from such dielectric CMP may get filled with ECP copper and act as a stringer or a bridging short.

Defects from metal deposition process exposed during CMP

Electrochemical plating of copper is extremely sensitive to hindrances to nucleation and growth. These hinFigure 6e. Voids and seams in copper. drances could be non-uniformity of seed layer or it could be residues from SEM review of seed layer due to carbon condensation. A void may get embedded in electroplated films, where the copper failed to adhere and nucleate. Such embedded voids can be exposed during polishing of copper. Some electroplating conditions are prone to bread-loafing, and generate a seam along the axis of trench in which copper is deposited.

Such a seam shows up after CMP as a row of voids along the center of a copper line.

Corrosion and material non-compatibility

The CMP process has a large chemical aspect to it. Copper CMP typically proceeds in an acidic environment. Nearing the endpoint, the acidic Figure 6f. Corrosion in copper. electrolyte is now in contact with both the barrier layer and the copper line.

This leads to the formation of a galvanic cell, resulting in corrosion of copper lines along the barrier interfaces.

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Corrosion attacks may also take place along the triple points in the copper microstructure, leaving distinct pitting type defects behind.

Impact of annealing conditions and timing in the integration sequence

Electroplated copper films are polycrystalline. An annealing treatment is necessary to optimize the grain Figure 6g. Cross section schematic. size and stresses in copper films. However, the thermal energy available from the Grains annealing is utilized for void growth and coalescence. Such void growth may seek low free-energy sites such as grain boundaries or interfaces for condensation into large voids. Figure 6h. Triple point voids in copper.

If the annealing is done prior to CMP, then these condensed large void regions give rise to defects such as rip-outs, voids along the line edges and broken lines. If the annealing is done post-CMP, sub-surface Figure 6i. Condensed voids in copper. voiding may result from condensation of voids along the bottom of the via or the side of the trench.

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is not the correct metric in which to base the amount of inspection capacity needed. Instead, one should seek to maximize the profitability of the fab and employ the inspection capacity needed to reach that goal. When calculating that capacity, fabs need to pay attention to several factors that collectively are embodied in a yield management strategy. A fundamental analysis of process tool, material handling, andinspection/metrology capacity planning is required. Furthermore, the impact of inspection on yield and cycle-time needs to be understood to provide a return on investment (ROI) that is optimal. Strategies will then vary depending on the fab (development or production), device (memory, logic or mixed) and segment (captive or foundry).

The transition to 300 mm has a larger impact on the economic aspect of wafer manufacture. Transferring processes with low baseline yield into the ramp phase lacks economic viability or, worse still, will become fiscal disasters. This further reinforces the value of a high yield learning rate being present early. Preliminary analysis shows orders of magnitude difference in the value of yield learning for 300 mm processing. Table 1 contains some of the parameters used and Figure 7 shows the results. It can be observed that there is a much greater return per yield learning percent increase in 300 mm processing than in 200 mm processing. Although a high yield learning rate is not only dependent on the available inspection capacity, a lack of inspection capacity can certainly be the limiting factor in the yield learning process and would most definitely be the differentiator in the long run between leading-edge companies.

ASP/cm2 of silicon Wafer starts per week Die size Starting D0 Fault learning rate per month

$40 1000 1.5 cm2 0.65/cm2 4% 1

Economies of scale and yield management

The fundamental premise of the 300 mm initiative is economy of scale, i.e., to decrease the manufacturing cost per square centimeter of silicon. It is estimated that the manufacturing cost per square centimeter of silicon will be about 30 percent lower. As one would expect, the pressure on improving yield management to produce more good dies at a lower cost is increased. It is, however, simplistic to enforce the same cost performance on yield management needs without considering the whole picture. Using the guiding principle of reducing inspection cost per square centimeter of silicon by 30 percent

Table 1. Parameters in yield learning rate analysis .

After the ramp-up phase is finished, the excursion control mode of yield management takes over for the full production phase. Again the 300 mm fab is faced with the dilemma that while the initiative provides considerable economies of scale in chip production, each wafer is much more valuable and that greater amounts of material are at risk to excursions than in 200 mm production. Calculating the relative value of 300 mm yield losses relative to 200 mm yield losses in the full production phase is much simpler than for the ramp-up Winter 2002

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inspection capacity will be needed for the full production phase in 300 mm processing. KLA-Tencor has a wellestablished methodology to do sample planning for both the full production and ramp up phase of the fab. This methodology has the capability to address the 300 mm defect sample planning challenges. The following paragraphs address this methodology and its application to fab planning.

Figure 7. Comparison of opportunity gained in 200 mm and 300 mm processing for a range of increased yield learning rates. The insert explains the definition of an increased yield learning rate, a traditional yield learning rate is in blue and an increased yield learning rate in purple.

phase. Utilizing the applicable inputs from Table 1, and assuming that the wafers starts per week are 4,000 in this phase, we can calculate the value of lost materials each month relative to the same in 200 mm processing (see Figure 8). Numerous results in sample planning analysis2, 3, 7 have shown that the amount of inspection capacity to be used should be based on the value of the materials that can be saved. Given the vast value difference shown in Figure 8 it is expected that greater

300 mm defect sample planning

It has become well accepted that defect inspection tools play an important role in a fab’s yield management strategy. While few manufacturers currently operate without some type of defect inspection, many IC manufacturers tend to view inspection as non-value-added

Inspection Method?

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and are overly conservative when planning inspection capacity. It is here that the sample planning problem arises: what types of inspections to perform; where to locate them in the process; and how frequently to perform the inspections. To answer these questions, an effective method involves the trade-off between the cost of inspection operations, both fixed and variable, and the cost and/or risk of yield loss due to undetected yield-limiting defects and process excursions.

The main decision parameters are: • Placement of the inspections (which process steps/process tools) • Type of inspections (test wafer, product, or in-situ inspections) • Inspection frequency (percent lots to sample, number of wafers per lot, area per wafer) • Inspection sensitivity to use • Which parameters to track and respond to (Statistical Process Control scheme), • The fraction of defects to review • Inspection tool capacity All these parameters are inter-related, and each one gives rise to a set of variables that need to be understood.

KLA-Tencor’s Sample Planner 3 (SP3) cost model provides the framework and tools to analyze critical fab parameters to develop an optimal inspection strategy with reasonable effort. By combining it with analysis performed during fab planning, the fab plan can be devised to have inherent advantages in yield management.

In its simplest form, the cost model methodology is based around a recurring in- and out-of-control cycle occurring at each step in the process. A cycle starts where each step in the process is assumed to have an in-control mode of operation, which delivers a high yield. After a random length of time, an excursion takes place, causing lower yields. At this point, the inspection sampling strategy determines how quickly the excursion is caught and fixed, restarting the in- and out-ofcontrol cycle. It is sought to minimize financial loss by catching the excursions quickly, i.e., minimizing the time between excursion start and detection. It is here that accounting for yield management during fab planning is relevant. A significant portion of the delay to excursion detection is simply the time to get lots to the inspection tools. If a fab has badly placed tools and/or automated material handling systems that cannot accommodate

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the extra handling loads due to yield management, detection delays can be unnecessarily long and costly.

Planning to prevent this type of problems is simply a classic sample planning problem with a greater focus on material handling and cycle-time modeling to provide the data needed that characterize a fab layout. Therefore, outputs of material handling and cycle-time modeling performed during fab planning need to be made available to sample planning analysts who, in turn, can give feedback on the current fab plan strengths and weaknesses in excursion detection. The importance of having short detection delays to achieve the accelerated, and very valuable, yield learning rates should also be noted.

Fab planning with sample planner 3

Involving SP3 in fab planning requires the fab to provide good models for material-handling and cycle-time estimation. Then, by combining the outputs of these models with pilot line or applicable 200 mm data to characterize process variance and defect/excursion behavior, SP3 can quantify the yield losses to excursions.

Typical analysis may involve the comparison of farm and hybrid layouts. A farm layout is where all the metrology tools are kept in a separate bay, while a hybrid layout has the metrology tools in the same bay as the process tools they are monitoring. A good materials handling model will be able to provide the travel times as a function of the track layouts, number of stockers, number of automated vehicles, the load on the system, etc. Joining that with a cycle-time model that accounts for processing and queuing times, a comprehensive estimation of how long it will take lots to reach their inspections is realized for both the farm and hybrid layout. SP3 can than use these results to quantify which layout will cause greater yield loss to excursions.

Assuming that the material handling system and the number of inspection tools used is the same for both layouts considered, the differentiation comes down to the losses due to excursions. The analysis can clearly involve greater complexity where the cost of different material handling options and inspection tool capacity needs to be accounted for as well.

Initial 300 mm work and past experience have highlighted the following as the main drivers for inspection capacity: • Fab output (square centimeters of silicon/week) • ASP/product Winter 2002

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• Excursion frequency, types, magnitude, & yield impact • Tool capability/sensitivity • Material handling in fab/distance to inspection tools • Inspection tool throughput/queuing Conclusion

The economies of scale that are achieved with the 300 mm initiative have a flipside when it comes to yield management. The value of the material on each wafer is greater and more sensitive to excursions than ever before, calling for a much more careful planning and deployment of inspection capacity. Of concern is the possible emergence of new inspection points that are detailed in this paper. This is particularly relevant given the level of automation that is planned for 300 mm fabs that make it harder to alter layouts after the fact.

Unless a fab correctly accounts for yield management during fab planning, there is risk of giving a fab an inherent handicap in yield management and losing considerable amounts of material to excursions. Those losses can significantly affect the gains foreseen from the economies of scale that drive the 300 mm initiative.

References 1. Chatterjee, A. Personal Communication, Nov-Dec 2000, KLA-Tencor, San Jose, CA.

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2. R. Elliott, R. K. Nurani, S. Lee, L. Ortiz, M. Preil, G. Shanthikumar, T. Riley, and G. Goodwin, “Sampling plan optimization for detection of lithography and etch CD process excursions,” in proceedings of SPIE Metrology, Inspection, and Process Control for Microlithography XIV, vol.

3998, pages 527-536, 2000.

3. Nurani, R., Gudmundsson, D., Preil, M., Nasongkhla, R., Shanthikumar, G. Critical dimension sample planning for sub-0.25 micron processes. Proceedings of the 10th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, September 8 - 10, 1999.

4. Nurani, R.K., Gudmundsson, D., Stoller, M., Shanthikumar, G. Intelligent Sampling Strategies for Combined Optical/E-beam inspection. Yield Management Solutions, Vol 2, Issue 2, Spring 2000, p 28.

5. Wright, R. et al., “300 mm Factory Layout and Automated Material Handling”, Solid State Technology, December 1999.

6. Campbell, E. et al., “Simulation Modeling for 300 mm Semiconductor Factories”, Solid State Technology, October 2000.

7. Williams, R.R., Gudmundsson, D., Monahan, K., Nurani, R., Stoller, M., Shanthikumar, G. Optimized Sample Planning for Wafer Defect Inspection. IEEE International Symposium on Semiconductor Manufacturing, Santa Clara, California, October 11-13, 1999.

8. S. A. Kekare, et al. “Integration issues in effective removal of SiON anti reflective coating used in deep sub-micron CMOS gate layer definition.” MRS meeting-Spring 2000.

Reprinted with permission from Semiconductor Fabtech. This ar ticle was originally published in Fabtech, Edition 15. http://www.semiconductorfabtech.com

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Time-to-Detect Frames the Integrated Debate Ralph Spicer, Dadi Gudmundsson, and Raman Nurani, KLA-Tencor Corporation

Is integrated defect inspection really the wave of the future? Analysis shows that a simple particle detection strategy is unlikely to be more cost effective than a comprehensive excursion inspection strategy, even if the particle detection can be integrated to a process tool.

The decision whether or not to integrate defect inspection onto process tools is one of the most important decisions facing 300 mm fab planners. This decision impacts everything from capital procurement strategies, to automation, to floor-planning, to data systems integration. And, once made, this decision is expensive, if not impossible, to change as the fab approaches first silicon.

Therefore, it is important to understand the real variables behind this decision, moving beyond surface arguments that would appear to point strongly in favor of integration.

This article discusses the relevant issues that must be analyzed when making decisions regarding the deployment of integrated versus non-integrated defect inspection in a new 300 mm fab.

significantly, making it vital to forecast such variables through several design rules before deciding on a strategy. When all of these considerations are taken into account, our analysis shows that the fact that particle detection can be integrated to a process tool does not necessarily make it the most cost effective strategy for 300 mm fabs.

Trends affecting the decision

In order to determine whether or not an integrated inspection strategy makes sense for the fab, it is important to understand the variables that drive yield losses, and how technology trends are affecting these variables.

CYCLE TIME Cueue Times Automation

Layout

The decision to integrate

Recent arguments for integration cite equipment productivity as the driving variable upon which the decision should be based. While this is an important factor, it is also important to consider variables that drive yield, such as process tool excursion frequencies, defect kill probabilities, and the detection capability of the integrated and non-integrated systems being considered, as illustrated in Figure 1. Furthermore, while productivity-related variables remain relatively constant through design rule generations, the yield-related variables scale 42

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STEP YIELD

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Fastest Ramp Highest Yard Minimum Cycle Time

Figure 1. A multitude of factors must be considered when deciding on an inspection strategy for a 300 mm fab. These include productivity factors such as cycle time and process tool output, and yield factors such as step yield, process development, and the capabilities of the inspection technology.

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The two primary yield-related variables are: Defect types:

Does the inspection strategy have a high probability of detection (pd) for the defect types that cause yield loss? Will it keep up with the (as yet unknown) defect types that will occur as design rules shrink and new processes such as copper dual damascene, low-κ dielectrics, DUV resists and SOI are introduced?

Will it be able to adapt as yield learning in the fab proceeds?

Time to detection:

Does the approach minimize the time to detect the excursion? Can much of the benefit of integration be achieved through well-planned product flow and automation instead?

With probability of detection and time to detection as the two main variables, a summary question arises: Is it better to detect a larger variety of excursions with some delay, or detect a subset of excursions with little delay?

We studied this question as a part of a comprehensive study of integrated inspection technology. The results of this study led to the following key observations: • The excursion detection capability of a robust, comprehensive inspection strategy appears to outweigh the time-to-detect (td) benefits of integration.

• Significant time-to-detect (td) benefits may be achievable through optimized automation and fab layout without the loss of flexibility and added capital cost associated with integration. Integration per se has little incremental benefit once automation and fab layout are optimized.

• The choice of inspection strategy must include provisions for future trends, such as new copper and low-κ defect types, and the growing importance of process margins and systematics as a source of excursions.

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The industry has extensive experience in optimizing fab yield and productivity through the use of standalone inspectors. In the paragraphs that follow, we will review some of this experience, and focus on the issues that an integrated inspection approach can introduce to a fab.

Defect types

A robust excursion control strategy must be capable of finding the defect types expected in today’s aggressive design rules, and must be adaptable to find the new types that are certain to occur in the future. Simple particle detectors are suited to find one particular defect type (large particles), but provide no capability in detecting other killer defects. True wafer inspection captures both process-induced and tool-induced defect types with a high probability of detection (pd).

Examples of these defect types for Cu CMP are shown in Figure 2. Particles, of course, are captured as well, making additional particle detection inspections unnecessary.

New processes and advanced design rules

At advanced design rules, defect densities must decrease to achieve viable yield1. As defect densities fall, the definition of an excursion becomes tighter, meaning that the inspection system must be able to detect smaller and smaller amplitude excursions without an undue increase in false alarms. The choice of appropriate inspection equipment typically includes a requirement for multiple-design-rule reuse; this is not supported by simple particle detection technologies.

While it could be argued that particle detection technology is likely to improve in the future, such technology will remain behind the need as advanced design rules and new materials like copper and low-κ dielectrics are introduced. As design rules shrink, fewer excursions are caused by people and process tool contamination, making

Scratch

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Micro Scratch Voids (from EP)

Figure 2. A comprehensive defect inspection strategy must detect the wide range of defect types that can cause yield loss. Many of these defect types, such as these Cu CMP defects, cannot be captured by simple particle detectors.

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particles a less important part of the picture relative to process-induced defects. This is due to the fact that environmental and equipment-induced particle sources are steadily being reduced and do not scale with design rule to the same extent as margins and systematics that are continually being pushed at each successive design rule generation, making such issues more likely at each successive design rule generation2.

Inspection’s role in fast ramp

The ability of a fab to quickly ramp new processes is a major contributor to profitability. The faster the ramp, the faster the time to market, the higher the average device ASP.

unexpected problems tend to dominate. An inspection strategy that is to be effective during ramp must be able to capture defect types that cannot be predicted a priori.

In contrast, once the fab reaches entitlement yield, it is less likely that new defect types will occur, making defect inspection much more predictable. This might lead to one asking whether the fab should invest in sensitive inspectors for ramp and development, and then switch to particle monitoring equipment during production, even though non-particle defects would still be present to some degree.

Two important trends indicate that more sensitive tools are needed throughout the fab’s life, as shown in Figure 3.

First, the yield “hurdle” that a process must pass prior to moving into ramp and production is moving ever higher, with a faster ramp. This means that there is less and less time to qualify lesser-capability inspection equipment to check that it finds the defect types identified during development. Secondly, the time period between process changes is decreasing, meaning that

The choice of inspection approach can have a major impact on the fab’s ability to ramp quickly. This is because the problems being solved during ramp are of a very different nature than those being solved during high volume production. During development and ramp, problems tend to be unpredictable; that is, new,

Trend: shorter time in high volume production

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Figure 3. Development and ramp drive fab profitability: the faster the ramp, the faster the fab can profit from higher ASPs. Most fabs are always in the development and ramp states, even after years of time, as new processes and shrinks replace older, lower ASP production products.

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Figure 4. A robust process tool monitoring approach includes the ability to feed back learning from more sensitive line monitoring inspectors.

Without this feedback, it is difficult to control new excursion types introduced by new processes or design rule shrinks.

the typical fab is always in a development/ramp state.

The net result is that today’s fab requires ever-morecapable excursion inspection capability to detect everchanging defect types.

These observations imply that a robust tool monitor defect inspection approach must incorporate the learning from higher-sensitivity line monitor inspectors, as depicted in Figure 4. This allows the tool monitor inspectors to be tuned for new excursion types that are certain to be introduced by process changes or design rule shrinks. Experience suggests that without this vital feedback loop, it is impossible to sustain yield learning over time. While state-of-the-art standalone defect inspectors are able to adapt via this feedback, simple particle detectors cannot. Thus, a key element of excursion control would be eliminated were an integrated particle detector strategy to be chosen.

Operational aspects of integration

The decision to integrate has major operational impacts to the fab: • One inspector is required for each process tool or cluster, meaning that there are more inspectors in the fab • Each inspector is tied to its process tool, meaning that a given inspector can only inspect wafers from its process tool.

Obviously, capital cost is a major consideration. Typical standalone implementations utilize a ratio of anywhere from 4:1 to 10:1 (that is, 4 to 10 process tools per inspector). Unless the integrated particle detectors are significantly less expensive than the standalone defect inspectors, the increased quantity of inspectors leads to a higher capital investment cost for the fab. Also, integrated inspectors add to each process tool’s footprint, reducing product output per unit area.

False alarming is also a major consideration. Operators and engineers must respond to each report of an excursion as it occurs. As the simple technologies employed by particle detectors are readily confused by processinduced pattern variation on product wafers, they risk a higher incidence of false alarms than defect inspectors that incorporate technologies developed specifically to suppress such pattern variation. It is easy to see how a larger number of particle detectors, each false alarming more often, would lead to an intolerable distraction on process operations, or, worse yet, lead to process operations which either ignore alarms or “dumb down” the recipes to prevent them. These are situations that would completely negate the benefits of integration.

Reliability is also a concern. With the particle detector dedicated to the process tool, a failure in the detector leads to a downed process tool (leading to lost productivity), or skipped inspections (leading to a possibility of an undetected excursion). Unless MTBFs and MTTRs of the particle detectors can be raised to levels many times better than that which is achievable today, Winter 2002

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the sheer number of inspectors in the fab implies that at least one inspector will be down nearly all of the time, along with its associated process tool. A standalone approach, on the other hand, allows lots to be routed around downed inspectors in a way that is difficult with integration.

Past studies of excursion control in 200 mm fabs indicate that the average time between lot processing and excursion detection in a typical fab can be eight hours or more3. This means that the average excursion affects yield across several lots of wafers before the source of the excursion is identified and action taken. One of the primary perceived benefits of integrated inspection is that this time is reduced significantly, since wafers can be inspected soon after processing. But, integration of the inspector to the process tool is only one way to reduce this time. For example, reducing queue and transport time from eight hours to two hours via efficient layout and inspector utilization would gain much of the benefit of integration while retaining the flexibility of a standalone inspection strategy. Such 300 mm automation concepts as multilevel transport and intrabay shuttles hold promise in making this feasible.

We plan further modeling studies to quantify how these operational variables feed into the decision of an optimized excursion detection strategy.

Modeling integrated versus standalone strategies

Given that there is significant industry effort toward integrating particle detectors, we set out to answer the question: which approach minimizes excursion losses in the fab: (1) a simple particle detector integrated to each process tool, or (2) a comprehensive defect inspection strategy implemented in a standalone fashion? Our preliminary results are that the second approach is the optimal strategy for the process steps we studied.

Using KLA-Tencor’s Sample Planner™ software4, we were able to model the effects of defect type capture and inspection delay (such as that caused by transit, queueing, and inspection times) on the overall yield loss for various process steps. An example of the results of this study for Metal 3 etch are shown in Figure 5.

The two curves show the value of inspection at Metal 3 etch for a 5000 wspw, 300 mm logic fab relative to performing no inspection at this step. As one would expect, the value increases as time to detection (td) decreases, since excursions are caught sooner. However, 46

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this increase in value is much more pronounced when a comprehensive defect inspection strategy is used, since the particle detection approach misses many excursions entirely, negating the benefit of decreased td. In fact, the cost of missed excursions is so substantial that, even with an eight-hour td, the standalone inspection approach provides a 30 percent yield benefit over an integrated particle detection approach ($1.3 m/year versus $1.0 m/year).

The cost of the inspection tools has to be considered when comparing the value curves in Figure 5. When large scale integrated defect inspection was first conceptualized, it was clear from the start that each integrated inspector would have to cost considerably less than a standalone tool. This is clear from the fact that standalone tools are serving anywhere from four to ten process tools and an integrated inspector would serve only one tool. For this analysis, whether standalone or integrated inspection is used, it can be assumed that the overall inspection expenditure is the same. This arises from the observation that the price of integrated tools for our example are about a third of the standalone tool price. In addition, this particular example required slightly less than a third of a standalone’s tool capacity to serve one M3 etcher. That same etcher would require a single integrated inspector for itself, demonstrating the approximate cost equivalence. This follows the trend that to make integrated tools feasible they have to be cheaper; unfortunately, that can only be realized at the expense of detection capability.

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reduction when using comprehensive standalone inspectors.

Baseline Yield

We now explain in more detail the key variables that drive excursion-related yield losses, and how these were analyzed to produce the values in the above figure.

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What is an excursion?

Excursions

An excursion is defined as an out of control condition at a single process step which impacts yield until the excursion is corrected. As shown in Figure 6, a fab’s baseline yield rises over time as yield learning is achieved. Excursions represent temporary dips in this yield, corresponding to a loss of profit. The goal of a comprehensive yield management program is one that raises baseline yields as high as possible as quickly as possible (hitting the “sweet spot” of high device ASPs), coupled with an effective strategy for preventing and minimizing the impact of excursions during volume production.

Time Figure 6. The baseline yield of the fab drives its baseline profitability.

Excursions represent temporar y drops in yield, resulting in lost profit for the fab.

yield learning are harder to model, but experience shows that these benefits would further tilt the results in favor of comprehensive standalone inspectors.

In order to determine the best strategy for minimizing the financial losses from excursions, it is important to understand in greater detail where these losses come from. Figure 7 shows a more detailed timeline of an excursion and its losses for two situations: when the

These results indicate that substantial benefit can be derived through effective material handling time

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Figure 7: The financial loss due to an excursion consists of two primar y elements: yield loss due to wafer scrap and/or die yield impact, and loss due to reduced productive tool time. An excursion that is not detected by the defect inspector increases yield loss dramatically.

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defect inspector detects the excursion (upper half of figure), and when it does not (lower half of figure). Three points in time define the timeline: (1) the time that the excursion event occurs, (2) the time that the chamber (e.g. deposition chamber or polishing head) is taken down, and (3) the time that the chamber is returned to production.

Before the excursion event occurs, production lots are being processed normally. When the event occurs (for example, a problem with one etch chamber), product continues to move through that chamber, causing lots that will have to be partially or completely scrapped.

This occurs until the event is detected and confirmed, and the chamber is taken down. Then, the tool is serviced, during which time no product is being processed by the chamber. Finally, the chamber is confirmed fixed, and processing resumes.

The shaded regions of the figure depict the losses that occur. First is the yield loss (Ly). This is defined as the time to detect the excursion (td) times the cost of the yield loss (cy) per hour. Second is the process tool productivity loss (Ltp). This is the number of hours it takes to repair the chamber and bring it back into production (ttp) times the capital cost of the tool per hour. To give some sense of scale to the timeline, our experience in 200 mm fabs indicates that an average number for td is approximately eight hours, and for ttp 16 hours, in cases where the excursion is caught.

The cost of yield loss (cy) is driven by two variables: excursion yield impact, and die ASP. Yield impact is the probability that a given excursion type will cause an electrical failure in a given die. For example, a micro excursion might cause sparse defects that kill, on average, 25 percent of the die on the wafer (yield impact = 0.25), whereas a macro excursion might impact every die on the wafer (yield impact = 1), leading to complete wafer scrap.

For the case where the yield impact is less than 1, one might expect cy to scale with the yield impact; that is, a yield impact 0.5 excursion would lead to a cy of half of the yield impact 1 value. However, wafers will still be scrapped completely if the number of failed die exceeds a threshold beyond which the cost of continuing the wafers’ processing does not justify the smaller number of good die that will result.

One immediate observation is that the cost of excursions is influenced heavily by product and yield-related 48

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variables. So, while it may appear that an obvious integrated strategy would be to set a capital cost target for process tools’ integrated inspector (say, 20 percent of the process tool’s cost), this is likely not the cost-minimizing approach. The cost-minimizing approach takes into account the cost of yield loss for the process step. For example, benchmarking studies indicate that the typical inspection investment is higher for early metal layers than for later metal layers, due the tighter design rules and higher defectivity encountered there, even though the exact same process tools are being used. One side effect of integrating inspection into the process tool is the absence of this kind of investment flexibility. For a complete discussion of this topic, see reference5.

Another observation is that great leverage can be obtained by reducing td by reducing the time it takes to make a tool up/down decision. By removing the possibility of incurring queue time at standalone inspection, td can be reduced dramatically. This is the obvious attractiveness of integrated inspection.

However, past experience indicates that a missed excursion is usually not detected until days later, when the lot is inspected by a more sensitive line monitor inspection, by the next step’s tool monitor inspection, or worse, by back end final electrical test. Most fabs have had the painful experience of an extensive “yield bust” because of a defect type that was not detected by the inspection equipment.

A higher probability of excursion (pe), combined with a lower probability of detection (pd), make this undesirable scenario more likely. Another way of looking at the same issue is to use a weighted value for the time to detect, Td(effective) = td(caught) * pd + td(missed) * (1-pd) Given the potentially immense losses associated with missed excursions, it is dangerous to choose an inspection strategy without analyzing pd.

To analyze pd, we utilized a historical root cause database and benchmarking data, combined with a survey of process experts to create an exhaustive list of the defect types and frequencies typically encountered at various process steps. We then assessed the capability of various inspection and particle detection approaches against these defect types. A subset of this assessment is shown in Figure 8. Here, the frequencies of excursion are multiplied by the pd for that excursion type to

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Figure 8. Defectivity benchmark and defect root cause data were used to evaluate p d for various inspection technologies.

generate the results we showed earlier (see Figure 5).

The comprehensive standalone approach indicated greater benefit than the integrated particle detection approach. Again, these results do not include the benefit of fast yield learning, a benefit that experience shows to be substantial.

We found that simple particle detectors missed a significant number of the excursion events at state-of-theart process rules, reducing pd considerably when compared to today’s standalone tool monitor inspectors.

This, combined with the comparable effective throughput of darkfield inspectors and particle detectors (due to real-world factors such as wafer handling and alignment time), leads to a summary of average pd vs throughput for various inspection technologies such as that shown in Figure 9.

1

We then loaded the resulting probabilities of detection (pd) and throughputs into the Sample Planner™ model, which allowed us to more accurately model the interaction between the probabilities of detection, excursion frequency, sampling strategy, integration approach, and real-world issues such as transit and queue times.

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obtain an event-weighted pd for the process step for various types of product wafers. These are then combined to obtain a die-weighted pd. Of course, this analysis is not static. As process tools mature and design rules shrink, we expect a decrease in the frequency of particle excursions, and an increase in the frequency of process-induced excursions.

E-beam Inspection Brightfield Inspection Darkfield Inspection Particle Detection Low High Throughput (Wafers/Hour)

Figure 9. The p d for particle detectors is significantly lower than

We modeled a range of td, from the historical average of eight hours of td, to an optimized standalone td of two hours, and on to an integrated td of 15 minutes to

currently available darkfield, brightfield, and e-beam inspectors, with effective throughputs comparable to darkfield inspectors. This is in direct relation to the lower cost of integrated inspectors.

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On the application front, metrology is applicable to advanced process control concepts such as feedforward (e.g. modifying the etcher recipe based on film thickness measurements) and feedback (e.g. modifying deposition tool parameters based on measured results from previous wafers). Defect inspection, on the other hand, does not lend itself to such applications: what would one adjust on an etcher were an excursion to be detected by the defect inspector?

Process control considerations

One obvious question that arises is: if the economics of integrated inspection do not appear favorable, why is there so much activity revolving around integrated technologies? The answer lies in the fact that three very different classes of integrated technologies are being pursued: integrated metrology, integrated particle detection, and integrated defect inspection. The differences among these applications are significant (as shown in Figure 10), and so it is vital to analyze each separately.

It is important not to confuse the technology and applications of integrated metrology with those of defect inspection.

One proposed compromise solution for defect inspection is the particle detector, which performs a type of defect inspection, but is able to capture only one type of defect (large particles). As we showed earlier in this article, capturing large particles is insufficient to prevent costly yield busts due to lengthy out-of-control conditions.

This is why particle detection does not lead to an optimal solution, even if it is integrated to the process tool.

On the technology front, the nature of the items to be measured (the targets) are known with certainty. Therefore, once a technology has shown an ability to measure targets with the required accuracy (for example, spectroscopic ellipsometry’s ability to measure film thickness on multilayer stacks to 0.5 percent) in a form factor which supports integration, there is higher confidence that integration may be an appropriate path.

Conclusions

Our conclusion is that a particle detection strategy is not likely to provide benefit over a comprehensive standalone inspection approach, even if particle detection can be integrated to process tools.

In contrast, defect inspection must take into account the added complexity of full-wafer scanning, which implies a highly variable background signal (the pattern) which reduces the signal-to-noise ratio of the inspection.

The complex image acquisition and processing algorithms required to achieve a useful signal-to-noise ratio are not currently available in an integrated form factor. In fact, because this problem becomes more difficult as design rules shrink, it is a distinct possibility that adequate wafer inspection performance may never be available in an integrated form factor.

This conclusion was driven by these observations: • The excursion detection capability of a robust, comprehensive inspection strategy appears to outweigh the time-to-detect (td) benefits of integration. • Significant time-to-detect (td) benefits may be achievable through optimized automation and fab layout

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Figure 10. The applicability of metrology to process control applications means that the decisions regarding the optimal approach for metrology are ver y different from those for defect inspection.

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without the loss of flexibility and added capital cost associated with integration. Integration per se has little incremental benefit once automation and fab layout are optimized.

• The choice of inspection strategy must include provisions for future trends, such as new Cu and low-κ defect types, and the growing importance of process margins and systematics as a source of excursions.

These observations suggest that integrated particle detection may not necessarily be the future trend that conventional wisdom might suggest. Integration of inspection will only become viable when integrated inspection technology is comparable to standalone technologies, and today’s candidate integrated particle detection approaches are not near this point. Even in the long run, the fact that inspection requirements scale with the design rule suggest that the crossover point at which integrated inspection becomes viable may be a long way off, if it appears at all.

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The authors would like to acknowledge the contributions of Wayne McMillan, Anantha Sethuraman, Paul Marella, and Sanjay Tandon to the study.

References 1. Stapper, C.H., Fact and Fiction in Yield Modeling.

Microelectronics Journal, vol. 20, no. 1-2, 1989, p.129-151 2. Jensen, D. State of the Industry Address, 1995.

3. Esposito, T. et al. Automatic Defect Classification: A Productivity Improvement Tool. Conference proceedings IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, p. 269-276.

4. Williams, R.R., Gudmundsson, D., Nurani, R.K., Stoller, M., Chatterjee, A., Seshadri, S., Shanthikumar, J.G. “Challenging the Paradigm of Monitor Reduction to Achieve Lower Product Costs”. The 10th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, September 8 - 10, 1999.

5. Williams, R., Gudmundsson, D., Monahan, K., Nurani, R., Stoller, M., Shanthikumar, G. Optimized Sample Planning for Wafer Defect Inspection. IEEE International Symposium on Semiconductor Manufacturing, Santa Clara, California, October 11-13, 1999.

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commitment to faster yield ramps. As a result, the fab’s director identified our partnership as critical in helping reach 200 mm-equivalent yields on their very first 300 mm customer lots. Just another reason why more fabs depend on us to help make yield ramps – and ROI – look their very best. For more information, please visit www.kla-tencor.com/300mm, or call 1-800-450-5308. ©2001 KLA-Tencor Corporation

Accelerating Yield

Yield Management Seminar A valuable venue for innovative ideas KLA-Tencor’s Yield Management Seminars (YMS) focus on value-added, integrated process module control solutions for defect reduction, process parametric control and yield management.

Key topics include navigating the transition to the sub-0.13 µm technology node, with special emphasis on copper/low-κ interconnect, sub-wavelength lithography, and the 300 mm wafer.

To register online for the upcoming YMS, please visit us at: http://www.kla-tencor.com/seminar Date: Wednesday, January 30, 2002 Time: 1:00 pm – 6:00 pm Location: Shanghai, China

Call for future papers Papers should focus on using KLA-Tencor tools and solutions to enhance yield through increased productivity and performance. If you are interested in presenting a paper at one of our upcoming yield management seminars, please submit a one-page abstract to: Cathy Silva by fax at (408) 875-4144 or email at cathy.silva@kla-tencor.com.

YMS at a Glance DATE

LOCATION

January 30

Shanghai, China

April 17

Munich, Germany

July 23

San Francisco, California

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CMP: Where Does It End? Ron Allen, Charles Chen, Tom Trikas, Kurt Lehman, Robert Shinagawa, and Vijay Bhaskaran, KLA-Tencor Corporation Brian Stephenson and David Watts, Ebara Technologies Inc.

We describe the design, operation, and algorithms for an in-situ CMP endpoint detection and control system, with particular emphasis on copper polishing. The system’s eddy current-based sensor gives absolute surface metal thickness. Its multi-angle reflectometer gives eight optical reflectance measurements. The endpointer improves on existing sensors and techniques in several ways. It can process reflectance traces individually according to their endpoint sensitivity, which applies to dielectric polishing and copper barrier removal processes. Also, it merges reflectance signals for higher signal-to-noise ratios, which benefits copper CMP. Finally, the system can fuse the reflectance data with thickness readings for more robust endpoint detection.

Introduction

Chemical Mechanical Planarization (CMP) is a widely accepted polishing and patterning method in microelectronics fabrication.

Though CMP is indeed crucial to some processes—copper (Cu), for instance, for which plasma etching remains problematic—process engineers must still cope with underpolish and overpolish problems.

Stopping a metal polish step too soon (underpolishing) leaves metal or barrier material residues, which cause electrical shorts in the target layer. Underpolishing dielectric films causes open circuit defects.

Polishing too long (overpolishing) results in metal dishing and dielectric erosion, ultimately leading to metal pooling and short circuits in higher metal layers. Simple time-based polishing is widespread in fabs.

But Cu electroplating produces film thickness variations that thwart timed recipes, and the requisite rate monitor wafers are becoming prohibitively expensive. CMP tool conditions such as temperature, pad condition, and wafer pressure profile also affect the polish rate and uniformity.

To facilitate CMP integration into largevolume production, process controllers must have cross-wafer information available and monitor each wafer’s polish profile to 54

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determine the process endpoint (the precise time at which the target material has been removed) or the remaining requisite layer thickness. KLA-Tencor’s Precision In-Situ CMP Endpoint (PRECICE™) system addresses these issues by providing real-time film thickness measurements, reflectance data, and endpoint detection for a variety of polishing processes, including Cu CMP. Design: sensors, controller, and communications links

The system contains an eddy current-based sensor; a single wavelength, multi-angle reflectometer; a data acquisition and control processor; and communication links to the CMP host computer. The sensors mount beneath the CMP tool’s rotary platen (Figure 1). The eddy probe has a drive coil that induces a current in the wafer, a sense coil to find in-phase and quadrature components of the induced voltage, and signal generation and data acquisition electronics1. The control computer’s calibration curves give absolute metal thickness values, independent of temperature and pad wear. The standard optical sensor wavelength is 808 nm. Two methods exist for creating an optical path to the wafer: a flexible polyurethane window inserted into the pad and a self-clearing objective (SCO) that uses a timed flow of deionized water (DIW). Thus, wafer incidence angles vary; with a SCO they range from 6.7° to 56.3°.

A rotary union and slip ring on the table shaft bring fluid lines and electrical paths to table-mounted sensors.

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where φm is the magnetic flux (webers/m2) linking the coil.3 Let εo be the open coil EMF generated when the sense coil is not over the wafer. As the probe scans the wafer, primary flux enters the Cu layers, inducing an EMF, and thus an eddy current by Ohm’s law. The eddy currents reduce the primary flux. As the sense coil passes over thicker Cu regions, the flux moves through deeper layers of metal, decreasing the linkage flux, and reducing the voltage magnitude across the sense coil from εo (Figure 2). Calibration of the sensor involves an estimate of εo and a measurement of ε for a Cu sample wafer of known thickness, such as may be measured with a four-point probe. A referencing scheme is employed to compensate for temperature and pad wear.

For pass k over the wafer and each wafer sample n, the metal thickness is

TABLES AND FIGURES

Proximity sensor

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T(n) = Scal[||ε(n) – εo(k)|| – Dcal]*Cpt(k) – Wres, Figure 1. System layout, top view. Proximity sensor triggers data acquisition as eddy probe passes carrier ring. Slip ring passes serialized eddy and optical data to controller. Dual-platen polishers, such as Ebara’s FREX-300™, may have CW rotation tables; such setups have proximity flags before the reflectometer.

In typical operation, the host computer downloads recipe data to the endpoint controller (Fiure 1). After a delay for polish process stabilization, data acquisition from the eddy current probe and the multi-angle reflectometer begins. A proximity sensor, or, alternatively, the indication of the metal carrier ring from the eddy current device, triggers acquisition. Sensors report data on every platen revolution. The electronics serializes the data and passes it through the slip ring assembly to the computer. Before the next trigger, the controller’s algorithm software analyzes the data for characteristic endpoint features. When the algorithms detect the recipe’s prescribed endpoint feature, the endpointer notifies the host, which stops the current polish step.

(2)

where ε(n) is the complex EMF; εo(k) is open coil EMF; Scal and Dcal are calibration scale and offset, respectively; Cpt(k) is the pad and temperature compensation, and Wres is an optional offset for a low resistivity wafer substrate.

The multi-angle reflectometer can be understood through modeling the reflectance and transmission through the optical objective to the wafer.4 The wafer

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consists of isotropic media M0, M1, …, Mm+1; with complex refractive indices N0, N1, …, Nm+1; where M0 is the semi-infinite ambient (e.g., DIW); Mm+1 is the semi-infinite wafer substrate; Mi has thickness di, 1 ≤ i ≤ m; the angle of incidence is φ0; and the angle of refraction in Mi is φi, 1 ≤ i ≤ m+1. The 2×2 scattering matrix is the product S = I01L1I12…LmIm,m+1/(t01t12…tm,m+1),

(3)

Wafer areas do not clear uniformly, of course. To spatially resolve endpoint declarations, the system either (1) divides the wafer into simple annular zones or (2) computes the actual sensor path. The sensor electronics samples at uniformly timed rates so, in either case, the sensor spots do not cover the wafer uniformly.

The carrier and platen (Figure 1) rotate at Rc and Rp RPM, respectively, so their angular orientations are:

ω(t) = 2tπRc/60

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Thus, via p- or s-polarization values, the wafer transmission coefficient is t = (S11)-1, the reflection coefficient is r = S21/S11, and so the reflectance is R = |r|2.

Varying di at Mi’s polish rate and computing R at each step produces a model of the CMP process. The model (Figure 3) establishes threshold and time delay parameters for endpoint detection algorithms.

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Endpoints of interest to the Cu CMP process engineer are: bulk copper to a specified thickness, copper clear, and barrier clear. Endpoint on eddy probe values (2) is as simple as specifying the absolute target thickness. Thin Cu endpoints rely on reflectance values whose endpoint behavior is governed by the thin film model (3)-(6).

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new coordinates of the point will be (10) This means that after rotation by ω(t), the coordinates of the sensor over the wafer, relative to the (u, v) coordinate system will be

(11) Figure 4. Reflectance data from an edge-slow polish of a 200 mm

Once thick Cu clears locally, the system relies on the optical sensors to find remaining thin patches. The algorithm, a conventional blob analysis5, is as follows: (1) Cu reflectance values are combined to get a composite optical trace (Figure 3), (2) the algorithm sets a reflectance baseline Rb across the wafer. At this time, Cu is still fairly thick, and the reflectance should be near its theoretical average (slurry effects and process step changes can harm the Rb calculation, but standard process trend and control chart techniques greatly mitigate the risk6); (3) Points where Cu remains are found by comparing reflectance to this baseline value. Thus, if T is the threshold, and Rm is the measured reflectance, then Cu is present at sample n if Cu (n) = 1 ⇔ Rm (n) ≥ T * Rb (n) •

(12)

(iv) Median filtering the Cu array fills narrow gaps between high R regions. (v) The width of the contiguous Cu regions is determined, and where the width exceeds a percentage of a zone width, a Cu blob is declared for the zone. If W is the zone width, Tw is the threshold, and Blob(m,n) means there is a Cu blob in the region [m, n], then we have Blob (m,n) ⇔ Min {Cu (k) | m ≤ k ≤ n} = 1

&Cu(m – 1) = 0&Cu(n + 1) = 0&n – m ≥ W*Tw

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The percentage of blob points that intersect a zone is calculated from the blob array. Though the system acquires data at fixed time intervals, the wafer samples are not uniformly spaced. However, the sensor path (11) gives the spatial extent of Blob(m,n). Precession calculations using the carrier and platen RPM provide the relative location between successive wafer sweeps.

(4) Finally, Cu clear endpoint occurs when the percentage of blob points in a zone is less than a threshold. A time

patterned Cu wafer.

delay, proportional to the sensor path (11) coverage of wafer zones, reduces false positives. Figure 4 shows reflectometer data for a 200 mm Sematech 931 patterned Cu test wafer.

The Cu thickness and reflectance values can be fused.

One technique fits a regression line to thickness values to predict clearing. The reflective patch analysis (12)(13) confirms Cu clearing. Another method is to optimize a local thin film model using the measured reflectivity and thickness values.

Conclusion

The eddy current sensor measures impedance vectors as opposed to simple scalar measurements offered by competing eddy current devices. Absolute measurement makes CMP process recipes easy to establish, reliable, and portable. Absolute thickness capability also allows tools to be dynamically controlled for within-wafer uniformity. After bulk metal clear, the application software merges the eddy current and reflectometry sensors’ data streams within their overlapping ranges; a crisp and repeatable soft landing to the copper-clear endpoint results.

Multiple angle reflectometry advances CMP monitoring and diagnostics by giving process engineers more repeatable and flexible control over endpoints. Software can combine these reflectance signals, improving signal-to-noise ratios, or analyze them separately, for increased robustness of endpoint control on certain thin metal films. Depending on the process and film stack properties, some angles may give a stronger endpoint signal than others (Figure 3). Real-time wafer mapping Winter 2002

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of metal thickness, non-uniformity, and copper patches allows for dynamic feedback control during CMP and results in a sharp and reliable copper-clear endpoint.

The in-situ endpoint system shortens process development cycle, eliminates underpolishing, and reduces overpolishing to increase yield.

Multi-angle reflectometry allows the endpointer to support other CMP applications: shallow trench isolation (STI) and tungsten processes. Single angle reflectometry has been tried for STI, but the reflectance signal feature that signifies endpoint is not unique. Such endpointers depend critically on timing parameters and knowledge of incoming film thickness. Any problem upstream of the CMP process affects endpoint timing accuracy. In positive contrast, the PRECICE system manipulates its angular spectrum reflectometry data to extract a signal feature unique to STI polish endpoint. Thus, it supports a CMP process independent of layer thickness variation from prior deposition steps.

References 1. C.L. Mallory, W. Johnson, and K. Lehman, “Eddy current test method and apparatus,� U.S. Patent No. 5,552,704, September 3, 1996.

2. R.C. McMaster, P. McIntire, and M.L. Mester eds. Nondestructive Testing Handbook: Electromagnetic Testing, 2nd edn., American Society for Nondestructive Testing, 1986.

3. J.D. Jackson. Classical Electrodynamics, 3rd edn., New York: Wiley, 1998.

4. R.M.A Azzam and N.M. Bashara. Ellipsometry and Polarized Light, Amsterdam: North-Holland, 1992.

5. D. H. Ballard and C.M. Brown. Computer Vision, Englewood Cliffs, NJ: Prentice-Hall, 1982.

6. M. Basseville and I.V. Nikoforov. Detection of Abrupt Changes: Theory and Application, Englewood Cliffs, NJ: Prentice-Hall, 1993.

A version of this article was originally published in the 2001 ISSM/IEEE proceedings International Symposium of Semiconductor Manufacturing Conference, October 8-10, 2001, San Jose, California, USA.

KLA-Tencor Trade Show Calendar January 30, 2002

YMS China, Shanghai, China

February 5-7

SEMICON Korea, Seoul, Korea

February 11-15

AVS, Santa Clara, California

March 3

Lithography Users Group Meeting, Santa Clara, California

March 5-6

SPIE/Microlithography, Santa Clara, California

March 26

SEMICON China, Shanghai, China

April 10-12

ACE/APC, Dresden, Germany

April 16-18

SEMICON Europa, Munich, Germany

April 17

YMS Europa, Munich, Germany

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The Dollar Value of Accelerated Shrinks Kevin Monahan, Adil Engineer, Georges Falessi, Matt Hankinson, Sung Jin Lee, Ady Levy, Mike Slessor, KLA-Tencor Corporation

Previously, we have developed a simple microeconomic model that directly links metrology, yield, and profitability. The model has been used to explain the effect of metrology on gross margins in 200 mm and 300 mm factories. The same model can be adapted to evaluate the relative economic impact of accelerated design-rule shrinks in demand-limited markets. Using examples relevant to the high-volume production of memory products, we demonstrate that metrology-driven shrinks are still the most cost-effective way to improve profitability. We also describe the means by which these shrinks can be achieved in high-volume factories.

Introduction

In this work, we use a simplified microeconomic model for the profitability, or rate of profit, generated by the semiconductor manufacturing processi. Let P = −R +

∑ WT (Y y d b i

i i i ij pij

−bij Ci )

ij

where R is the factory overhead rate, W is the number of wafer starts, T is the time interval, Y is the metrology-limited yield entitlement, y is the die yield expressed as a fraction of the entitlement, d is the number of dies per wafer, b is the bin yield expressed as the fraction of good dies in each performance bin, p is the average selling price per die, C is the manufacturing cost per wafer, i is the product index, and j is the bin index. This business model represents the gross rate of profit attributable to a factory.

It does not include variable costs associated with packaging, marketing, or sales of the product. Some of the basic strategies for maximizing gross profit are discussed below.

The first term represents the fixed costs associated with capital investment, operation,

and depreciation of the facility that are independent of capacity utilization. The traditional strategy for minimizing the relative contribution of fixed costs is to reduce manufacturing cycle time and operate near maximum capacity. In a supply-limited environment, this means filling the factory with the highest margin products.

Demand-limited environments may induce loading the factory with low-margin products. Such cases reduce average gross margins and can generate actual losses during times of rapid price erosion. Table 1 shows April 2001 estimates of yield-normalized cost per die, revenue per die, revenue per megabit, and revenue per wafer for several DRAM products. The 16-, 64-, and 128-megabit chips were nearly perfect commodities at one dollar per 16 Mb. Gross margins were negligible for 180 nm design rules. Since April 2001, average selling prices have sunk below the cost of manufacturing2.

Table 1

Cost and Revenue in Dollars

Date: 4/12/01 16Mb SDRAM 64Mb SDRAM 128Mb SDRAM 128Mb DDR 128Mb RDRAM 256 Mb SDRAM

Cost($) 1.00 2.00 4.00 5.00 6.00 8.00

Price($) $/16Mb 1.02 1.02 2.15 1.08 4.35 1.09 7.90 1.98 10.00 2.50 13.95 1.74

$/Wfr 2040 2150 2175 3950 5000 3488

Gross Margins 180 nm 0.02 0.15 0.35 2.90 4.00 5.95

150 nm 0.33 0.76 1.57 4.43 5.83 8.39

Table 1.

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Inspection of the table shows that DRAM profitability can be recovered in at least three ways:

• Increased capacity: 256 Mb memory prices are falling, but they currently sell at a per-bit premium relative to 128 Mb memory.

• Increased density: At constant yield, shrinks improve margins by decreasing the cost per die (e.g., 30 percent for a 180 to 150 nm shrink).

+185

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• Increased performance: 266 MHz double data rate (DDR) memory sells at a per-bit premium compared to 133 MHz (SDR) memory.

Spot Prices per 128 Mb 16 14 12 10 8 6 4 2 0

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+107

+32 +29

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Figure 1. In 2001, DRAM spot prices declined eight-fold in six months.

The ASP advantage for DDR SDRAM and 256 Mb SDRAM declined from 185 and 107 percent to 32 and 29 percent, respectively.

Microeconomics of shrinks

The second term in the profitability equation above is the rate of revenue, adjusted for manufacturing cost per wafer. For the sake of simplicity, we can ignore speed bins (b) and estimate a yield-normalized die cost (c) given by ci ≡

1 Ci S2 Ci ≅ Yi yi di yi d0i D2 Yi

[ ][ ]

Here, S is the shrink ratio (e.g., 150 nm/180 nm), D is the wafer diameter ratio (e.g., 300 mm/200 mm), and d0 is the initial density. Substituting into the profitability equation, the term to the right of the sum becomes the product of salable die output and the variable margin for each product:

T∑ i

P = −R + 1

Wi di Yi yi −(pi −ci)

As shown above, the normalized die cost in the second term falls off sharply with larger wafer size, improved yield, and smaller design rules. For the purposes of this work, a demand-limited market is defined as a nearly constant revenue opportunity for a given product, so that excess production results in a reduction of average selling price as shown in Figure 1.

• The benefit of increased wafer size is lower die cost, offset by excess production-driven price reductions and the cost of 300 mm facilities and equipment.

• The benefit of a metrology-driven shrink is lower die cost, offset by the cost of the metrology, statistical analysis, control applications, and an advanced process control framework.

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The investment required for metrology-driven die-cost reduction is 1-2 orders of magnitude lower than that required for 300 mm solutions, with the notable exception of existing pilot lines. Clearly, existing 200 mm factories must pursue aggressive die-cost reduction or face closure. The most economically defensible strategies will leverage metrology-driven shrinks initially, followed by ramp of 300 mm lines as the market recovers.

Metrology-driven shrinks

The bulk of this paper is dedicated to the systems, tools, software, and methodology required for enabling metrology-driven shrinks. In order to maintain yield, one full generation of design-rule shrink (0.7x) requires a 30 percent reduction in CD and overlay variation, plus a large drop in the levels of macro and micro defects.

For the purpose of this work, we shall focus on factorywide systems that enable shrinks by improving CD control in the lithography and etch areas. In the near future, performance of such systems will not be measured at the component level (e.g., metrology precision).

Instead, performance will be measured at the systems level, with the metric being improvement in CD variation given a specified process capability. Since these specifications must be data-driven, rigorous factorywide stochastic analyses will be required beforehand.

Currently, such stochastic analyses are provided as a service to support factory-wide sample planning and advanced process control (APC).

Key steps in the implementation of a factory-wide gate CD Control System (CD-CS) are outlined below:

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Figure 2. An APC scheme incorporating feedback and feed-for ward of post-development CDs, feedback of etch CDs, and feedback of etch-time to adjust the CD target in the lithography cell.

• Utilize factory-wide, generalized, nested ANOVA to separate systematic and random, plus spatial and temporal, components of variation by site, field, wafer, lot, and cell. Determine the overall process capability and CD control opportunity.

• Utilize factory-wide APC simulation to evaluate model-based, feed-forward and feedback control as a means of reducing temporal CD variation in cell-tocell, lot-to-lot, or wafer-to-wafer data. Determine the specific APC opportunity.

• Implement the factory-wide APC framework, conforming to SEMI E-93 standards (Catalyst). Facilitate control system integration (Figure 2).

• Implement a pre-integrated CD Control System consisting of SEM or spectroscopic CD tools, data and recipe server, data analysis modules, and basic control applications. Optimize tool-specific control applications.

DRAM CD control opportunities

DRAM shrinks are limited by the requirement for tight control over the physical parameters that affect the physics of the device. An approximate expression3 for saturation current in an MOS transistor illustrates this problem: Ids ≅ W • µ • ε •(Vgs - Vth)2 2 L D

( )( )( )

Here, W is the gate width, L is effective gate length, µ is the carrier mobility, D is the thickness of the gate

dielectric, ε is the permittivity of the gate dielectric, Vgs is the gate voltage, and Vth is the threshold voltage at which switching begins to occur. At small L, shortchannel effects reduce Vth non-linearly, so that small variations in L have large effects on current. Matching of L-effective is, therefore, critical to the operation of differential circuits such as the sense amplifiers and comparators used in memory devices. Moreover, the equation above is an approximation; leakage current does not go to zero in the sub-threshold region. At small L, variations in L can have large effects on leakage from the DRAM storage nodes. Due to these and other parametric limitations, the DRAM roadmap for 1 Gb production has fallen off the historical trend line, and further attempts to lower bit-cost are at risk4. As a result, control of L-effective in DRAM is becoming more important as design rules decrease and as performance requirements increase.

Advanced Analytical Methods Gate CD control for DRAM is quite different from that seen in logic factories. Lithography cells are not specifically dedicated to gate layers. For the purpose of controlling overlay, cells are typically dedicated to a series of critical layers on a specific product. These usually include the active, gate, contact, and first-metal layers. Each critical layer is aligned and exposed using the same stage and lens. Therefore, CD control in a high-volume DRAM factory entails controlling cell-tocell variation over a large number of lithographic cells.

In addition, the etch processes used in DRAM manufacture may induce more field-to-field variation across the wafer and more site-to-site variation across each field. Generalized ANOVA is required to identify the Winter 2002

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exposure dose. In the case of etching, adjustments are typically made to etch-time.

ANOVA 3.69 0.42 NEG 8.50

Table 2.

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Feed forward corrections for random error. After resist patterns are developed, “random” CD errors become systematic and may be corrected by adjusting parameters such as etch-time.

•

Create a systematic manufacturing context.

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Develop generic control applications.

sources of correctable systematic variations, as shown in Table 2 above: Without generalized ANOVA, systematic and random errors are confounded (right-hand column). As a result, a semiconductor manufacturer could make the costly and erroneous conclusion that he had achieved entitlement for his process toolset.

After a pattern is etched, CD errors are not correctable; there is no subsequent patterning step. If the CD errors arise from chamber offsets, one could adjust the etch-time of individual chambers.

Ideally, more than 80 percent of a generic APC script should be re-useable anywhere in the factory. Otherwise, unique code will be created for each application.

Advanced Process Control

Factory-Wide Framework

The essence of advanced process control (APC) is the automated correction of systematic process error. The strategy of APC is to de-confound and correct as much systematic error as possible. Several tactics can be employed to support this strategy, as shown in Figure 2.

CD control systems for DRAM require multiple integrations of control applications, metrology tools, and process tools for both lithography and etch cells. The implementation of a standard factory-wide APC framework solves this problem. With a framework, the task of integrating with the factory MES system is performed only once.

•

In the case of lithography, adjustments are typically made to

Feed back corrections for systematic error.

Catalyst APC Framework

MES/ Equipment Manager

Control Executor

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Figure 3. Open factor y-wide framework for advanced process control.

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The multiple data types provided by SCD enable both process and metrology fault detection. Without such information, profile variations that change L-effective could go undetected, compromising performance of the APC system and reducing die yield. The sub-nanometer matching and precision of SCD tools enables APC architectures for controlling critical dimensions below 50nm. Significantly above these dimensions, the contribution of metrology error would be negligible.

In addition to simplifying MES integration, the framework provides middleware for managing the complex interactions among the control executor, control database, control history, control documents, GUI workbench, and application interfaces. The middleware enables rapid extension of APC into overlay, etch, films, and CMP. It can also support integrated metrology and control on process tools. Failure to use a framework can generate recurring costs that persist for multiple product generations and compromise availability (e.g., >0.9999).

CD Process Window Monitors Advanced Metrology Tools

The algorithms used for CD-APC often depend on factors such as stepper focus offsets and illumination settings, which are not explicitly called out in the equations. For example, a generic proportional control algorithm with EWMA filtering (λ) might be written as

The L-effective of DRAM transistors is sensitive to both gate CD and gate profile. To address the need for CD and profile optimization, control systems based on spectroscopic ellipsometry have been developed to supplement the traditional SEM-based metrology.

Spectroscopic CD tools (SCD) can measure CD, sidewall angle, height, and film thickness, simultaneously.

Although measurements are made in 50-micron diffraction gratings located in the scribe lanes, line and space dimensions can be adjusted to mimic the proximity behavior of gate structures in either dense arrays or relatively isolated logic areas. Intra-field targets may be used when the economic benefits are compelling.

Some typical SCD metrology results are shown in Figure 4.

Zn = Zn-1 −

λ [X − Xt] m n-1

where Zn is the updated process adjustment, Zn-1 is the last process measurement, Xt is the process target, and m is the estimate of the local slope of X as a function of Z. In the specific case of CD control, we could have Dosen = Dosen-1 −

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Figure 4. The high precision and multiple data types of SCD enable both advanced process control and CD process window monitor applications (CD-PWM).

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Klarity ProDATA Computed Best Focus (µm)

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• Advanced SCD and SEM systems that address CD and profile metrology requirements for APC

0.60 0.40

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• An automated process window monitor to identify excursions that could compromise APC

0.20 0.00 -0.20 -0.40

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Programmed Exposure Tool Focus Offsets (µm)

Figure 5. PWM tracking of focus offsets on a 248 nm lithography tool. The residual 3σ is 12 nm. PWM is a web-enabled, automated system that can track common process windows and identify matched stepper groups across entire high-volume factories.

The stability of the APC algorithm depends on the estimate of the local slope (m), which in turn depends on the focus offset of the lithography tool. Periodic monitoring of the lithographic focus-exposure window is essential to detect process drift that could compromise the integrity of an APC system, particularly for the tight CD control requirements associated with 0.13 and 0.10 micron design-rules.

In the near future, we predict that factories will not be competitive without APC architectures that are based on factory-wide integration of network-enabled hardware, software, and control methodology. Considering the high return on investment provided by factory-wide APC architectures, semiconductor manufacturers are advised to continue such investments through industry downturns.

This strategy will enhance the performance and extend the life of both current and future process tools, contributing to efficient use of scarce capital resources.

Principal author biography

Dr. Kevin Monahan is a Vice President of Technology and Director of Parametric Solutions in the Customer Group of KLA-Tencor Corporation. His professional interests include patterning and parametric process control architectures for high-volume manufacturing.

References

Conclusions

We have shown that, in most cases, metrology-driven shrinks are the most economic and effective means for reducing die-cost in demand-limited DRAM markets.

We have also identified five technologies that can be combined to achieve shrink-enabling levels of CD control for sub-0.18 micron product generations: • Generalized ANOVA methods for identification of correctable, systematic CD error • Advanced control applications for automated correction of CD error in photo and etch cells • A factory-wide open framework to support integration and management of APC applications

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1. K. Monahan, G. Falessi, and A. Chatterjee, “Accelerated yield learning in aggressive lithography”, Proc. SPIE 3998, p. 492 (2000), Invited Paper.

2. Source: www.dramexchange.com 3. C. Meade and L. Conway. Introduction to VLSI Systems.

Menlo Park: Addison-Wesley, 1980, pp 1-5.

4. K. Itoh. VLSI Memory Chip Design. New York: SpringerVerlag, 2001, pp. 1-99.

5. R. C. Elliott, R. K. Nurani, S.-J. Lee, L. Ortiz, M. Preil, J. G. Shanthikumar, T. Riley, and G. Goodwin, “Sampling plan optimization for detection of lithography and etch CD process excursions”, Proc. SPIE 3998, pp. 527 (2000) .

A version of this article was originally published in the 2001 ISSM/IEEE proceedings International Symposium of Semiconductor Manufacturing Conference, October 8-10, 2001, San Jose, California, USA.

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Got a Litho Question?

Ask the Experts Q

The Rayleigh equation says depth of focus decreases with shorter wavelengths.

I’ve also heard the opposite, that shorter wavelengths give more depth of focus.

Which is correct?

A

Both answers are correct, depending on the details of the specific question. The Rayleigh equation says depth of focus (DOF) is directly proportional to wavelength. This equation, however, is derived for a very specific case: when the feature being printed is at the resolution limit of the imaging tool. Rayleigh’s resolution equation (the other Rayleigh equation) says the resolution limit is also directly proportional to wavelength. Thus, when the wavelength is reduced, the Rayleigh DOF equation says the DOF of the smaller feature is less. This is not an astounding conclusion – small features have less DOF. Suppose the question were asked in a different way: for a given feature to be printed (say, 130 nm lines and spaces), how does wavelength affect DOF, all other things being equal? Is there a difference in DOF using 193 nm exposure tools versus 248 nm?

The Rayleigh DOF equation by itself cannot answer this question. In fact, the lower wavelength will always give more depth of focus for a given feature size.

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Chris A. Mack

Q

I read a paper that talked about “forbidden pitches”. What is a forbidden pitch and why can’t I use them?

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The term “forbidden pitch” is frequently used when imaging with off-axis illumination, such as quadrupole or annular illumination. These illuminations bring light to the mask at an oblique angle.

Diffraction of light from the patterns on the mask occurs at angles that depend on the pitch of the patterns. Off-axis illumination is optimized so that the angle of illumination striking the mask matches the angle of diffraction for a given pitch to give optimum performance (usually be spacing the diffraction orders evenly about the center of the stepper lens). This angle of illumination is only optimum at this one pitch. When the off-axis illumination is optimized for one pitch (usually the smallest pitch on the mask), there will always be some other pitch where the angle of the illumination works with the angle of diffraction to produce a very bad distribution of diffraction orders in the lens (one diffraction order in the middle of the lens and the others at the outer edges of the lens), resulting in poor depth of focus for that pitch. We call this pitch “forbidden” because of its poor lithographic response, and because we hope the chip designers will listen to us and avoid putting that pitch on the mask.

Do you have a lithography question?

Just e-mail lithocolumn@kla-tencor.com and have your questions answered by Chris Mack or another of our experts.

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Product News TeraStar SLF77

The TeraStar SLF77, the latest version of KLA-Tencor’s series of advanced reticle inspection systems, provides high-performance, high-sensitivity die-to-database inspection that meets critical layer requirements for 130 nm production and 100 nm research and development. Database rendering capabilities include advanced database modeling, high-precision algorithms, and high-speed image-computing hardware. Reticle defect detection features include advanced Tera algorithms that enable high-sensitivity inspection and low false-defect counts. Advanced image-computing capabilities allow inspection of small linewidths and optical proximity correction (OPC) features, including sub-resolution assist features.

TeraPro HP high productivity mode

The TeraPro HP High Productivity Mode, a feature of the TeraStar SLF77 reticle inspection system, provides pattern, contamination and must-be-black (MBB) border inspections all in one inspection, saving time and increasing productivity. This multi-faceted inspection using MBB inspects for yieldkilling pinhole defects in the opaquing border, eliminating the need for an extra inspection. With TeraPro HP, multiple algorithms now run concurrently in multiple areas. Concurrent inspection modes—STARlight and die-to-die or STARlight and die-to-database—save time by reducing the number of inspection passes performed in the reticle flow.

Viper 2430

The Viper 2430 is an automated macro-defect inspection system for inspecting 300 mm wafers using a multi-channel, multi-algorithm setup to capture yield-limiting defects at design rules of 0.13 µm and below.

Built upon the extensive knowledge base developed in the field with customers who use the 2401 (the Viper 2430’s predecessor), this system is ideal for process modules such as litho, CMP, and etch, or in passivation and final inspection. It also captures defects in advanced processes and materials such as copper dual damascene, low-κ dielectrics, and silicon-oninsulator (SOI). The Viper 2430 plays an important role in a fab’s overall strategy to improve yield because it also monitors process excursions. It complies with all I300I factory-automation standards for immediate and seamless integration into the 300 mm production environment. For rapid dispositioning of wafer lots and faster root-cause analysis, the Viper 2430 features inline binning and flexible, on-board review capability that allows users to view individual defect images, wafer maps, wafer images, and galleries of wafer maps.

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Surfscan SP1 backside inspection module

Available as an option on both the Surfscan SP1TBI and Surfscan SP1DLS, the backside inspection module (BSIM) provides full edge handling and enables fabs to perform automatic, non-destructive inspection of both sides of a wafer, including the backside of patterned production wafers. Manufacturers can now control backside contamination and damage. They can also monitor the effectiveness of backside cleans between process modules, and ultimately reduce yield loss due to particle-induced hot spots and other defects that result from backside contamination. The module also supports 200 mm and 300 mm wafer manufacturing and advanced processes such as copper, low-κ dielectrics, and design rules of 0.13 µm and smaller.

µLoop™

µLoop (MicroLoop) is the industry’s first inline, non-contact electrical defect monitoring solution designed to help chipmakers speed time to market and time to profit. The µLoop solution reduces the length of each electrical yield-learning cycle within the fab from as much as eight weeks down to as little as a few days. This enables chip manufacturers to substantially accelerate the production ramp of new IC technologies while, at the same time, increasing their baseline yields. µLoop’s speed and accuracy in isolating the location of electrical defects is made possible by utilizing a combination of seamlessly integrated capabilities, including: (a) patented test structures, which replicate customer-specific design rules and products; (b) latest-generation eS20XP scanning e-beam inspection and µLoop Controller systems, which use a voltage-contrast technique to identify and characterize electrical defects; (c) advanced electrical defect and yield-analysis algorithms, which filter out non-yield relevant defects; and (d) industryleading yield-acceleration expertise.

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Attend KLA-Tencor’s 3rd Annual Lithography Users Forum Sunday, March 3rd, 2002 Techmart, Santa Clara, CA w w w. k l a - t e n c o r. c o m / s p i e

Register and submit poster papers online.

R S V P by F r i d ay, F e b r u a r y 2 2 n d , 2 0 0 2 .

K Accelerating Yield