Editorial S
E
C
T
I
O
N
S
Copper—The Technology Marathon Enabler Like moths to a flame, humankind is irresistibly drawn toward technology. Its pull is so strong, yet so innate, that we often don’t even question why we push so hard at testing its limits. Take Moore’s Law, for example. Why has the semiconductor industry continued to keep pace with it, as if engaged in a marathon? Certainly, no one questions the benefits of device scaling. Smaller chip designs enable more—and more complex—ICs per wafer, which leads to increased profits for the device manufacturer. If we take the 30,000-foot view, more complex and better-performing devices lead to new technology innovations that literally reshape the world we live in—from exploring the furthest reaches of our solar system or unlocking the secrets of the human genome, to redefining how we communicate with our friends and family, or even view our role in the universe. We test the limits of technology because the pros far outweigh the cons. Technology is THE driving factor in improving our lives. Faster and lower power-consuming chips will one day, very soon, help replace the gas-guzzling automobile with the environmentally friendly electric car. Supercomputers that were developed for military and defense purposes are used today to develop advanced drugs that will help impede the progress of ravaging diseases. In the not-too-distant future, microfluid biochips will be used for clinical diagnoses, and the list goes on. Without continued technology investments, however, many such futuristic advances may remain embryonic ideas. Let’s look at how this perspective applies to the technology trends we’re seeing today in advanced semi-
4
Winter 2002
Yield Management Solutions
conductor fabrication. If you look at chip manufacturing, you can essentially break it down into two segments: front-end-of-line, or FEOL (the transistor), and backend-of-line, or BEOL (the interconnect). Within these, two key technology inflections are occurring. In the front end, Intel’s newly announced depleted substrate transistors (DSTs) or silicon-on-insulator (SOI) materials are being introduced that promise to enable faster, lower-power switching. In the back end, however, no amount of innovation can improve device performance – it can only minimize any losses that you might have. All the improvement you’ve achieved in the front end can be lost in the back end, and what’s the point of having a faster-switching transistor that consumes less power if you have a poorly performing interconnect? That’s why copper and low-κ materials are so important to semiconductor innovation: because they help to minimize your losses in the back end so you can reap the performance gains of the front end. While copper has revolutionized chip manufacturing, it has also placed incredible challenges and pitfalls in front of us. For example, we’re hearing people talk about void-free copper fill and deposition, but what do they mean? The reality is that there is no such thing as “void-free”; we need to know what’s statistically acceptable to achieve this designation. It is not enough just to make decisions about what accelerants and suppressants to use and hope to achieve a “void-free” copper fill. We need to ask ourselves many other important questions as well. What aspect ratios are involved, and at what design rules? What are the defect density requirements? Can we have one bad via