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Q&A Talking Yield with Dan Hutcheson Dan is president and CEO of VLSI Research Inc. He is a recognized authority and well-known visionary for the semiconductor industry, whose career experience spans more than twenty years.

To help assess the impact that KLATencor’s new µLoop technology will have on the semiconductor industry, Yield Management Solutions sat down for a one-on-one discussion with one of the industry’s most well-known and respected independent analysts, G. Dan Hutcheson, CEO of VLSI Research Inc. The following Q&A elucidates some of the key issues chipmakers face with respect to yield management and the yield learning cycle, which µLoop was created to address.

YMS: Dan, let’s start at the beginning. What are some of the market and competitive pressures driving the acceleration of key technology transitions in the industry?

DH: One of the chief issues facing chip manufacturers today is the fact that cycle times are becoming extremely short. At the same time, the cost of bringing new technologies to market, like copper interconnect and 300 mm wafers, has become much greater than ever before.

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Furthermore, to fully leverage your investment, you have to get product to market faster – today, if you miss the market by six months, you can easily lose all the product’s profitability.

YMS: What impact does the convergence of copper interconnect, 300-mm, and subwavelength lithography have on yield?

DH: The impact of all these new technologies on yield has truly been to change the whole ball game. Not only are you no longer looking for surface defects, since many of them are now sub-surface, but the number of true killer defects is incredibly small today. While we used to look at defect densities of five to 10 per square inch, per layer, we are now dealing with small fractions. The fact is, in contrast to 10 years ago, the industry is not chasing particles but, rather, actual process problems. It’s somewhat analogous to looking for a needle in a haystack, within another haystack.

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YMS:

In today’s fab, then, how important is faster yield learning, or time to yield?

DH: It’s very important, simply because fabs are so expensive now.

Chipmakers are spending billions of dollars for these new 300 mm fabs, the time to market is critical, technology must be brought online quickly, designs have to come to market fast – everything has to happen in a much tighter time frame. A good illustration of this is the loss experienced by one of our clients, a chip producer. A yield problem in one of their fabs caused a six-month delay, costing them the entire profit potential for one of their products.

Any senior manager at a chip manufacturer today should understand the importance of yield because if you’re not focused on yield learning, you’re not competitive. At the end of the day, that’s what determines where your costs lie. There is no such thing as constant yield anymore – it’s all about how fast you can get there and how you go about improving it. We

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often talk about cost of ownership, cost of producing the wafer, but if you yield nothing, you have no revenues to offset that cost. The fact is, profits come from the yield part of the equation.

YMS: In your opinion, how does KLA-Tencor’s new µLoop technology stack up against today’s existing technologies aimed at yield learning?

DH: Clearly, µLoop technology is the next step in yield improvement and yield learning because, for the first time, we’re breaking away from visual inspection in the fab and can now do electrical testing in the fab.

The technology brings all of the advantages that you get with electrical test, of identifying true killer defects, inside the fab, so you don’t have to wait until the wafers are out to perform electrical test. That’s not only a revolution in yield management and yield learning – it’s a revolution in getting yield cycle times down.

YMS: Why is that so significant?

DH: If you can’t do that, your fab is going to have a yield learning disorder. Currently, it takes weeks or months to get wafers out and to electrical testing. Ten to 20 years ago, no one would have ever have accepted the notion of test as a means of improving yield in the fab. Yet now, senior executives in chip companies, all the way up to the CEO level, are talking about how they’re using

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electrical test as a way to drive fab yields because electrical test is the only way to sort killer defects from defects that don’t affect your fab. You don’t want to spend a lot of money and waste a lot of engineering effort to find defects in the wafer that don’t cause a problem, that don’t kill the yield – that really don’t matter, either to you or to your customer.

YMS: What’s the disadvantage of waiting until electrical test to identify yield problems?

DH: It’s simple: time is money in a fab. For example, suppose you’re a chipmaker running wafers at the rate of 7,500 per week, and you wait six weeks for those wafers. By the time a yield loss is detected, 45,000 wafers will have already been processed. If there is a yield problem, you must bring the fix into the loop, then wait another six weeks to see if the problem is solved. Now, you’re up to almost a hundred thousand wafers processed – if you lost, say, $10 per wafer, you’ve lost over $1 million. We’re talking about potential losses of hundreds of millions of dollars if you extrapolate that out across all of the products and product lines.

So, if you can shrink these long cycle times that cost you hundreds of millions of dollars by using µLoop technology, you can save those costs and expenses by simply bringing those revenue streams back in. Or, you can transfer

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the lower cost to your customers directly, allowing them to satisfy their customers faster. Either way, you win in the marketplace because it makes you more competitive, and makes your customers more competitive.

YMS:

How would you rank µLoop against the various yield-management advances you’ve seen over the last couple of decades, based on its potential?

DH: The last big thing in yield management was yield management.

Chipmakers went from looking at wafers with microscopes to automating defect inspection and classification. µLoop is really the next big step because it’s a new paradigm for improving learning and yield in the fab. It’s really an interesting new way of doing things. Instead of looking at an optical image, which has been done before, you’re looking at a SEM-based voltage contrast image.

The difference is that when you look at it electrically, it tells you whether a product is good or bad, or if a defect is really a killer. That has always been the promise of e-beam probing in this space, but the problem with e-beam is that it is classically too slow. That’s the big challenge that has to be overcome – and that’s really the promise of µLoop. It’s more significant than a lot of the other things we have seen in the past because at the end of day, yield is everything.

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