Winter02 voids pits copper by KLA Corporation

Cu/low S

κ C

Voids, Pits, and Copper Judy B Shaw, Richard L. Guldi, Jeffrey Ritchison, Texas Instruments Incorporated Steve Oestreich, Kara Davis, Robert Fiordalice, KLA-Tencor Corporation

As circuit features have scaled below 0.25 micron, the resistivity of aluminum has become an obstacle to integration. With forty percent higher conductivity than aluminum – and far more resistance to electromigration—copper holds the key to dramatic improvements in circuit density, speed and reliability. Integrating copper into the IC manufacturing process, however, is extremely challenging. Copper can diffuse into silicon and dielectrics, causing shorts or leakage, which can impact device performance and yield.

The introduction of copper dual damascene processing into integrated circuits has brought about a host of new defectivity issues, especially those related to voiding and pitting. These defects must be understood and eliminated to achieve competitive manufacturing yields and assure device reliability.

Surface pit

Void characterization in copper processes

As part of a joint development copper program to develop 100 nm logic processes, KLA-Tencor and Texas Instruments worked together to develop new defect inspection strategies. The most important yield limiting defect types with copper are voids. Almost naturally, copper voids seemed to group into two distinct categories: optically detectable voids that are on the surface of the copper layer, and sub-surface voids, which are detectable using e-beam voltage contrast inspection (Figure 1).

Sub-surface void

Figure 1. The most critical copper voids can be grouped into two categories—optically detectable pits/voids on the surface of the copper, and sub-surface voids not obser vable from the surface, but detectable using e-beam voltage contrast inspection.

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Void formation may stem from electroplating, annealing, or polishing steps. It is important to identify appropriate inspection tools to characterize the process steps responsible for void generation in order to quickly determine root causes and optimize process capability, process control, and tool maintenance.

Post-ECD

Long Pit

Void ECD Void

ECD Void

Post-CMP

70% Post-CMP Pareto

An advanced 0.13-micron, copper dual damascene process was used at Texas Instruments’ Kilby Development Center (KFAB) to generate the samples in this paper. The gallery of defects generated by this type of process (Figure 2), shows some embedded and surface particles, but primarily voids or pits dominating the defect Pareto.

60% 50% 40% 30% 20% 10%

ECD Void

Other

Missing Material

Scratch

Particle

Void

Figure 3. Darkfield inspection implemented post-ECD and post-CMP,

At the time that Texas Instruments and KLA-Tencor undertook the studies of copper defects, the process of record had brightfield inspection as part of the process loop, and this was done after copper CMP. Although brightfield inspection revealed many defects—some yield limiting and some less important—the sheer numbers of defects and the presence of patterning and underlying defects made surface void source partitioning difficult.

Optical Images

Long Pit

Micropartioning strategies determine root cause

using KLA-Tencor’s AIT III, was utilized to partition the source of patterning and underlying defects.

To partition the source of these defects, a darkfield inspection was carried out using a KLA-Tencor AIT III, and the first inspection was performed after CMP. Immediately, a high defect count and an obvious swirl pattern of voids were noted. The defect Pareto revealed the highest two categories to be voids and long pits, which are essentially another form of voids. Together, these two categories Copper Defect Gallery accounted for well over 70 percent of SEM the Pareto. Based on knowledge of the Images process and the process tool, the void formation appeared to show a CMP sigProcess Step nature (Figure 3). The first step in moving towards understanding the voids ILD Dep (5 Step) was inspection after electrochemical Seam From Topography ILD CMP (Optional) deposition (ECD). Post ECD inspection showed the swirl pattern to be subtler; Via Photo voids and pits were also present, albeit Defective Via Etch smaller and shallower than after CMP. Via Embedded The next step was to overlay ECD and Particle Trench Photo CMP defects on the wafer map using Trench Etch analysis software. Defect overlay con(BARC, Trench, Etch Stop) BARC firmed that the post-CMP voids in the Under-Etch swirl pattern had their root cause in the Barrier/Cu Seed Dep Void/Rip Out ECD, and were enlarged and revealed by Cu EP polishing and post-CMP clean (Figure 4). Cu Anneal Cu CMP

Void Void

Figure 2. This figure shows a galler y of typical defects generated during copper dual damascene processing. Voids or pits dominate the defect Pareto, although a few other surface-type defects are present at a lower level.

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In this and other examples we have seen that darkfield inspection is quite successful for rapid and focused engineering analysis in the copper loops. This is because oblique illumination minimizes the detection of previous Yield Management Solutions

Common defects show "swirl" pattern

Same Defect

Random Mode Logic

Array Mode SRAM

Physical (non V.C.)

Post-ECD Missing Count

Array Mode DD Test CHIP

Adder Count 1448 306/2978

1142 3288

1644

3288

Physical (non V.C.)

Total True Defects: 306 Displayed Total Defects: 2431 Displayed True Defects: 306 6052M1PL JDP_M1CMP_SW

Stepchart

Post-CMP

Figure 5. Sub-surface voids have many potential causes and are electrical in nature. These sub-surface voids were detected using the eS20XP’s voltage contrast methodology.

Figure 4. Defect overlay confirmed that the post-CMP voids in the swirl pattern had their root cause in ECD and were simply being enlarged by polishing and post-clean. Darkfield inspection is quite successful for rapid engineering analysis in the copper loops, because oblique illumination minimizes the detection of previous layer issues and other “noise,” enabling effective focus on current layer problems.

layer issues, as well as other inspection “noise,” so that we effectively focus just on the current layer. Eliminating sub-surface copper voids

The second type of copper void is very different. It is a sub-surface void and, generally, these types of defects are related to materials or process integration issues. It is absolutely essential, during the technology development phase, to have a tool that finds these sub-surface voids, enabling screening experiments and quick elimination of these voids. This is critical to ramping a copper damascene process, because voids must be eliminated before the process flow is set, and before it is qualified. If the metal lines contain copper voids, they stand the risk of becoming opens, resulting in device failure. In order to capture these voids at this very important juncture, KFAB used KLA-Tencor’s eS20XP e-beam inspection tool (Figure 5).

Random or array mode: when it works There are a number of techniques for implementing e-beam inspection to inspect sub-surface voids. The first option is random mode inspection of the logic areas on the product chip. This inspection is very useful to perform, as it provides considerable information. However, 10

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due to the random nature of the pattern, it is quite difficult to perform an effective analysis of root cause. It would be quite time-consuming for a failure analyst to take this information and determine the defect that caused the electrical opens. The next option in implementing e-beam inspection is to utilize the array mode to inspect the memory areas of an SRAM chip. Array mode analysis is easier than random mode, because the defects of interest readily stand out in a voltage contrast SEM, but failure analysis is still non-trivial because of slight variation in SRAM design among different products or different technology generation, requiring considerable skill and time to perform the failure analysis. The most useful analytical technique is array mode inspection of defect density test die, which affords straightforward failure analysis, since the analyst can e-beam scan the defective chain along its length to precisely locate the electrical failures and then port those locations to a focused ion beam (FIB) microscope for cross-sectioning (Figure 6). The work shown in the remainder of this paper is focused on the array mode inspection of a defect test chip. The test chip is grounded using a contact mask as the first pattern. This method makes it very easy to see where the defective via is. In the normal case, when the e-beam inspector scans the wafer, the grounded structure will appear bright due to the secondary electron emission. However, if a via void is present, the secondary electrons are effectively extinguished and that portion of the chain will appear dark. The inspection system’s extraction field attracts the secondary electrons.

Blocked etch, previous layer

VC Defects Electrical Opens

Metal 3

Metal 2

Under-etched Via Figure 8. This figure shows types of electrical disconnections. The image on the left shows a problem arising from a stopped via etch or under etch; the image on the right shows a blocked trench etch at the Figure 6. Utilizing a defect density test chip in conjunction with the

previous metal level.

eS20XP’s voltage contrast methodology enables easy detection of defective vias.

Experiment 1 – Evaluating via integrity at the wafer level

They are replaced from ground in the grounded structure and the floating structure charges positively. Secondary electrons from the floating structure have a lower net energy and are attracted to the positive surface charge, limiting the number that make it to the detector. Hence, these defects look dark (Figure 7). In the case of Figure 8, a surface SEM detected nothing physically wrong, but voltage contrast imaging suggested that there was an electrical open below the surface. That is exactly what the FIB cross-section revealed—a void in the previous layer metal, the via landing pad.

Experiment 1 was conducted to evaluate via integrity at the wafer level using the eS20XP under various interconnect process conditions. Three process variables were screened: the ECD seed conditioning, the pre-ECD rinse conditioning, and the post-ECD anneal. The experiment was designed for 0.13 µm dual damascene copper/low-κ via structures. Wafers were inspected using the eS20XP. The outcome clearly showed that the same result could be achieved with the eS20XP inspection that otherwise would have only been detected with electrical via resistance testing at final test (Figure 9).

Screening Experiments After the practicality of e-beam inspection was established, this technique was applied to two experimental problems. The first experiment investigated the effect of ECD seed conditions, pre-ECD rinse, and post-plating anneal on voids, while the second examined the effect of seed thickness and post-plating anneal.

The experimental data show that the post-ECD anneal conditions drove the experimental results. Anneal B had several times as many defects as anneal A. The other two process variables—the ECD seed condition and the pre-ECD rinse condition—had negligible effect on the defect counts. Another valuable piece of

eS20XP Defect Scan Summary Anneal "B"

Wafer Map

Anneal "A"

Metal 1

Total Defect Count

Metal 2

Void in Landing Pad

Figure 9. This summarizes the results of the first experiment, which Figure 7. In this example, top surface inspection showed nothing

compared the effect of ECD pre-conditioning anneal, pre-ECD rinse,

physically wrong; however voltage contrast e-beam inspection and

and post-ECD anneal on copper voids. The vast majority of defects

subsequent FIB revealed the presence of a high-resistance, sub-surface

found by the eS20XP were voltage defects as opposed to surface or

connection due to a void in the previous layer metal at the landing pad.

particle defects.

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100% Anneal Condition A 70%

Anneal B

50% Anneal Condition B 30%

0 0

(Ω/Via)

Anneal B

Figure 10. Electrical probing confirmed the e-beam inspection results, with anneal B giving a high resistance fail in the via chain cumulative percent fail, compared to the relatively healthy via fail distribution for anneal A.

information was also found in this data—a strong acrosswafer radial dependency of the defect counts. The vast majority of the defects were at the edge of the wafer. The next step with these same wafers was to probe the via chains; these results were consistent with voltage contrast data. The via chain cumulative percentage plot showed fall-out under anneal B conditions. Anneal A had a relatively healthy, robust distribution of via resistance, whereas anneal B’s distribution was poor, with many outliers. This probing revealed the same sort of voids as seen before. Anneal B had either voided via plugs or voids in the underlay landing pad (Figure 10). Experiment 2 – Evaluating via integrity under thermal stress

Experiment 2 was conducted to evaluate via integrity under thermal stress using the eS20XP. The experiment was again set up on 0.13 µm dual damascene copper/ low-κ via structures. The wafers were exposed to four thermal cycles post CMP. An eS20XP inspection was performed after each of these cycles. In this screening experiment there was only one process variable—the ECD Cu seed thickness (Figure 11). eS20XP Via Void Evaluation

Defect Count

Thickness wfr 1 A wfr 3 A wfr 2 B wfr 4 B wfr 5 B wfr 6 B

Time

Figure 11. The two wafers having thickness A maintained a low via fail rate throughout the entire annealing sequence.

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A number of results were found in this experiment. First, there was a strong wafer-to-wafer effect. The same spatial effect of center to edge found in Experiment 1 was seen again. Seed thickness A produced lower defect counts. The defective vias were again confirmed to have subsurface voids. Seed Thickness A wafers have the most consistent counts as well as the lowest defect counts after four anneals. Seed thickness B wafers had much wafer-to-wafer variability, generally with higher counts. One seed thickness B wafer, wafer 5, had very high counts. Counts increased greatly with the number of anneal cycles. Wafer 5 was then taken to the FIB tool (Figure 12) and, for the third time, it was demonstrated that voids were induced by anneals, both in the plug as well as in the underlying pad.

Moderate Void

Voltage Contrast Example

Moderate Void

Extensive Void

Figure 12. This figure shows FIB cross-sections of three different voltage contrast voids after the fourth anneal. It was found that intermediate temperature annealing leads to moderate void formation at the bottom of vias, resulting in voids that are not as fully developed as those arising from higher temperature anneal. However, a few extensive void developments were also seen, as shown in the lower right corner of this figure.

Conclusion

Both optical and e-beam inspection methodologies have proven useful for copper void detection. AIT III inspection, with its oblique angle of incidence, is very effective in detecting surface voids, helping to characterize the ECD process, which is responsible for generating most of the voids. Voltage contrast inspection of defect density test chips using eS20XP has a unique and complementary application: to detect subsurface voids. The combination of optical and e-beam inspection tools enables faster detection and analysis of copper voids, leading to accelerated learning cycles.

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