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Yielding in the Era of Innovation “Learning and innovation go hand in hand. The arrogance of success is to think that what you did yesterday will be sufficient for tomorrow.” —
William Pollard
The semiconductor industry has always been endlessly innovative. As chipmakers strive to stay on Moore’s Law, the level of innovation today is unprecedented. Scaling alone is no longer enough to stay on the industry’s historic growth trajectory. Novel transistor architectures, exotic new materials, new lithography techniques—all these and more are necessary to achieve desired device performance. Implementing these innovations poses significant technological and economic challenges for chipmakers. Like feverish jugglers, chipmakers today simultaneously grapple with successfully advancing to the next node, maximizing the use of their existing capital, controlling their manufacturing costs, and speeding their fab ROI. Bringing these new innovations into production quickly and cost-effectively requires a keen aware-
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Winter 2005
Yield Management Solutions
ness of the manufacturing process at a moment’s notice. More sampling and line monitoring, as well as more die-level process data, for example, are required to provide the quantitative AND qualitative information needed to identify these new yield loss mechanisms, keep a tight reign on process variation, and speed yield learning. These challenges are driving many new innovations in process control, several of which are covered in this latest issue of Yield Management Solutions. “Thin is in”, reviews recent advancements in spectroscopic ellipsometry, as well as newer techniques to enable chipmakers to meet the thin film process control challenges of 65-nm and beyond. “Progressiveness kills quality” tackles reticle quality degradation, a growing problem in wafer fabs exacerbated by 193-nm DUV lithography. “Loop before you yield” examines the application of electrical line monitoring to accelerate FEOL process development for 90 nm. And “The limiting factor” deconstructs pattern limited yield—one of the greatest challenges awaiting chipmakers at the 65-nm node and beyond. These and other articles