Winter05 loop before yield by KLA Corporation

FEOL T

Loop Before You Yield Accelerating Killer Defect Detection in the FEOL Akihiro Shimada, Yasuo Matsumiya, Atsuo Fushida, Atsuo Shimizu, Fujitsu Limited

This article presents the application of KLA-Tencor’s µLoop inline electrical defect monitoring method for the front-end-ofline (FEOL) process of a 90-nm node logic device. Using this method, killer defects in the FEOL process were as easily detected as in the back-end-of-line (BEOL) process. In addition, the defect density value (D0) was obtained in less than one-third of the time than with the conventional electrical-testing method. This demonstrates that the µLoop method in the FEOL is very powerful and useful for detecting killer defects and for inline monitoring of the FEOL process.

Introduction

Killer defect detection has become a critical component of yield improvement and yield monitoring. Several kinds of inspection tools—including brightfield, darkfield, and electron beam (e-beam)—are used to detect them. However, non-killer defects detected by brightfield and darkfield inspection tools hamper detection of killer defects. E-beam inspection enables fabs to find electrical defects that are, in fact, killer defects1, 2, but the throughput is much slower than with other inspection methods. KLA-Tencor’s proprietary µLoop method is a promising solution to detect only killer defects and improve e-beam inspection throughput. Several companies have implemented this method in the BEOL process and have achieved successful results 3, 4, 5. However, the µLoop method has not been applied in the FEOL, since the structure and target defects are more complex than in the BEOL. If the µLoop method is established in the FEOL process, it will become a powerful tool for yield improvement and yield monitoring at this stage.

sists of two kinds of lines: the single end grounded line and the floated line. We call this the metal open/short structure. The killer defect detection procedure is as follows: (1) Electrical defects (both open and short) are detected in the assessment (Assess) scan using voltage contrast with the e-beam inspection tool; (2) In the identification (ID) scan, only the area where the electrical defects were detected is scanned to find killer defects; and; (3) Detected defects will be reviewed and the Short Defect

(a) Defect Assessment

(b) Defect Identification (c) Defect Review

GND

Overview of µLoop method

Figure 1 shows the key principle of the µLoop method. The pictured structure con-

Open Defect

Figure 1. Principle of µLoop method.

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P Active

Poly

N ++

N + Active

see that electrical defects can be detected in all structures.

Ground Bus Very Large Capacitor Very Large Capacitor

Grounded Active

(a)

Quasi-Floated Active

Quasi-Grounded Poly

Floated Poly

(b)

Quasi-Grounded Poly

Floated Poly

(c)

Figure 2. The basic structures of (a) active open/short, (b) poly open/short, and (c) gate leakage.

killer defect image can be obtained to determine root cause.

Structure in µLoop method for gate-SD short Shorting between gate poly and the active region (source and drain) is an issue of concern in transistors. For example, the overgrowth of cobalt silicide (CoSi) might cause the short bridge between the gate and active regions. Or, the contact to the active region might break the side-wall of the transistor and create a breakdown between gate and contact, which causes the path between the gate and active regions to short. To detect these

Active Short

Active Open

µLoop structures for the FEOL process We applied the µLoop method for the FEOL process in a revolutionary manner. In the FEOL, e-beam inspection is done after salicidation. Figure 2 shows the example of the basic test structures of the method. Figure 2a shows an active open/short structure. We made the line of N+ an active region on the P-silicon (Si) substrate. In the inspection of these structures, we set up the e-beam condition to charge silicide positively. The line itself is similar to the metal floating line because the P-N junction prevents the electron from flowing from the substrate (we call it quasi-floating active line). The line connected to the P+ active region forms the grounded line. Figure 2b shows a poly open/short structure. Due to the design limitation, poly wire/gate can’t be directly connected to the P+ substrate. So we created a ground bus (reservoir) instead of a ground connection. The reservoir is a big capacitor between the poly-gate electrode and the P-Si substrate, which makes a poly line behave as if it were connected to the ground. We call this the quasi-grounded poly. These two structures can be treated like the metal open/short structure. In addition to these two structures, we challenged the detection of the gate leakage failure. Figure 2c shows the gate leakage structure. If the gate oxide breakdown occurs, then the floating gate poly will be connected to the P-Si substrate, becoming brighter during e-beam inspection. Figure 3 shows examples of patch images in e-beam inspection. Arrows show the positions of voltage contrast defects. We can 34

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(a) Poly Short

Poly Open

(b) Gate Leakage

(c) Figure 3. Example of patch image in e-beam inspection. (a) Active open/short. (b) Poly open/short. (c) Gate leakage structure. Arrows show the electrical defect in e-beam inspection.

Metal Poly N + Active P Active

Contact

Structure in ÂľLoop method for bulk contact As we described previously, the P-N junction creates a quasi-floating active region, which enables us to develop the via chain between the active region and metal 1. In the same way we can make the via chain between poly and metal 1. Figure 6 illustrates these two types of via-chain structures. These structures can be treated in the same way as conventional metal via-chain structures. Figure 7 illustrates patch images of the open defects of these structures.

N + Implant

Metal Poly N + Active

Isolated Metal 1 Pattern

P Active

Contact

Figure 4. The basic structures of gate-SD short module.

defects, we developed the structure shown in Figure 4. The isolated metal 1 patterns on the N+ active region are usually dark because they are connected to the quasi-floating active region with P-N junction. The electrical potential of poly is grounded, since poly is connected to metal 1 with grounded potential. If a short occurs between the gate and active regions, the potential of the isolated metal 1 pattern will be grounded and become brighter. Figure 5 illustrates the patch image of the short defect of this structure.

N + Implant

Figure 6. The basic structures of (a) contact to active and (b) contact to poly module.

(a)

(b)

Figure 7. Example of patch image of via-chain modules in e-beam inspection: (a) contact to active and (b) contact to poly module.

Comparison with e-test

Figure 5. Example of patch image of gate-SD short module in e-beam inspection.

Defect counts in the Assess scan can be directly converted to D0 value. Of course, the D0 value can also be estimated from the yield of circuit TEG, but this requires a very long time from lot input to electrical test (e-test) and FBM test. In addition, to enable physical failure analysis, some layers should be removed, Winter 2005

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E-Test

µLoop Method

Wafer Process Measurement PFA

(a)

(b)

Figure 8. Time to root cause of killer defects in the FEOL. Figure 10. Example of short killer defect in poly open/short module.

which is a cumbersome task. Using the µLoop method, we can obtain the D0 value in one-tenth to one-third of the time that the conventional e-test method would require. Furthermore, the µLoop method can steer us to the exact killer defects directly and easily. This quick D0 calculation enables us to accelerate process improvement. For example, by comparing D0 between different process conditions, we can determine which condition will be higher yielding. Figure 8 shows the difference of the time from lot input to physical failure analysis (PFA) between the two methods.

(a) Patch image in e-beam inspection. (b) Review scanning electron microscope (SEM) image.

Figure 9b. Navigating the review image immediately tells us that most of these short defects were due to scratches, and that these scratches caused the deformation of poly pattern (Figure 10). This means that many non-killer defects prevented us from identifying killer defects during darkfield inspection. The µLoop method, on the other hand, detected only killer defects. We are currently developing new equipment to qualify the method that reflects the killer defect rate from µLoop.

Application of µLoop method

Case 1: Scratch at STI CMP

Defect Count (Arbital Unit)

This case study examines the results of darkfield inspection after STI CMP was performed for the µLoop wafers. Figure 9a shows the defect count following darkfield inspection. No difference was observed between the wafers. The µLoop method was also applied after salicidation. Poly short and active open/short defects showed some slot dependence in

SLOT ID (a)

SLOT ID (b)

Case 2: Gate leakage module In this case, we initially tried to confirm the module function as follows. We processed wafers with three different gate oxide thicknesses, and performed µLoop inspection. Unexpectedly, gate leakage D0 did not increase in the case of thinner oxide. Leakage current in the thinnest oxide was not detectable. The intrinsic leakage might have been larger than background, and all gate lines behaved as grounded. On the other hand,

Proportional to Defect Count (a.u.)

In this section, we will show some examples of the application of the µLoop method in FEOL processes.

dark field inspection µLoop (MT) method

Wafer

Figure 9. Slot versus defect count graph. (a) Darkfield inspection after

Figure 11. Defect count trend from darkfield inspection after STI CMP

STI CMP. (b) µLoop method.

and following µLoop inspection.

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the inline data shows that the gate leakage D0 might be related to the data in the inline inspection tool. Therefore, further study is necessary to distinguish killer defects from non-killer defects.

Case 3: Gate-SD short module In this study, we attempted to investigate whether the gate-SD short module worked well under various conditions in the formation of CoSi. We assumed that the gate-SD short defect would increase in the order as follows: [Condition 1] < [Condition 2] < [Condition 3] < [Condition 4]

Condition 4

Condition 3

Condition 2

Condition 1

(Arbital Unit)

Gate-SD Short Defect Count

Figure 12 shows the condition dependence of the gateSD short defect. The defect count increased as we expected. This result implies that the gate-SD short module worked successfully. Now, we are using this module as a line monitor of gate-SD short.

Figure 12. Condition dependence of gate-SD short defect.

Conclusion

Acknowledgement

The authors would like to thank M. Sadamura, V. Ramani, J. C. Lin, and G. Verma at KLA-Tencor Corporation for their technical support, comments, and suggestions. This article is base on a paper that was originally presented at the International Symposium on Semiconductor Manufacturing 2004. Reprinted with permission from IEEE. References 1. R. Guldi, J. Shaw, J. Ritchison, S. Oestreich, K. Davis and R. Fiordalice, “Characterization of copper void in dual damascene processes,” Advanced Semiconductor Manufacturing IEEE/SEMI Conference and Workshop, April 2002, pp351-355. 2. C. H. Yun, H. Kang, J. B. Lee, H. NamKoong, B. H. Lee, S.B. Chin. T. Tamori, T. Ninomiya and M. Nozoe, “Application of novel EB-inspection to inline monitoring for state-of-the-art DRAM products,” ISSM 2003, pp251254 3. J. Shaw, R. Guldi, T. Kim, D. Corum, J. Ritchison, S. Oestreich, J. Lin, K. Weiner, K. Davis and R. Fiordalice, “Rapid interconnect development using an area accelerated electron beam inspection methodology,” presented at the IEEE International Interconnect Technology Conference, US, June 2002. 4. J. Fretwell, G. Lange, J. Beberman, G. Long, D. M. Price, G. Verma, J. C. Lin, M. Chong and J. Witowski, “Utilization of µloop on the eS20 platform to detect systematic problems in the back end of line copper process and driv e su cce ssfu l corre ct i v e act i ons,” pre se nted a t KLA-Tencor Yield Management Seminar, US, July 2002. 5. T. Suzuki, “Advanced killer defects search µLoop for 90-nm node high end logic device,” presented at KLA-Tencor Yield Management Seminar, Japan, December 2002. 6. V. Lim, “MicroLoop for 0.13 µm Low k Cu interconnect process development,” presented at KLA-Tencor Yield Management Seminar, Singapore, August 2003.

In this paper, we discussed how we tested the µLoop method in FEOL processes for the first time. We confirmed that almost all structures—active O/S, poly O/S, gate-SD short, active-metal contact chain, and poly-metal contact chain—can be evaluated effectively using µLoop. Using this method we can generate information on killer defects and defect density directly and very quickly compared with the conventional e-test. The µLoop method is a powerful technology for detecting killer defects, providing a quick estimation of D0 value, and performing line monitoring.

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