Before testing, DUT is preconditioned to its valid operating state and allowed to stabilise to testing temperature. The testing begins with initial ATE testing of DUT, to ensure the Fail device meets the specifications set for it. Initial () current will Fail Pass be measured and recorded for each pin before applying the stress. After each trigger, the for each pin is measured and Fail Pass checked against failure criteria. If latch-up has occurred, the test is stopped, failed part is replaced with a fresh part, after Figure 2. Schematic of latch-up test. which the testing will continue with other pins. The I-test cycle begins with forcing positive current triggers for all possible operating states of the device. All input, output and configurable I/O pins shall be tested. For complex ICs, the testing can be conducted in worst case operating states. The positive current triggering is followed by negative current triggering, also testing for all pins. The I-test is followed by overvoltage test, where each pin will be tested with voltage triggering. At minimum, a cool-down time between triggers is the same as the duration of the trigger pulse, preferably longer. Failure criteria for latch-up can be set as 1. per nominal current a) if absolute lnom < 25 mA, failure criterium is absolute lnom +10 mA, b) if absolute lnom < 25 mA, failure criterium is absolute lnom . 1.4, 2. does not pass post-stress ATE. A past-stress ATE is used to indicate short-duration latch-up. 3.2.4 Dielectric reliability
Hot carrier injection (HCI) and Bias Temperature Instability (BTI) are transistor aging processes and manifest as degradation of dielectric mainly in MOSFETs. Mainly they can be detected as increase of threshold voltage and circuit delay, and eventually lead to reduction of lifetime. BTI can occur as Negative Bias Temperature Instability (NBTI) affecting mainly pFETs, and Positive Bias Temperature Instability (PBTI) affecting nFETs, especially high-k dielectric materials. HCI can occur in both pFET and nFET, and it does not show recovery effects, while BTI degradation may partially restore over time.
Guidelines for reliability testing on circuit level
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