Performance Analysis for EDMA Based on TIC6678 Multi-core DSP

Scientific Journal of Information Engineering June 2015, Volume 5, Issue 3, PP.73-77

Performance Analysis for EDMA Based on TIC6678 Multi-core DSP Yun Xu #, Yimin Ouyang, Renjie Niu Department of Information Technology, Institute of Optics and Electronics Chinese Academy of Sciences, Sichuan 610209, China #

Email: yzb808@126.com

Abstract Frequent data exchange among all kinds of memories has become an inevitable phenomenon in the process of modern embedded software design. In order to improve the ability of the embedded system data’s throughput and computation, most embedded devices introduce Enhanced Direct Memory Access (EDMA) data transfer technology. TMS320C6678 is a multi-core DSP produced by Texas Instruments (TI). There are ten EDMA transmission controllers in the chip for configuration and data transmissions are allowed to be performed between any two pieces of storage at the same time. This paper expounds the working mechanism of EDMA based on multi-core DSP TMS320C6678. At the same time, multiple data sets are provided and the bottleneck of limiting data throughout is analyzed and solved.

Keywords: EDMA; Multi-Core DSP; High-Speed; Data Throughout

1 INTRODUCTION The traditional way of data transmission is realized by CPU direct access storage device. However, due to the embedded devices often need to process large amounts of data, this traditional method which directly controlled by CPU to exchange data has two disadvantages. Firstly, CPU speed is usually higher than the speed of data transmission between the storage devices outside the chip [1] [2]. Secondly, Data exchange directly controlled by CPU is a redundant operation which will reduce the efficiency of CPU calculation rate. Because of the above reasons, DMA, IDMA or EDMA are used to realize data exchange between different storage devices [3]. The key idea of EDMA (Enhanced Direct Memory Access) is to achieve a large amount of data moving without CPU intervention.

The TMS320C6678 has eight independent cores and each core has 32KB L1D SRAM, 32KB L1P SRAM and 512KB LL2 SRAM, all cores share 4MB SL2 SRAM. In addition, TMS320C6678 also has a 64-bit 1333MTS DDR3 SDRAM interface which can support 8GB external extended memory. EDMA can move data efficiently between the memory devices described above.

64-bit DDR3 SDRAM

4MB MSM SRAM

External memory

C66xTM CorePac 32KB L1D 32KB L1P

512KB LL2 HyperLink TeraNet

FIG. 1 MEMORY ARCHITECTURE OF TI-C6678 SYSTEM

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In this paper, the TMS320C6678 is a chip which has eight independent processing core, and its normal working frequency is 1GHz. Chip integrated with IDMA, QDMA and EDMA is used to realize the flexible high-speed data exchange between different memory[4]. Because EDMA can be used in most memory’s data exchange, and is flexible, efficient and typical, this paper will focus on the principle and test of EDMA. The remainder of this paper is organized as follows: section 2 describes the key technology of EDMA. Section 3 lists the test data and analyzes the results. At the end of this paper, in section 4, this paper is summaried.

2 THE KEY TECHNOLOGY EDMA module can be divided into two parts, channel control and data transceiver. The channel control part mainly realizes event trigger and queue, data transmission mode set and detection. The function of data transceiver part is relatively simple, just realizing the communication with channel control module and accomplishing actual data handling. TI-6678 has 3 channel control module corresponding to 10 data transceiver parts and can handle 10 channel datas simultaneously within the system bus bandwidth permission. Because the channel control module determines the operation mode of EDMA, this paper will describe he trigger, configuration and completion of EDMA based on channel control module.

Figure 2 describes the internal logic structure of EDMA channel control module and the signal’s transmission direction.

Channel Controller

To/from EDMA3 programmer

DMA/QDMA channel logic

Event queues

PaRAM

Transfer request submission

TC[0:n] ERRINT INT[7:0] MPINT GINT

Completion and error interrupt logic

Completion detection

FIG. 2 EDMA CHANNEL CONTROL ARCHITECTURE

2.1 Trigger EDMA has three kinds of trigger modes which are Event trigger, Manual trigger and Chain trigger. Each trigger mode has 64 channels which can receive the trigger event independently. Each event can be identified uniquely by different channel and queuing in the queue to be processed. The trigger in each time is called an event which can be generated artificially or by system. So an event leads to an expected data transmission.

2.2 Configuration Each EDMA transmission is determined by a set of configuration information called PaRAM set which is stored in PaRAM. Each group of configuration information takes 32bytes memory space. Table 1 is the details of PaRAM set.

PaRAM set defines the detailed information needed in the process of transmission which including source address, destination address, the size and way of transmission data and whether a transmission will link to the next after completion of this transmission[5]. The essence of event link is one event trigger causes two EDMA data move which is performed not by the same EDMA channel. Otherwise, the same data moves two times which is not only meaningless but also occupy the internal bus bandwidth and affect the inner data flow speed. TI-6678 design is to link one event to the first channel, then linking this channel’s complete interruption to the other EDMA channel.

When an event is triggered, the first EDMA channel is triggered to transport data. After the first channel completed, it will emit an event to trigger second channel transport data.

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TABLE 1 FONT SIZES FOR PAPERS

OPT SRC BCNT

ACNT DST

DSTBIDX BCNTRLD DSTCIDX Rsvd

SRCBIDX LINK SRCCIDX CCNT

2.3 Detection Completion At the end of EDMA transmission, the corresponding module will generate a completion signal (completion or Early completion), which is generated by the data transmitting and receiving part. Early completion Is generated by the Transfer request process submit module, and completion signal will generate an event interrupt to CPU, notifying CPU that data transmission is completed, or generating a link signal to the channel control part which will prepare for the next data transmission[6].

The whole process of using EDMA is to wait for the arrival of an event trigger after configuration of EDMA transmission mode. At the end of data transmission, the completion detection signal will represent that data transmission is completed. The advantage of this method is that CPU is only responsible for EDMA, the subsequent data transmission does not require CPU intervention, and CPU can perform other operations in the data transmission process. [7].

3 TEST AND DATA ANALYSIS In order to make full use of the bandwidth, it is very important to transmit large data block. It contains three units of measurement (ACNT, BCNT and CCNT) in the process of transmission. In order to make full use of 256-bit bus, ACNT should be an integer multiple of 16 bytes. In order to make full use of burst data block Of EDMA, ACNT should be Integer times of 64 bytes. In order to make full use of EDMA FIFO, ACNT should be at least 512 bytes.

Figure 3 shows the data throughput when data transfer from SL2 to DDR about 1~24KB size on 1GHz C6678 EVM (64-bit 1333 MTS DDR).

Figure 4 illustrates the effect of address offset on the EDMA throughput. These data are measured in 1GHz C6678 EVM (64-bit 1333MTS DDR) which transfer 1024 lines (BCNT= 1024) 2D data from SL2 to DDR transmission.

From the test results in figure 3, we can observe that the bandwidth utilization increases with ACNT’s growth. Each EDMA data transmission contains additional time consuming, thus we use the minimum unit of data transmission completion time delay to represent the EDMA transmission overhead. The additional consuming of using EDMA3CC0 transmission between DDR and SL2 is 266 clock cycles. Thereby for a small amount of data copy, we need to make a trade-off between CPU and EDMA. When transmitting data is small, the extra spending accounts for more than major, shows the result is lower EDMA data transmission bandwidth. When transmitting data increasing, proportion of overhead reduce gradually the EDMA data transmission bandwidth increasing, eventually close to ideal data transmission bandwidth.

From the test results in figure 4, we can see that the linear transmission (Index= ACNT) can make full use of bandwidth. When Index= ACNT and ACNT is a power of 2, 2D transmission is optimized to 1D transmission, so this situation performs much better than others. If the 2D transmission is not linear, the utilization of bandwidth is completely determined by the ACNT. Address alignment has slightly effect on the efficiency of EDMA. EDMA3’s default burst data block size is 128 bytes. If the transmission across the 128 bytes boundary, EDMA3 data transceiver will separate ACNT size data block into 128 bytes burst size data block. This case obviously effects 1 ~ 256 bytes data transmission, but slightly on more large blocks data.

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FIG. 3 ACNT EFFECT DATA THROUGHOUT

FIG. 4 ADDRESS OFFSET EFFECT DATA THROUGHOUT

4 CONCLUSIONS EDMA technology has been applied widely in data transmission between different memories in embedded equipment for its efficient and independent characteristics. How to rationally and effectively use the EDMA module has become the key to increase the efficiency of code execution. This paper introduces the work principle and configuration method of EDMA, then provides test data and makes analysis on the data. Experiments show that, when there are large data need to be transferred, it is an effective measure to use EDMA technology. Under the same conditions, Large EDMA configuration parameter ACNT can improve the data throughput rate of EDMA. At the same time, the offset address selection will greatly affect the transmission efficiency of EDMA. Experiments show that, when the offset is equal to the ACNT parameter, EDMA can play the greatest ability. On the other hand, considering the transmission process of burst data blocks and FIFO buffer on the overall effect of transmission, the data being transmitted is best when it is powers of 2.

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L. Karam, I. AlKamal, A. Gatherer, G. Frantz, D. Anderson, and B. Evans, “Treads in Multicore DSP Platforms,” Signal Processing Magazine, IEEE, vol. 26, no. 6, pp. 38-49, 2009

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TMS320C6678 Multicore Fixed and Floating–Point Digital Signal Processor, Literature Number: SPRS691C, February 2012

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Murtaza Ali, Eric Stotzer, Francisco D. Igual, Robert A.van de Geijn, “Level-3 BLAS on the TI C6678 multi-core DSP,” IEEE Computer Society, IEEE, DOI 10.1109/SBAC-PAD.2012.26, pp. 179-186, 2012.García Márquez, Gabriel. Love in the Time of Cholera. Translated by Edith Grossman. London: Cape, 1988

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System,” in IHMSC, pp. 331–334, August 2009 [7]

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AUTHORS 1

Yun Xu, male, undergraduate student at the school of electronic information of Wuhan University of Hubei

province. Participated in Hubei Province Electronic Design Contest in campus, won the two prize, participated in the National Undergraduate Electronic Design Contest, and won the two prize. During master attended Photoelectric Technology Research Institute China, follow the teacher engaged in related research of embedded equipment, having a plurality of embedded system board design and debugging experience. Research direction during the master is designed for multi-core DSP image processing platform, is a part of 863 project.

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