2011 MEPTEC Media Kit by MEPTEC

Microelectronics Packaging & Test Engineering Council

2011 Media Kit SPRING 2011

WELCOME A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

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A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

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2011 Media Kit

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Microelectronics Packaging & Test Engineering Council Contents

About MEPTEC

MEPTEC Membership Demographics

2011 Advertising Opportunities

MEPTEC Report Newsletter

Distribution

Advertising Rates and Deadlines

Advertising Specifications

Technitorials

1/6 Page Ad Artwork Production Services

2011 Marketing Opportunities

Web Banner Advertising

NEW! Email Banner Advertising

MEPTEC Event Sponsorship

MEPTEC Event Exhibiting Opportunities

2011 Media Kit

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Microelectronics Packaging & Test Engineering Council About MEPTEC

MEPTEC (Microelectronics Packaging and Test Engineering Council) is a trade association of semiconductor suppliers and manufacturers, committed to enhancing the competitiveness of the back-end portion of the semiconductor business. Since its inception over 30 years ago, MEPTEC has provided a forum for semiconductor packaging and test professionals to learn and exchange ideas that relate to assembly, test and handling. Through our membership of subcontractors, semiconductor manufacturers and vendors to the back-end, and an Advisory Board consisting of individuals from different segments of the back-end semiconductor industry, we continuously strive to improve and elevate the roles of assembly and test professionals in the industry.

A SPECIAL ONE-DAY TECHNICAL SYMPOSIUM

MEPTEC&SMTAPRESENT Microelectronics Packaging & Test Engineering Council

MEPTEC MEMS Symposium MEMS and IC System Integration: From Sensing to Awareness S A N

J O S E

•

S A N

C A L I F O R N I A

2.25.10

Presented by

In Association With

Surface Mount Technology Association

A S P E C I A L T W O - D AY T E C H N I C A L S Y M P O S I U M

8th Annual

J O S E

•

2010

Medical Electronics Symposium / Day One Successful Strategies for the Medical Electronics Sector

C A L I F O R N I A

5.20.10

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ABOUT MEPTEC

ADVISORY BOARD

S A N TA C L A R A • C A L I F O R N I A

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11.10.10

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ABOUT MEPTEC

ADVISORY BOARD

INDUSTRY PARTNERS

Applications Driving Requirements

ASU CAMPUS • TEMPE • ARIZONA

9.22.10

Microelectronics Packaging & Test Engineering Council

Semiconductor Packaging Roadmaps

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

Volume 15, Number 1

SPRING 2011

A SPECIAL ONE-DAY TECHNICAL SYMPOSIUM

MEMS Volume 15, Number 1

DRIVING INNOVATION Existing Technologies Enable Future Innovations

SPRING 2011

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

MEMS -

DRIVING INNOVATION Existing Technologies Enable Future Innovations page 12

page 12

World Class Manufacturing Services for Power Management Semiconductors page 14

INSIDE THIS ISSUE

MEPTEC Fall Events Tackled Packaging Challenges for ICs and MEMS Devices

Single Digit Growth for Total Semiconductor Sales in 2011

QFN Packaging The Re-Birth Advances with of Silicon Routable High Interposers? Density Leadframe Technology SPRING 2011 MEPTEC Report 3

World Class Manufacturing Services for Power Management Semiconductors page 14

INSIDE THIS ISSUE

2011 Media Kit

MEPTEC Fall Events Tackled Packaging Challenges for ICs and MEMS Devices

Single Digit Growth for Total Semiconductor Sales in 2011

QFN Packaging The Re-Birth Advances with of Silicon Routable High Interposers? Density Leadframe Technology SPRING 2011 MEPTEC Report 3

www.meptec.org

Microelectronics Packaging & Test Engineering Council MEPTEC Membership Demographics

As of February 2011, MEPTEC membership represents 171 companies in 21 states and 13 foreign countries. Geographically, 93% of MEPTEC member companies are located in North America (U.S. and Canada), 4% in the U.K. and Europe, and 2% in the Pacific Rim region.

U.K. and Europe

Pacific Rim

93%

North America

In the U.S., 321 MEPTEC members represent 161 companies in 21 states.

South America

12%

East Coast

75%

West Coast

13%

Southwest

West Coast membership accounts for 75%, Southwest 13%, and East Coast 12%, of MEPTEC member companies in the U.S.

2011 Media Kit

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2011 Advertising Opportunities MEPTEC Report Newsletter

A primary goal has been to make the MEPTEC Report a marketing tool for MEPTEC member companies. Priority coverage is given to member companies' products, services, and technology development. Advertising in the MEPTEC Report is very cost effective when compared to other trade journals, and reaches a very targeted audience of loyal readers. With the addition of a digital edition the MEPTEC Report reaches an ever increasing audience.

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

Volume 15, Number 1

SPRING 2011

The MEPTEC Report is published four times per year as a service to MEPTEC members and supporters. The full color publication features articles on cutting edge technology, guest editorials, industry developments, and other news applicable to major issues surrounding the world of semiconductor assembly and test.

MEMS -

DRIVING INNOVATION Existing Technologies Enable Future Innovations page 12

World Class Manufacturing Services for Power Management Semiconductors page 14

INSIDE THIS ISSUE

Contact: gedwards@meptec.org

2011 Media Kit

MEPTEC Fall Events Tackled Packaging Challenges for ICs and MEMS Devices

Single Digit Growth for Total Semiconductor Sales in 2011

QFN Packaging The Re-Birth Advances with of Silicon Routable High Interposers? Density Leadframe Technology SPRING 2011 MEPTEC Report 3

www.meptec.org

2011 Advertising Opportunities MEPTEC Report Distribution

Print copies of the MEPTEC Report are distributed directly to all MEPTEC members. Additionally, thousands of bonus copies are distributed at major industry events throughout the year. New for 2011, the MEPTEC Report is available as a digital publication distributed at no charge through the MEPTEC website.

Bonus Event Distribution

All MEPTEC Symposiums and Luncheons

APEX Expo & Conference

Del Mar Electronics Exposition & Conference

ECTC / Electronic Components and Technology Conference

GSA Suppliers Expo & Conference

IMAPS Device Packaging Conference & Exhibition

IMAPS International Symposium on Microelectronics

IWLPC / International Wafer Level Packaging Conference

Known Good Die Packaging & Test Workshop

MEMS Industry Group Executive Congress

RTI Technology Venture Forum

SEMICON West

SMTA International Exposition and Conference

SMTA Pan Pacific Microelectronics Symposium & Exhibition

Contact: gedwards@meptec.org

2011 Media Kit

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4 MEPTEC REPORT SPRING 2011

1/4 Page 3.45 x 4.6

to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled the wafer area, and thus the number of chips, for around same processing cost. Over the past 35 years, geometries have gone from 8 micron (8000 nm) to 4x nm, roughly doubling the number of transistors per square inch every two years. Minimum feature size reduction has been the biggest driver of Moore’s Law. For years, there have been predictions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to maintain Moore’s Law from a technical capability viewpoint ... can we build and run equipment that will allow us to follow Moore’s Law. I think we are beginning to reach a point where we must give serious consideration to the financial aspects of Moore’s Law. Can we justify the ongoing investments to stay on the Law based on a reasonable return on investment and long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the technicaf designing and building the equipment and developing the processes. There is a lot of data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, to recoup their investment and make a profit. There is certainly a case that can be made that a move to 450 mm no predecessors. Whether we are able to maintain adherence to Moore’s Law remains to be seen. If we do start to fall off the Moore’s Law curve, it will probably not be because we can’t develop the technology, but more likely be because we can’t justify the development and equipment cost. ◆

2/3 Page Vertical 4.6 x 9.5

NICK LANGSTON you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled the wafer area, and thOver the past 35 years, geometries.

NICK LANGSTON you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled

To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different understanding. First, it applies only to the Iduction has been the biggest driver of Moore’s Law. For years, there have been predictions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to maintain Moore’s Law from, fab operations and IC folks. There will, however, be some additional expense to those in as: take put 10 million transistors on the head of a pin. Historical progress has caused me to focus on two main drivers for Moore’s Law: wafer size and minimum feature size. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled the wafer area, and thus the number of chips, for around same processing cost. Overduction has been the biggest driver of Moore’s Law. For years, there have been predictions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to maintain Moore’s Law from a technical capability viewpoint ... can we build and run equipment that will allow us to follow Moore’s Law. I think we are beginning to reach a point where we must give serious consideration to the financial aspects of Moore’s Law. Can we justify the ongoing investments to stay on the Law based on a reasonable return on investment and long term health of our industry? For the last couple of

years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the technical wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpensively” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the We, as an industry, take a fierce pride in being able to do the seemingly impossible task of following Moore’s Law. We can now put 10 back of my mind, I assumed you needcost of manufacturing the chips, but also the cost of designing and building the equipment and developing the processes. There is a lot of data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab operations and IC folks. There will, however, be some additional 450 mm must allow vendors to recoup their investment and make a profit. ped. There is certainly a case that can be made that a move to 450 mm no predecessors. Whether we are able to maintain adherence to Moore’s Law remains to be seen. If we do start to fall off the Moore’s Law curve, it will probably not be because we can’t develop the technology, but more likely be because we can’t justify the development and equipment cost. ◆ NICK LANGSTON you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled

To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different understanding. First, it applies only to the IC chip itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. To those of us in the industry, we don’t give it cost factor. It is not of many years. We, as an industry, take a fierce pride in being able to do the seemingly impossible task of following Moore’s Law. We can now put 10 million transistors on the head of a pin. Historical progress has caused me to focus on two main drivers for Moore’s Law: wafer size and minimum feature size. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled the wafer area, and thus the number of chips, for around same processing cost. Over the past 35 years, geometries have gone from 8 micron (8000 nm) to 4x nm, roughly doubling the number of transistors per square inch every two years. Minimum feature size reduction has been the biggest driver of Moore’s Law. For years, there have been predictions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to maintain Moore’s

Law from a technical capability viewpoint ... can we build the based on a reasonable return on investment and long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the technical wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpensively” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the cost of manufacturing the chips, but also the cost of designing and building the equipment and developing of data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab operations and IC folks. There will, however, be some additional expense to those in the assembly/test arena, such as: probe, wafer thin, wafer bump/RDL, saw and die attach. For our industry to remain healthy, a move to 450 mm must allow vendors to recoup their investment and make a profit. Setting 450 mm aside for a moment, these same fab vendors must continue development to allow new node jumps, which have been the main driver of the law. The investments that have been made to drive minimum feature size have been very expensive. Over the past NICK LANGSTON you 15 years, we both havetomoved from needed stay on 350 nm (.35µ) <40 nm. target. When to I started in This the progress industry,alone waferalmost sizes follows Moore’s Law. were 1” and are now The 12” cost of mm). development and (300 Each diamequipment must The outcome eter step roughly doubled of this progress is that we see

PACKAGING

1/2 Page Vertical 3.45 x 9.5

4 MEPTEC REPORT SPRING 2011

SPRING 2011 MEPTEC REPORT 5

To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different understanding. First, it applies only to the IC chip itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. To those of us in the industry, we don’t give it a second thought. I would itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. We, as an industry, take a fierce pride in being able to do the seemingly impossible task of following Moore’s Law. We can non investment and long term health of our in die attach. For our industry to remain healthy, a move to 450 mm must allow vendors t50 mm with all its intendant development cost will dilute the focus and funding on node jump development to the point that no net gain will be realized. We, as an induze. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the technical wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpensively” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the cost of manufacturing the chips, but also the cost of designing and building the equipment and developing the processes. There is a lot of data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab operations

and IC folks. There will, however, be some additional 450 mm To those of us in the industry, we don’t give it a second thought. I would itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. We, as an industry, take a fierce pride in being able to do the seemingly impossible task of following Moore’s Law. We can non investment and long term health of our in die attach. For our industry to remain healthy, a move to 450 mm must allow vendors t50 mm with all its intendant development cost will dilute the focus and funding on node jump development to the point that no net gain will be realized. We, as an induze. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is in the ointment is the word “inexpensively” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the cost of manufacturing the chips, but also the cost of a lot equipment, fab operations and IC folks. There will, however, be some additional 450 mm must allow vendors to recoup their investment and make a profit. ped. There is certainly a case that can be made that a move to 450 mm no predecessors. Whether we are able to maintain adherence to Moore’s Law remains to be seen. If we do start to fall off the Moore’s Law curve, it will probably not be because we can’t develop the technology, but more likely be because we can’t justify the development and equipment cost. ◆

1/3 Page Vertical 2.25 x 9.5

4 MEPTEC REPORT SPRING 2011

SPRING 2011 MEPTEC REPORT 5

To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different understanding. First, it applies only to the Iduction has been the biggest driver of Moore’s Law. For years, there have been predictions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to maintain Moore’s Law from, fab operations and IC folks. There will, however, be some additional expense to those in as: take put 10 million transistors on the head of a pin. Historical progress has caused me to focus on two main drivers for Moore’s Law: wafer size and minimum feature size. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled the wafer area, and thus the number of chips, for aroundrs. Minimum feature size reduction has been the biggest driver of Moore’s Law. For years, there have been predictions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to maintain Moore’s Law from a technical capability viewpoint ... can we build and run equipment that will allow us to follow Moore’s Law. I think we are beginning to reach a point where we must give serious consideration to the financial aspects of Moore’s Law. Can we justify the ongoing investments to stay on the Law based on a reasonable return on investment and long term health of our industry? For the last couple of

To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different understanding. First, it applies only to the IC chip itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. To those of us in the industry, we don’t give it a second thought. I would i itself. It doesn’t involve packaging and itself. It doesn’t involve packaging and itself. It doesn’t involve packaging and tself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Senode jump development to the point that no net gain will be realized. We, as an induze. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the technical wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpendof data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab operations and IC folks. There will, however, be some additional 450 mm must allow vendors to recoup their investment and make a profit. ped. There is certainly a case that can be made that a move to 450 mm no predecessors. Whether we are able to ably not be because we can’t develop the technology, but more likely be because we can’t justify the development and equipment cost. ◆

PACKAGING

nical wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpensively” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the cost of manufacturing the chips, but also the cost of designing and building the equipment and developing the processes. There is a lot of data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab operations and IC folks. There will, however, be some additional expense to those in the assembly/test arena, such as: probe, wafer thin, wafer bump/RDL, saw and die attach. For our industry to remain healthy, a move to 450 mm must allow vendors to recoup their investment and make a profit. Setting 450 mm aside for a moment, these same fab vendors must continue development to allow new node jumps, which have been the main driver of the law. The investments that have been made to drive minimum feature size have been very expensive. Over the past 15 years, we have moved from 350 nm (.35µ) to <40 nm. This progress alone almost follows Moore’s Law. The cost of development and equipment must The outcome of this progress is that we see fabs that cost several billion dollars and mask sets that can cost many millions of dollars. Ther very expensive. Over the past 15 years, we have moved from 350 nm (.35µ) to <40 nm. This progress cost of development and equipment must The outcome of this progress is that we see fabs that cost several billion dollars and mask sets that can cost many millions of dollars. There are opinions the recent node jumps also have yet to be recouped. There is certainly a case that can be made that a move to 450 mm with all its intendant development cost will dilute the focus and funding on node jump development to the point that no net gain will be realized. We, as an industry, take a fierce pride in being able to do the seemingly impossible task of following Moore’s Law. We can now put 10 million transistors on the head of a pin. Historical progress has caused me to focus on two main drivers for Moore’s Law: wafer size and minimum feature size. In the back of my mind, I assumed you needed both

SPRING 2011 MEPTEC REPORT 5

in being able to do the seemingly impossible task of following Moore’s Law. We can non investment and long term health of our in die attach. For our industry to remain healthy, a move to 450 mm must allow vendors t50 mm with all its intendant development cost will dilute the focus and funding on node jump development to the point that no net gain will be realized. We, as an induze. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the technical wherewithal to design, build and operate 450 mm capacity. The pesky fly in the ointment is the word “inexpensively” in Moore’s Law. I have broadened this to include “total expense,” which includes not only the cost of manufacturing the chips, but also the cost of designing and building the equipment and developing the processes. There is a lot

of data that suggests that the industry still has not fully recouped the investment in going to 300 mm. Most of the cost of a move to 450 mm will be borne by fab equipment, fab operations and IC folks. There will, however, be some additional 450 mm must allow vendors to recoup their investment and make a profit. ped. There is certainly a case that can be made that a move to 450 mm no predecessors. Whether we are able to maintain adherence to Moore’s Law remains to be seen. If we do start to fall off the Moore’s Law curve, it will probably not be because we can’t develop the technology, but more likely be because we can’t justify the development and equipment cost. ◆ NICK LANGSTON you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled the wafer area, and thOver the past 35 years, geometries.

1/2 Page Horizontal 7.2 x 4.6

1/3 Page Horizontal 4.65 x 4.6

4 MEPTEC REPORT SPRING 2011

Bleed

PACKAGING

To those of us in the industry, we don’t give it a second thought. I would guess, however, that each of us may have a little different understanding. First, it applies only to the IC chip itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. To those of us in the industry, we don’t give it a second thought. I would itself. It doesn’t involve packaging and it doesn’t involve speed or other IC performance factors. Second, it describes an “inexpensively” cost factor. It is not what a scientist can achieve in a laboratory, but rather what can be done in a commercial environment. Third, there is the dimension of time that is not precise. Fortunately, this evens out over a period of many years. We, as an industry, take a fierce pride in being able to do the seemingly impossible task of following Moore’s Law. We can now put 10 million transistors on the head of a pin. Historical progress has caused me to focus on two main drivers for Moore’s Law: wafer size and minimum feature size. In the back of my mind, I assumed you needed both to stay on target. When I started in the industry, wafer sizes were 1” and are now 12” (300 mm). Each diameter step roughly doubled the wafer area, and thus the number of chips, for around same processing cost. Over the past 35 years, geometries have gone from 8 micron (8000 nm) to 4x nm, roughly doubling the number of transistors per square inch every two years. Minimum feature size reduction has been the biggest driver of Moore’s Law. For years, there have been predictions that Moore’s Law would run out of gas in x (fill in your number) years. I have always viewed being able to maintain Moore’s Law from a technical capability viewpoint ... can we build the based on a reasonable return on investment and long term health of our industry? For the last couple of years, we have been facing a practical decision: whether to go to 450 mm wafers or not. There is no doubt that our industry has the tech-

New Publication Trim Size: 8.0 in. x 10.5 in.

PACKAGING

MEPTEC Report Ad Specifications

1/6 Page Vertical 2.25 x 4.6

SPRING 2011 MEPTEC REPORT 5

Ad Size

Non-bleed

Full page

7.20 x 9.50 in. (183 x 241 mm)

8.25 x 10.75 in. (210 x 273 mm)

8.00 x 10.50 in. (203 x 267 mm)

2/3 vertical

4.60 x 9.50 in. (117 x 241 mm)

5.25 x 10.75 in. (133 x 273 mm)

5.00 x 10.50 in. (127 x 267 mm)

1/2 vertical

3.45 x 9.50 in. (88 x 241 mm)

4.10 x 10.75 in. (104 x 273 mm)

3.85 x 10.50 in. (98 x 267 mm)

1/2 horizontal

7.20 x 4.60 in. (183 x 117 mm)

8.25 x 5.35 in. (210 x 136 mm)

8.00 x 5.10 in. (203 x 130 mm)

1/3 vertical

2.25 x 9.50 in. (57 x 241 mm)

2.90 x 10.75 in. (74 x 273 mm)

2.65 x 10.50 in. (67 x 267 mm)

1/3 square

4.65 x 4.60 in. (118 x 117 mm)

N/A

1/4 vertical

3.45 x 4.60 in. (88 x 117 mm)

N/A

1/6 vertical

2.25 x 4.60 in. (57 x 117 mm)

N/A

Contact: gedwards@meptec.org

2011 Media Kit

Trim

www.meptec.org

2011 Advertising Opportunities

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

Volume 15, Number 1

SPRING 2011

MEPTEC Report Technitorials – A "Technical Editorial"

MEMS -

DRIVING INNOVATION Existing Technologies Enable Future Innovations page 12

World Class Manufacturing Services for Power Management Semiconductors page 14

INSIDE THIS ISSUE

MEPTEC Fall Events Tackled Packaging Challenges for ICs and MEMS Devices

Single Digit Growth for Total Semiconductor Sales in 2011

QFN Packaging The Re-Birth Advances with of Silicon Routable High Interposers? Density Leadframe Technology SPRING 2011 MEPTEC Report 3

Promote your products or services with this unique advertising opportunity. Each MEPTEC Report issue will contain a limited number of “technitorial” features which will highlight different aspects of technology relevant to assembly, packaging and test. The feature will include a right-hand placed full page, four-color advertisement, and a facing full page write-up. Priced at the low cost of $2,500.00, it is essentially two full pages of advertising for the price of 1-1/2 pages. What is a Technitorial? A technitorial is a full page write-up provided by the advertising company that is a complementary technical piece to the full page advertisement, describing the company’s products or services, non-commercial in nature. It will educate and inform the reader, yet will be subtly slanted towards the company’s technology by being placed next to the company’s full page advertisement. The article will not mention the advertising company’s name, but a by-line and contact information will be allowed. Email Gina Edwards at gedwards@meptec.org for availability and to place your order.

2011 Media Kit

www.meptec.org

2011 Advertising Opportunities MEPTEC Report 1/6 Page Ad Artwork Production

Promote your products or services with a low cost 1/6 page four-color ad space in the MEPTEC Report. Rate includes ad artwork, if needed, created using images provided by you (photo and/or company logo) and your text. Network Ad Rates (per insertion) 1/6 page Ad

Standard Rate

Discounted Member Rate

$350

$250

Additional Discounts

Advanced Component Labs, Inc.

A 15% discount will be allowed on pre-paid advertising for four issues or more.

1/6 Page Ad Specifications 1/6 Page Ad artwork can be produced at no additional charge from materials supplied by advertisers. Advertiser should provide one four-color image (either photo or company logo) and one text file. Acceptable electronic formats are as follows: Photo image or logo files need to be provided as eps, tiff, or jpeg files. Images should be at least 300 dpi at the final desired print size for best reproduction quality. Ad text should be approximately 75 words (or less) and submitted as a Word document. Please include your company website URL for inclusion at bottom of ad. Deviation from these guidelines may require additional time or cost, and/or sacrifice reproduction quality.

“Time Critical” Semiconductor Substrates BGA, CSP, Flip Chip, High Frequency, High Speed, Rigid, Cavity and Flex Packages - 25µm Lines and Spaces -

ACL is the only North American company focusing exclusively on the fabrication of “Quick Turn” semiconductor packages. Phone: 408.327.0200 Email: acl1@aclusa.com

www.aclusa.com Shown actual size – 2.25 x 4.6"

Contact: gedwards@meptec.org

2011 Media Kit

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2011 Marketing Opportunities MEPTEC Web Banner Advertising

MEPTEC banner ads are a new, low cost way to gain exposure for your company while stretching your advertising dollars. MEPTEC Banner ads start as low as $95.00 per month for a single unit banner, up $380.00 per month for a quad banner, when purchased on a 12 month contract. All banners appear in the right-hand column on every page of the MEPTEC website and are positioned on a first-come first-served basis. Based on the total number of banner advertisers in any given month, banner ads will be rotated with each advertiser receiving equal number of page views. Microelectronics Packaging & Test Engineering Council

Banner Ad Sizes HOME

ABOUT MEPTEC

ADVISORY BOARD

INDUSTRY PARTNERS

Single Banner: 120 pixels (w) x 90 pixels (h) Double Banner: 120 pixels (w) x 180 pixels (h) Triple Banner: 120 pixels (w) x 270 pixels (h) Quad Banner: 120 pixels (w) x 360 pixels (h)

Banner Ad Specifications Accepted in GIF format only, animation permitted. 15K maximum file size for Single unit banner, 30K for Double, 45K for Triple, and 60K maximum file size for Quad banner. Please provide the URL address for the specific page that you would like to have your ad linked. Banner Prices 1 Month 3 Months 6 Months 12 Months

MEPTEC Member Rate (cost per month) Single Double Triple Quad $125 $250 $375 $500 115 230 345 460 105 210 315 420 95 190 285 380

Non-Member Rate (cost per month) Single Double Triple Quad $150 $300 $450 $600 140 280 420 560 130 260 390 520 120 240 360 480

Contact Gina Edwards at gedwards@meptec.org to place your order.

2011 Media Kit

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2011 Marketing Opportunities MEPTEC Email Banner Ads

A limited number of MEPTEC Monthly Update Email Banner Ads are now available to MEPTEC Members only. These banner ads cost $45.00 per month for a single unit banner, or $450.00 for 12 months when purchased on a 12 month contract. All banners appear in the left-hand column and are positioned on a first-come first-served basis. A maximum of 10 banners will appear on each Monthly Update email. Current monthly distribution numbers approximately 4500 recipients. Microelectronics Packaging & Test Engineering Council

Update for January 2011 Banner Ad Size 120 pixels (w) x 90 pixels (h)

January Luncheon - Next Week!

MEPTEC Symposium - The Heat Is On

Banner Ad Specifications Accepted in GIF format only, animation permitted. 15K maximum file size for single unit banner. Please provide the URL address for the specific page that you would like to have your ad linked. Banner Prices 1 Month 12 Months

Available to MEPTEC Members Only Single Unit Banner $45.00 per month $37.50 per month

Contact Gina Edwards at gedwards@meptec.org to place your order.

2011 Media Kit

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2011 Marketing Opportunities MEPTEC Event Sponsorship

WELCOME MEPTEC&SMTAPRESENT Microelectronics Packaging & Test Engineering Council

MEPTECPRESENTS A

Gold Sponsor: $2,100 – 3 available per event • Company name & logo listed as Sponsor on all promotional materials, including email and web promotions • Full-page black & white ad in event proceedings • 2 free admissions to symposium • 1 tabletop exhibit display at event • Featured as Gold Sponsor in symposium proceedings • 1 CD of symposium proceedings • Company logo/description displayed on video screen at beginning of event • Signage recognition at event • Exposure in semiconductor industry trade magazines (deadline restrictions) • Discount on future MEPTEC Report 1/2 page or larger, 4-color ad

2011 Media Kit

O N E - D A Y

T E C H N I C A L

S Y M P O S I U M

S P E C I A L

T W O - D A Y

T E C H N I C A L

2010

E X H I B I T S

8th Annual

ASSOCIATION SPONSORS

MEPTEC MEMS Symposium

Typical Sponsorship Benefits include: Platinum Sponsor: $3,250 - 3 available per event • Company name & logo listed as Platinum Sponsor on all promotional materials, including email and web promotions • Full-page black & white ad in event proceedings • 3 free admissions to symposium • 1 tabletop exhibit display at event • Featured as Platinum Sponsor in symposium proceedings • 1 CD of symposium proceedings • Company logo/description displayed on video screen at beginning of event • Signage recognition at event • Exposure in semiconductor industry trade magazines (deadline restrictions) • Discount on future MEPTEC Report 1/2 page or larger, 4-color ad

In Association With

Surface Mount Technology Association

S Y M P O S I U M

MicroElectronics Packaging and Test Engineering Council

Presenting Companies:

• Amkor Technology • Analog Devices Fraunhofer Institute for • Silicon Technology (ISIT) • Fullpower Technologies • IMEC • Intel Corporation • IntelliSense • MEMS Industry Group

• Roger Grace Associates • Sandia National Laboratories • Silicon Clocks • SVTC of California • atUniversity Berkeley • WiSpry, Inc. • Yole Développement

GOLD SPONSORS

M AY

SILVER SPONSOR

2 0 ,

2 0 1 0

•

S A N

J O S E ,

Association Sponsor

ASU Sponsor

Medical Electronics Symposium

MEMS and IC System Integration: From Sensing to Awareness

Original Image Courtesy Sandia National Laboratories

MEPTEC offers a variety of event sponsorship opportunities for its technical symposiums. Event sponsorship provides a valuable opportunity to promote your company brand and product or service message to attendees while supporting your business development and positioning goals.

C A L I F O R N I A

MEDIA SPONSORS

TAP TIMES ®

Successful Strategies for the Medical Electronics Sector Wednesday & Thursday September 22nd & 23rd Corporate Sponsors

A SPECIAL ONE-DAY TECHNICAL SYMPOSIUM

Semiconductor Packaging Roadmaps

Applications Driving Requirements

Media Sponsors

SANTA CL ARA • C ALIFORNIA

Presented by

11.10.10

Output (1) @ 100% of File Size • Final Size 31.5” x 79.75”

Silver Sponsor: $1,250 – 10 available per event • Company name & logo listed as Sponsor on all promotional materials, including email and web promotions • 1/2 page black & white ad in event proceedings • 1 free admission to symposium • Featured as Sponsor in symposium proceedings • 1 CD of symposium Proceedings • Company logo/description displayed on video screen at beginning of event • Signage recognition at event • Exposure in semiconductor industry trade magazines (deadline restrictions)

Note: Sponsorship pricing and benefits may vary from event to event. For specific sponsorship details and more information contact Gina Edwards at gedwards@meptec.org.

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2011 Marketing Opportunities MEPTEC Event Exhibiting Opportunities

MEPTEC offers table top exhibit opportunities at its technical symposiums throughout the year. A limited number of table-top exhibit spaces are available on a first-come, first-served basis. Each draped table is 2-6 x 6-0.â&#x20AC;Ż The cost includes a table and chairs, a complimentary table top sign, company description in the Symposium proceedings, and one complimentary admission to the symposium.You may use your table to display literature, parts, small pieces of equipment, table top display signs, etc. A table top sign will be provided, but you may also wish to display a banner or some other appropriate type of sign on the front or top of the table. 2011 MEPTEC Symposiums March 21

The Heat is On: Performance and Cost improvements Through Thermal Management Design Doubletree Hotel, San Jose, CA

May 19 9th Annual MEMS Symposium â&#x20AC;&#x201C; MEMS Market Evolution Wyndham Hotel, San Jose, CA September 27 & 28 6th Annual MEPTEC Medical Electronics Symposium (co-sponsored bt SMTA) Arizona State University, Tempe, AZ November 8

MEPTEC Semiconductor Packaging Symposium Biltmore Hotel, Santa Clara, CA

November 9

Know Good Die Packaging and Test Workshop (in association with SEMI) Biltmore Hotel, Santa Clara, CA

For more information contact Gina Edwards at gedwards@meptec.org.

2011 Media Kit