MEPTEC REPORT FALL 2021

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

November 9 –11, 2021

FALL 2021

MEPTECReport Volume 25, Number 3

REGISTER TODAY!

Road to Chiplets:

DATA&TEST

MEPTEC presents the second in a series of cross-functional workshops focused on the practical aspects of designing, implementing (packaging), and testing Chiplets. page 15

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How Traditional Waffle Pack/Chip Trays are Exacerbating the High Price of Obtaining Known Good Die (KGD) page 9

Scaling the Chiplet Adoption Wall page 14

Design of Heterogeneous Integrated Circuits – Chiplets and Modeling page 20 INSIDE THIS ISSUE

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UP FRONT As Summer turns to fall and vacations are distant memories, many are again focused on work.

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CALL TO ACTION Supply chain decision makers are betting on a single source subcontractor to provide 90% of America’s solder columns.

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COUPLING & CROSSTALK Clearly the most obvious time to step back and reevaluate is when things are not going according to plan.

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CATCHING UP WITH Zoë Conroy is Principal Hardware Engineer at Cisco.

She joined the MEPTEC Advisory Board in 2020.

UP FRONT The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council 141 Hewitt Street, Summerville, SC 29486 Tel: (650) 714-1570 Email: bcooper@meptec.org Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown Sales Manager Gina Edwards

MEPTEC Executive Director Ira Feldman

MEPTEC Advisory Board Board Members Dave Armstrong Advantest Ivor Barber AMD Calvin Cheung ASE (US) Inc. Zoë Conroy Cisco Jeff Demmin Keysight Technologies Abram Detofsky Intel Neal Edwards AMD Jaspreet Gandhi Xilinx Ravi Mahajan Intel Emeritus Advisors Seth Alavi Sunsil Joel Camarda Anna Gualtieri Elle Technology Phil Marcoux PPM Associates Mary Olsson Herb Reiter eda 2 asic Consulting, Inc., Retired In Memoriam Ron Jones

Contributors Zoë Conroy Cisco Darby Davis Delphon Industries Ira Feldman Feldman Engineering Corp.

Martin Hart TopLine Corporation Rob Munoz Intel Design and Engineering Group Jawad Nasrullah Consultant, formerly zGlue Inc. David Ratchkov Thrace Systems James Wong Palo Alto Electron

MEPTEC Report Vol. 25, No. 3. Published quarterly by MEPCOM LLC, 141 Hewitt Street, Summerville, SC 29486. Copyright 2021 by MEPCOM LLC. All rights reserved.

Materials may not be reproduced in whole or in part without written permission.

MEPTEC Report is sent without charge to members of MEPTEC. For non-members, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere. For advertising rates and information contact Gina Edwards at 408-858-5493.

Back to School!

Ira Feldman Executive Director, MEPTEC

Now that summer has turned to fall and our vacations are distant memories, many of us are again focused on work. While most children have returned to school, adults are in different phases of transitioning back to the office from full-time to part-time to delayed re-openings to remote forever.

However, it is not just children who should return to school. Now is the time for adults to head back to school too! “Wait, we haven’t returned to our offices yet so why should we go back to school?” you ask… Well, it is not exactly going back to school with classrooms run by chalk wielding teachers. It is time for all of us to study up on our technology. Plus learn the latest gossip industry news!

MEPTEC started the Road to Chiplets series in July with Road to Chiplets – Architecture focused on the high-level decisions that need to be made to implement a product using a Chiplet approach. This two-day virtual event had great participation with seven hundred registrations and five hundred live attendees.

If you missed any of the excellent presentations, you will find them on events. meptec.org including links to the YouTube videos.

The next stop in the road trip, i.e. the next class, is Road to Chiplets – Data & Test which will be held as a free virtual event on three days November 9 - 11, 2021. It is focused on the required cross-functional data sharing across factories and suppliers that is essential to transition Chiplets from design of experiments and prototypes to commercial reality. It will cover new data sources including new test steps and new ways of analyzing and sharing data. Register today to not miss it! You wouldn’t want hear that the class was full…

We are working on the planning for 2022 and look forward to resuming in-person events while retaining some virtual events. Do share your suggestions and feedback on what you would like to learn/see/do and how MEPTEC can best serve you. And don’t be shy!

Stay safe and healthy!

Ira Feldman Executive Director, MEPTEC ira@meptec.org +1 650-472-1192

FALL 2021 MEPTEC REPORT | 3

CALL TO ACTION

FPGA Industry Bets on Immortality Martin Hart TopLine Corporation

THE RESPONSIBILITY OF PROVIDING timely delivery of Field Programmable Gate Arrays (FPGA) for use in warfighters and space applications is entrusted to a relatively small number of civilians in the industrial base. The entire supply chain relies on an uninterrupted supply of solder columns, the last step in the manufacture of aerospace and defense grade LGA packaged FPGA components.

Betting on Immortality Decision makers in the supply chain are betting on the immortality of a single source subcontractor that provides 90% of America’s solder columns. Simply stated, the defense establishment is placing a high stakes gamble that one subcontractor will be in business 5 years from now, or even 30 years from now.

Should one assume that the Department of Defense agrees with decision makers in the industrial base?

Risk Analysis Let’s analyze the odds of this wager.

Firstly, it is helpful to review some unclassified information available in the public domain.

Fact 1. Less than 100,000 aerospace and defense FPGA devices are produced annually that require solder columns to connect the FPGA device package to the PC board.

Fact 2. Solder columns perform a critical function to reduce stress on the FPGA device and assure resiliency (operational longevity in rugged environments) of the device within black-box systems.

These ruggedized FPGA devices can not operate without solder columns. In other words, there is a risk that the supply chain can come to a halt should solder columns suddenly become unavailable.

Even though 100,000 devices may not

4 | MEPTEC REPORT

FALL 2021

seem significant, they are nonetheless the primary critical devices that are required to keep warfighters flying and rockets launching.

At the time of this writing, only one subcontractor (Six Sigma) is certified by the Defense Logistics Agency (DLA) to perform solder column attachment services in the United States.

Decision makers in the supply chain are betting on the immortality of a single source subcontractor that provides 90% of America’s solder columns.

It may take as long as a 3-year process for FPGA device makers to certify additional vendors to perform column attachment services on defense and space grade FPGA components.

The controlling owner of America’s single-source column vendor is quickly approaching the age that most people are considering to retire.

Even if retirement is not in his plans, actuarially speaking, it is a high stakes bet to assume America’s sole column attachment vendor will be operational 20 years from now.

Most manufacturers of defense and aerospace grade FPGA devices are

satisfied with relying on one-supplier and have not taken steps to qualify an alternative supplier of column attachment services.

Civilian managers within the supply chain have decided not to qualify alternative suppliers of column attachment services.

It appears that no U.S. Government agency, such as the Department of Defense, has a policy in place that creates incentives for chip makers to qualify alternative suppliers of column attachment services.

Consequences of Inaction The author predicts that before the end of this decade, there could be End of Life (E.O.L.) announcements by chip makers whose FPGA devices will no longer be available with solder columns. The onset of such an event will put the defense and space industry into a tailspin.

This scenario should be disturbing to thousands of customers who rely on an uninterrupted supply of Aerospace and Defense grade FPGA devices with solder columns.

Normally, the loss of just one supplier in the supply chain can be covered by another supplier providing a similar product or service.

Sadly, today there is no industry-wide Plan “B” solution to continue delivering FPGA devices with columns in the event of a loss of the nation’s solely certified provider of column attachment services.

Conclusion To reduce risk of a formidable collapse of warfighter and space missions that rely on FPGA components with solder columns, steps should be taken by the Department of Defense to incentivize chipmakers to engage and certify alternative subcontractors for column attach services before disaster actually strikes. ◆ meptec.org

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MEMBER NEWS Intel Advances Neuromorphic with Loihi 2, New Lava Software Framework and New Partners

Second-generation research chip uses pre-production Intel 4 process, grows to 1 million neurons. Intel adds open software framework to accelerate developer innovation and path to commercialization.

INTEL HAS INTRODUCED Loihi 2, its second-generation neuromorphic research chip, and Lava, an open-source software framework for developing neuro-inspired applications. Their introduction signals Intel’s ongoing progress in advancing neuromorphic technology.

“Loihi 2 and Lava harvest insights from several years of

collaborative research using Loihi. Our second-generation chip greatly improves the speed, programmability, and capacity of neuromorphic processing, broadening its usages in power and latency constrained intelligent computing applications. We are open sourcing Lava to address the need for software convergence, benchmarking, and cross-plat-

form collaboration in the field, and to accelerate our progress toward commercial viability.”

–Mike Davies, director of Intel’s Neuromorphic Computing Lab Neuromorphic computing, which draws insights from neuroscience to create chips that function more like the biological brain, aspires to deliver orders of magnitude improvements in energy efficiency, speed of computation and efficiency of learning across a range of edge applications: from vision, voice and gesture recognition to search retrieval, robotics, and constrained optimization problems. Applications Intel and its partners have demonstrated to date include robotic arms, neuromorphic skins and olfactory sensing.

More details may be found in the Loihi 2/Lava technical product brief. ◆

Xilinx and NEC Accelerate Next-Generation 5G Radio Units for Global Deployment XILINX, INC. AND NEC CORPORATION have announced that the companies are collaborating on NEC’s next-generation 5G radio units (RUs) expected to be available for global deployment in 2022. Xilinx® 7nm Versal® AI Core series devices, which are currently shipping in volume production, will enable greater performance in the new NEC RUs. These latest NEC 5G massive MIMO RUs utilize digital beamforming for more efficient communication and wider bandwidth.

Designed to address worldwide markets, NEC RUs will support a wide range of 5G frequencies, including C-Band. The Xilinx Versal AI Core series devices used within the NEC RUs enable advanced signal processing and beamforming, while also integrating O-RAN capabilities. O-RAN interfaces enable open and flexible 5G RAN deployments, in addition to allowing broader interoperability with products from different vendors.

“NEC’s new massive MIMO radios using Xilinx’s commercially-proven beamforming capabilities will enable an improved wireless meptec.org

end-user experience as use cases continue to grow and evolve in the future,” said Liam Madden, executive vice president and general manager, Wired and Wireless Group at Xilinx.

“The combination of NEC’s leadership in massive MIMO radio design and Xilinx technology will deliver a compelling solution to the ORAN market.”

“In the highly competitive 5G base station market, the integration of Xilinx technology within NEC RUs will provide valuable advantages to our customers who demand highlycapable and feature-rich RUs that deliver the performance needed to scale for nearly any application,” said Kenichi Ito, general manager, 1st Wireless Access Solutions Division at NEC. “The Xilinx Versal AI Core series delivers on its design promise for performance and scalability by using advanced signalprocessing for massive MIMO antennas and beamforming. We look forward to continuing our collaboration with Xilinx.”

For more information visit www.xilinx.com and www.nec.com. ◆

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INTEGRA ANALYSIS LAB GRAND OPENING

INTEGRA TECHNOLOGIES has announced the opening of the Integra Analysis Lab at the Integra Technologies’ headquarters in Wichita, Kansas. The state of the art 2,700 square foot lab expansion will house 15 new pieces of specialized test equipment allowing for 150 projects to be run per week at the new lab.

Onsite DPA will give Integra the ability to reduce the time needed to complete component qualifications that directly impact time to market, allowing customers to pull in schedules to meet the nation’s demand for qualified microelectronics. The new Lab will bring approximately 40 engineering positions and non-technical operator positions. www.integra-tech.com

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GEL-PAK NAMED FINALIST IN SAN FRANCISCO EAST BAY’S INNOVATION AWARDS

GEL-PAK, a division of Delphon and worldwide leader in protective carriers for semiconductor, optoelectronic, and medical devices, was recognized as a finalist in the East Bay Innovation Awards for its new LCS2 product. Out of more than 200 nominations, the GelPak's LCS2 product was among 20 innovations chosen for this special honor.

The LCS2 product was developed in partnership BAE Systems, a global defense electronics manufacturer, to help save millions of dollars in costs due to device damage and labor associated with semiconductor chips migrating out of their packaging during transit. www.gelpak.com

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FALL 2021 MEPTEC REPORT | 5

Infineon and Panasonic Accelerate GaN Technology Development for 650 V GaN Power Devices

INFINEON TECHNOLOGIES AG AND PANASONIC CORPORATION have signed an agreement for the joint development and production of the second generation (Gen2) of their proven gallium nitride (GaN) technology, offering higher efficiency and power density levels. The outstanding performance and reliability combined with the capability of 8-inch GaN-on-Si wafer production mark Infineon’s strategic outreach to the growing demand for GaN power semiconductors. In accordance with market requirements, Gen2 will be developed as 650 V GaN HEMT. The devices will allow for ease of use and provide an improved price-performance ratio, targeting, amongst others, high- and low-power SMPS applications, renewables, motor drive applications.

For many designs, gallium nitride (GaN) offers fundamental advantages over silicon. The outstanding specific dynamic on-state resistance and smaller capacitances compared to silicon MOSFETs qualify GaN HEMTs for high-speed switching.

The resulting power savings and total system cost reduction, operation at higher frequencies, improved power density, and overall system efficiency make GaN a very attractive choice for design engineers.

“In addition to the same high reliability standards as for Gen 1, with the next generation customers will benefit from even easier control of the transistor as well as a significantly improved cost position, thanks to moving to an 8-inch wafer manufacturing,” says Andreas Urschitz, President of Infineon’s Power and Sensor Systems Division.

Launch of the new GaN Gen2 devices is planned for the first half of 2023. ◆ 6 | MEPTEC REPORT

FALL 2021

Semiconductor Sales Hit All-Time Record VLSI's Semiconductor Analytics Report

SEMICONDUCTOR SALES BLEW past $11B to hit an all-time weekly record.

The IC weather cooled another 1°F for the week. Markets were mixed, with Memory & MM Foundry cooler. SoC warmed to Hot. IDM, MtM, and OSAT were hotter. Last week, Auto ICs had the highest W/W growth, followed by Logic, NAND,

DRAM, and Analog & Power. Focusing on Analog & Power, MAs continue to run at levels ~35% higher than 2020. VLSI's current forecast is for it to finish the year up 30%.

IC Wafer Fab Production continued to ride a capacity ceiling, as wafer price inflation almost hit 40% Y/Y. VLSI's IC Supply/Demand indices jumped Tight last week with OSAT, More Moore, and More than Moore Foundry rising a notch. DRAM, NAND, IDM, Auto IC, and Analog & Power were all stronger.

The 3Q21 Supply/Demand NowCast held at Balanced.

Electronics' Retail Prices continue to trend down with signs of a bottom.

For more information visit https://www. vlsiresearch.com/services/semiconductoranalytics ◆

Intel to Break Ground on Two New Leading-Edge Chip Factories in Arizona

Intel’s newest factory, Fab 42, became fully operational in 2020 on the company’s Ocotillo campus in Chandler, Arizona. Fab 42 produces microprocessors using the company’s 10nm manufacturing processes. In March 2021, Intel announced a $20 billion investment to build out two new factories (or “fabs”) on the Ocotillo campus. The company expects to begin planning and construction activities this year. (Credit: Intel Corporation)

WITH ITS IDM 2.0 STRATEGY, INTEL is committed to investing in manufacturing capacity to support the surging global demand for semiconductors. The company recently announced plans to build two new leading-edge chip fabs at its Ocotillo campus in Chandler, Ariz. The new factories will support expanding requirements of Intel’s products and provide committed capacity for foundry customers.

On Friday, Sept. 24, Intel CEO Pat Gelsinger was joined by government and community leaders for a groundbreaking ceremony to celebrate the largest privatesector investment in Arizona history: a $20 billion project that will bolster U.S. semiconductor leadership and help bring geographical balance to the global supply chain. ◆

meptec.org

COLUMN COUPLING & CROSSTALK

By Ira Feldman Electronic coupling is the transfer of energy from one circuit or medium to another.

Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought-provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Disruptions, Graduations, & Transitions WHEN AND WHY IS REFLECTION appropriate in our life and work processes? Stepping back and analyzing the situation (with the least possible bias) is not only appropriate when conditions change, it is essential! Such reflection is necessary not only when things go wrong, but especially when things go right.

Clearly the most obvious time to step back and reevaluate is when things are not going according to plan. It is also often the most difficult time as one may be in the middle of “delivering” – i.e. bailing water fast enough to keep the ship afloat long enough to reach the destination. Or if “all hands are on deck”, meaning there is no one left to do the analysis without slowing things down or missing a deadline. It is rare that in a crisis anyone would want to be accused of not pulling their weight resulting in everyone focusing on tactical solutions rather than longterm strategy.

The less-obvious times for reflection?

Whenever disruptions, graduations, and other transitions take place. Disruption is when outside factors change so significantly that the process is no longer viable.

We have had over eighteen months of disruption grappling with how to best respond to the pandemic. Absolutely everything has changed – from organizations hesitant to allow telecommuting now requiring work-from-home “for now”, to cancellation of travel and events, to days full of Zoom calls, and more. As restrictions are loosened, we are now working on the “new normal” which I can assure you will be meptec.org

clearly different than the “old normal”.

As we work through the disruption of Covid-19, many are simply trying to keep their heads above water. Companies and individuals are doing what it takes to make it to the end of the day, end of the week, end of the quarter, and beyond to the “new normal”. At the same time, self-aware individuals and learning organizations are doing the hard work of assessing what it is they want to do and how to change their practices during the disruption. Much of this change may not have an immediate pay-off but it is positioning for future success. Race car drivers reportedly say that races are won in the curves and not the straightaways.

Graduation is the successful completion of a significant process that may not be done on a regular basis. Think of an acquisition, a major product family launch, or the restructuring of an entire business. These activities are extremely disruptive and difficult to manage especially when short term goals are not the eventual objective. (We were very excited that our twin children graduated high school in June and have started their college journeys! As we remind them, college majors are what they are concentrating on now and although this will provide a foundation it is not necessarily what they will be doing for the rest of their lives.)

In the business world, learning organizations hold “postmortems” upon the completion of programs, sales opportunities won or lost, etc. – at the end of a process or “graduation”. These postmortems allow the team to capture the lessons learned and identify process improvements.

An often-overlooked reflection point is transition. The more important the transition, the more likely reflection will occur.

Personally, we will be rethinking – or should I say reducing - a lot of day-to-day activity as we are now empty nesters.

Maybe this is more like graduation than a simple transition… but we have also done this each year when we do the switch from “summer schedules” to school year schedules.

The business analog of transitions can be seen in companies that use a stagegate Hardware-Software Product Life Cycles (HSPLC) or the equivalent. More thorough HSPLCs have a process review step as part of each stage’s exit criteria to force the discussion of what should be changed in the process for the next product. For organizations that are event

driven – like MEPTEC with quarterly or yearly events – postmortems should be done as part of each event to collect the details and improve for the next time. The key, regardless of the business cycle or structure, is that the review – i.e. taking the time to reflect and identify places to improve - is built into the process.

Many friends have complained about the proliferation of online meetings in the current work-from-home (WFH) environment. Some do nothing other than attend back-to-back Zoom meetings throughout an ‘extended’ workday all week long.

Unfortunately, the ease of “gathering” i.e. no physical logistics or limitations has made it easier to become over scheduled.

Or should I say, has eliminated easy excuses for not attending. And saying “sorry I cannot attend since I need to get some work done” is not an acceptable excuse in many organizations.

I see no improvement in the situation as organizations move back to the office part- to full-time. It will be common for some of the attendees to be remote for many meetings even if they are located near the meeting place. As organizations transitioned to WFH setups it was done as knee-jerk reaction to the pandemic. Very few organizations recognized this transition as point for inflection. It was more “the show must go on so we will simply switch to web meetings” than “we need to make a change, how do we improve our processes”. And although much thought is being put into the safety and process of reopening offices, very little is being put into the fundamental processes of work.

Mismanaged meetings remain a pet peeve of mine. Just because you can meet, should you? What is the purpose of the meeting? Can it be handled more efficiently in some other manner? Is it the best medium for the information that needs to be conveyed? (That’s a trick question – if you are simply conveying information the answer is you shouldn’t have a meeting.) Due to the low apparent “cost” of online meetings, more are held without proper planning or meeting discipline. The biggest cost of a meeting is not the physical space or travel expense, it is the value of everyone’s time. The larger number of people at a meeting, the greater the true cost. Just because your web conferencing service is billed at a flat rate for unlimited usage, does not mean the incremental cost of the meeting is zero! (continued on page 18) FALL 2021 MEPTEC REPORT | 7

Dragos Maciuca Executive Technical Director Ford Motor Company

YOU DRIVE THE FUTURE OF MOBILITY. WE ACCELERATE THE PROCESS.

Learn how SEMI Smart Mobility is synchronizing the automotive and electronics supply chains.

The automotive industry is rapidly evolving to meet the world's shifting transportation needs. Explore how the SEMI Smart Mobility initiative addresses industry challenges, harmonizes regional and global priorities, and grows new business opportunities. To learn more, visit semi.org/semiismore.

SEMI IS MORE

PACKAGING

How Traditional Waffle Pack/Chip Trays are Exacerbating the High Price of Obtaining Known Good Die (KGD) by Causing Defects from Die Migration Darby Davis Vice President Sales and Marketing Delphon Industries

THE NEED FOR KNOWN GOOD Die (KGD) was originally introduced in the 1980s with Multi-ChipModules (MCMs) due to their brittle ceramic dielectric material where excessive die replacement rework was inevitable. This problem is only exacerbated in 2.5D and 3D chiplet designs where just a singular defective die often results in the entire part being discarded. Once a die is tested and determined to be “good”, it is important to ensure it remains that way while being handled internally or transported from one location to another.

The use of traditional waffle pack/chip trays for shipping thin KGD has the potential to cause unpredicted failures due to die migration (Figure 1). In a study completed by BAE Systems, a global military electronics manufacturer, and Gel-Pak, it was determined that millions of dollars were being lost due to component defects, Return Material Authorizations (RMA’s), rework labor, and other Cost of Poor Quality (COPQ) incidents associated with the use of waffle pack/chip trays. The analysis brought to light that die migration, or Component-Out-Of-Pocket (COOP) conditions, most frequently occurred at the supplier site or during transit before ever reaching the end customer.

A novel testing methodology involving the use of x-ray scanning equipment illuminated these failures by peering within the closed waffle pack without altering or removing the lid.

This way, failures could be identified when they occurred at the supplier site and during transit. The major culprit was found to be the large gap between the tray and lid of the traditional waffle pack.

This article discusses the proper handling meptec.org

Figure 1. Die migration condition shown in standard waffle pack.

of bare die and how unforeseen failures can occur due to the migration of thin semiconductor components (< 0.010”).

Additionally, how the new patented Lid Clip Super System (LCS2) readily addresses these challenges and allows for both the manual and automated handling of bare die.

The Costly Considerations Around Known Good Die (KGD) In the heyday of Moore’s law, every two years the transistor density reliably doubled and, along with Dennard scaling, the performance per watt of these chips scaled accordingly.

This golden era of microelectronics has slowed down with smaller (<7nm) device geometries where meeting the high performance needs of modern applications now requires costlier fabrication and/or larger die sizes.

However, the cost to fabricate large dies has grown increasingly uneconomical – the larger the die, the smaller the yield.

This apparent slow-down of Moore’s law has led semiconductor manufacturers

and design firms to seek alternative solutions including the disaggregation of the large, monolithic functionality into interconnected smaller dies. The “chip of the future” now consists of a number of different chips all interconnected to perform compute-intensive processes.

All of these trends have yielded a demand for Known Good Die (KGD) – a bare die that has been fully tested prior to packaging. This requirement began with the production of MultiChip Modules where faulty chips would cause manufacturers to replace the entire module. Now, with chiplet design, the “large die” is partitioned into custom-designed, hardened IP blocks (or smaller die) that are co-optimized with other blocks. These blocks are all highly integrated, calling for KGD in order to maintain high yield and costeffectiveness. Bare dies are notoriously difficult to test and to handle. Bare die must be tested using a specialized wafer prober while packaged parts can be measured with standard automated test equipment. This entire manufacturing process shifts testing earlier to ensure that the parts going into a multi-chip/ chiplet package are a higher quality.

Known Good Die (KGD) are bare die that meet datasheet specifications in regards to quality, reliability, as well as basic electrical and mechanical performance. In this way, it is not very different from a packaged part. There are, however, significant challenges in ensuring their performance. For starters, as die and chips grow increasingly thin, the wafers are susceptible to cracks during the sawing process. Moreover, the fine bump pitches found on the bare die must be accessed via probe card FALL 2021 MEPTEC REPORT | 9

PACKAGING

Figure 2. The trend for wafer diameter, thickness, and individual die thickness[3].

technology where a custom probe card with thousands of probing needles press the micro bumps in order to rapidly test for defects via the high voltage stress, low voltage, or Iddq test methods. This is not a perfect process. The probe cards themselves can damage the die’s bond pads. For these reasons the KGD themselves are tied to a Parts Per Million (PPM) and Failures In Time (FIT) level.

Higher reliability applications might require 100 PPM while most commercial applications will have around 1,000 PPM[1]. Since testing the latest generation of assembly technologies for defects is still less than completely accurate, some organizations have shifted the term KGD to a more reasonable Known Not Bad (KNB) to describe die.

This differs vastly for conventionally packaged chips where final testing occurs after the wafer sort and packaging.

The wafer sort process is by contrast much simpler. These high-throughput machines process entire wafers at speed and batch them into their respective lots while also performing visual inspections

with infrared (IR) cameras checking for defects such as cracks and particles.

The concept and realization of KGD has shifted testing earlier in order to increase the yield of the MCMs, systemin-package (SiP), and chiplets at the vendor’s end. However – with all these innovations around bare die testing to ensure it is KGD – it is even more critical to handle these components properly after testing to ensure the die reaches the end user functional.

Addressing the Trend of Decreasing Die Thicknesses There is another factor to consider when handling bare die – whether or not the component has been thinned. As more chips are integrated vertically in 2.5D and 3D stacking configurations, one method to decrease the overall package thickness is to thin the die themselves.

Wafers are grinded down to thicknesses as low as 50 μm (or 0.002”) in order to ensure thin device packaging. This is key in wearable device manufacturing where unconventional package dimensions are necessary. Thin die can also be found packaged on flexible substrates in applications where pliability and nearimperceptibility are required such as in smart-forms, -labels, -tickets, and -bank notes as well as e-devices and micro LEDs. For power devices, thinner dies are able to perform faster heat dissipation on a copper lead frame to reduce its on-state resistance (Rds(on))[2], this in turn increases device efficiency and stability/ reliability. Overtime, standard wafer

diameters have steadily increased from around 100 mm up to 300 mm while wafer thicknesses typically stand around 600 to 750 μm (depending upon the wafer size) . However, current wafer back grinding techniques have dropped wafer and individual die thicknesses to 50 μm (Figure 2).

Die thinning comes with a series of design, grinding, packaging and general handling considerations. The back grinding itself can lead to die surface roughness and subsurface damage causing microfractures that compromise the mechanical integrity of the die (i.e. die strength). The dies also become more susceptible to crack formations and chipping during the sawing process, reducing the final package yields at the supplier’s end and potentially increasing FIT and decreasing mean time between failures (MTBF) for end-user device long-term reliability. Obtaining KGD becomes more difficult in these circumstances. There is also the added difficulty of stacking these devices.

The 3D stacking of dies on a thinned die leads to a lower yield rate because these devices are relatively fragile.

There are libraries of literature dedicated to manufacturing techniques around the design, fabrication, and quality of thinned die. Therefore, the transport and handling of these thinned KGD should also be seriously considered.

Waffle packs/chip trays are a commonly used method in handling thinned die.

However, shipping thinned die using this method can be problematic.

Figure 3. For decades, semiconductor industry professionals have been unable to adequately isolate the root cause of the die migration issue, often casting blame on one another for migrated components.

10 | MEPTEC REPORT

FALL 2021

meptec.org

The Culprit for Shipping Failures – Die Migration These waffle packs are a lesser recognized cause for failures during handling and shipment. Thin semiconductor dies of less than 250 μm thickness often migrate out of the pockets of the waffle pack’s trays. Waffle packs themselves are manufactured via injection molding where the final product is constructed of a suitable plastic material. The compartments can be built into the mold itself or cut into with a drill or laser to generate the pockets.

The width, length and positioning of these pockets is highly researched in order to best fit its desired component and allow for automated handling via a pick-and-place machine. However, the flatness tolerance associated with these carriers is often overlooked (Figure 3).

Thin components can be easily displaced with vibrations during transport where a die can be flipped within its pocket, rotated causing automated handling errors, or even caught between pockets leading to further migration issues after the pack is opened. All of these potential die migration events can lead to device damage as the sensitive components bounce around the waffle pack pockets and grind against each other.

With the associated complexities around the thinning and processing of die as well as the testing KGD, damaged die during transit in waffle packs directly leads to a substantial loss of dollars.

An increase in operating expenditures where non-value added labor such as component inspection and reordering must occur. This reduces pick and place machine utilization or causes the overengineering of automated assembly systems in order to compensate for die migration. All of which interrupts production and causes lead time delays.

These Component-Out-Of-Pocket (COOP), or die migration, defects were identified to be the major cause of BAE systems’ high cost of return material authorizations (RMAs), yield loss, and rework labor.

Isolating the Issue in BAE Systems’ Supply Chain The XQuick II x-ray counter system

by VJ Electronix was developed for BAE Systems in 2017 in order to visually meptec.org

Figure 4. X-ray image of traditional waffle pack with RF die. Image taken upon receiving at the end-user showing die migration on arrival.

Figure 5. Comparison of lid surface flatness taken from Keyence VR-3200 showing inadequate specs for the containment of thin die.

inspect components in sealed waffle packs (Figure 4). These x-rays showed that die migration issues not only stem from injection molding tolerances of the waffle pack and from operator error when the components have reached the end-user, but also at supplier sites and during transit; before the chips ever reach the customer.

Inadequate Flatness Tolerance Much of these failures stem from two of the top three root cases of die migration: the flatness tolerance of the injection molded materials used in the manufacturer’s waffle pack tray and lids.

The Keyence VR-3200 3D measurement system illuminated this issue, showing the level of warpage in both the waffle pack’s tray and lid. As shown in Figure 5, carbon loaded polypropylene waffle packs feature an upper limit of 300 μm (or 0.012”) while flatter, carbon loaded

polycarbonate counterparts can have an upper limit as low as 100 μm (or 0.004”). Both of which are not suitable for thinned die that go as low as 50 μm (or 0.002”).

The flatness profile of the lid surface is further shown with the VR-3200 in Figure 6 where there is a gradual deflection from the center of the lid to its edges. This warpage shows a maximum deflection of 239 μm (or 0.0094”) from the center to the edges – almost five times the thickness of a 50 μm die.

Pinching of Loose Inserts and Device Contamination Non-woven polyester inserts (typically Tyvek) are commonly used to provide ESD protection for the seated die. However, they have become a prevalent cause for die migration failures due to their misalignment or pinching during the waffle pack assembly process FALL 2021 MEPTEC REPORT | 11

PACKAGING defect transport/handling. This allows for the robust housing of devices down to 50 μm thicknesses. The lid employs low density polyurethane foam and industryapproved interleaf material assembled into a static dissipative injection molded lid using silicone free pressure sensitive adhesive (Figure 8). A unique gold static dissipative resin is employed for both the molded lid and clip to provide ESD class 000 protection for high value devices with the lowest voltage susceptibility thresholds.

The new LCS2 clip design uniformly compresses the lid around its full top perimeter onto the tray to ensure complete contact against the waffle pack tray surface. This prevents die migration due to tray and lid warpage.

Figure 6. Internal lid surface flatness measured using Keyence VR-3200 3D measurement system.

Figure 7. A standard waffle pack and lid separating during handling causing the resulting die migration.

(Figure 7). This pinching can work against the operator by creating an even larger gap between the tray and lid. Use of loose inserts also results in increased operator labor costs.

Deformation of Lid and Tray by One-Piece Clip The industry standard one-piece clip also causes uneven stresses on the chip and tray causing deformations of these components and increased chance for die migration. This ultimately warps both the tray and lid, adding another avenue for defects to occur due to die migration.

Eliminating the Issue of Die Migration with the Lid Clip Super System In order to effectively prevent these failure modes the waffle pack must do all of the following: • Uniformly seal each tray pocket 12 | MEPTEC REPORT

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• Compensate for tray and lid flatness issues • Be compatible with pick & place machines • Only use static dissipative, low outgassing, non-silicone, foreign object defect free (FOD-free) materials To solve BAE Systems’ COOP failures and the needs of the market, Delphon developed the Lid Clip Super System (LCS2). The patented LCS2 product was specially designed due to the migration of thin devices and addresses all the common causes of COOP due to warpage, pinched paper inserts, and industry standard one-piece clip utilization. The LCS2 solution consists of a special clip and padded lid that provides effective gasketing of each and every pocket to seal components within each compartment, ensuring zero

Qualifying the Novel Lid Clip Super System Efficacy of the LCS2 was demonstrated through a rigorous series of drop tests with 100 μm (0.004”) GaN devices.

These drops were conducted from 34” and 84” and an x-ray system was used to verify the effective containment of the internal bare die (Figure 9). A total of one hundred drop tests were performed (10 LCS2 dropped 10 times each).

The results revealed the elimination of die migration. A control test was also performed using an industry-standard one-piece clip in place of the novel LCS2 clip. In this case, die migration did occur, indicating the importance of the LCS2 clip.

The Implications of the LCS2 for KGD and Other Bare Die Between visual inspection, specialized testing, and careful handling during and after back grinding, the cost behind KGD and thinned die demands the use of a reliable waffle pack/chip tray.

The utilization of a robust waffle pack system that effectively sidesteps die migration failures while also allowing for automated handling enables semiconductor professionals to more rapidly package their devices, qualify them, and minimize failures in the field and longterm wear-out. All of these factors speed up the production process and enable the seamless use of industry-standard pickand-place equipment, saving on supply chain operating expenditures. ◆ meptec.org

References

[1] R. Arnold, S. M. Menon, B. Brackett and R. Richmond, “Test methods used to produce highly reliable known good die (KGD),” Proceedings. 1998 International Conference on Multichip Modules and High Density Packaging (Cat. No.98EX154), 1998, pp. 374382, doi: 10.1109/ICMCM.1998.670811.

Figure 8. Exploded view of the Lid-Clip Super System (left) and cross-sectional view of the system showing gasketing of the tray pockets (right).

[2] Z. Abdullah, L. Vigneswaran, A. Ang and Goh Zhi Yuan, “Die attach capability on ultra thin wafer thickness for power semiconductor,” 2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT), 2012, pp. 1-5, doi: 10.1109/IEMT.2012.6521812.

[3] Marks, M. R., Hassan, Z., &amp; Cheong, K. Y. (2015). Ultrathin wafer Pre-Assembly and assembly Process Technologies: A review.

Critical Reviews in Solid State and Materials Sciences, 40(5), 251–290. https://doi.org/10.10 80/10408436.2014.992585

Figure 9. GaN devices employed in LCS2 (left) with results of 34” drop test (center) and 84” drop test (right) showing no die migration defects.

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TECHNOLOGY

Scaling the Chiplet Adoption Wall Rob Munoz, Principal Engineer Intel Design and Engineering Group

“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected”[1] Gordon E. Moore, “Cramming more components onto integrated circuits”, Electronics, Volume 38, Number 8, April 19, 1965.

IN HIS FAMOUS 1965 PAPER OUTLINING what came to be known as Moore’s Law, Gordon Moore foreshadowed in the quote above that a chipletlike approach would become attractive.

By chiplets, we mean die that have been optimized to connect to other die within the same packaged device. If we fast forward many years later, more and more disclosed products are using chiplets with many more in development (a recent EE Times article [2] has a valuable historical perspective). The IEEE, in collaboration with SEMI and ASME, has sponsored a Heterogeneous Integration Roadmap [3] effort to foster collaboration and technology preparedness. Within Intel’s internal Chiplet Work Group, we believe a chiplet approach will become the “new normal”, especially when building chips (both merchant and custom) for data center and edge deployments.

Thanks to the use of a well-specified and open standard die to die interface, AIB (Advanced Interface Bus, see recent CHIPS Alliance presentation [4] for an in-depth introduction), multiple generations of Field Programmable Gate Arrays (FPGAs) and custom products have been able to successfully leverage chiplets. These chiplets (in the form of AIB tiles) have been produced by Intel (initial contributor of AIB to the CHIPS Alliance) as well as by customers and ecosystem partners. Chiplet-based FPGAs in particular help enable a valuable continuum of customizable solutions. Early in the product lifecycle FPGAs enable substantial updates to the logic customers deploy. Over time some or all of this logic 14 | MEPTEC REPORT

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Figure 1. Multigenerational FPGA example supporting AIB tiles and HBM (via EMIB-based advanced packaging).

can be migrated to structured ASICs (e.g. eASIC™ devices [5]) and/or fully hardened logic, both of which could be a mix of standard product and custom chiplets.

This type of approach has been especially valuable when building products where the underlying technology and standards are rapidly evolving (e.g. 5G/6G radio access network [6], data center accelerators [7] , etc.).

High Bandwidth Memory (HBM, specified in the JESD235 series of standards [8]) is another example of successful multigenerational, multiproduct, and multivendor adoption of a chiplet approach enabled by well-specified and broadly adopted standards. HBM has been successfully adopted for graphics, artificial intelligence/machine learning, and highperformance computing (HPC) applications.

However, apart from the multiproduct and multivendor usage demonstrated with HBM and with the AIB ecosystem (figure 1 illustrates a multigenerational FPGA example incorporating both), most chiplet usage to date has been confined to integrating die designed by the same company applied to building chips for the same product types (e.g. processors from Intel and AMD). For example, Intel and custom silicon customers have leveraged 2.5D Embedded Multi-Die Interconnect Bridge (EMIB) [9] and/or 3D Foveros [10] advanced packaging to greatly reduce the

area and distance overhead of multi-die integration. Intel has used the term “tiles” to describe chiplets that are integrated using high-density, high-bandwidth interconnects enabled by advanced packaging technologies such as Intel’s EMIB and Foveros.

Chiplet Tradeoffs In theory, a chiplet approach should be able to provide several important benefits.

These benefits include reducing portfolio (both product and project) costs, helping scale innovation and delivery capabilities, and improving time to solution.

Product cost reduction is the most frequently mentioned potential benefit of chiplets. Smaller die will have fewer defects than larger die (especially in the early years of manufacturing at a leadingedge process node) and can help achieve higher mask field utilization. Likewise, each chiplet can be built in a process node that is optimal for its intended usage.

There is no need to port all chip intellectual property (IP) to the newest (and typically most expensive) process node. The number and type of chiplets populated in a chip can more closely match the configuration that the customer is paying for (e.g. for a processor, this might include core count and I/O capabilities), reducing the amount of disabled or “dark” silicon (continued on page 16) meptec.org

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TECHNOLOGY

Figure 2. Chiplet interface specification requirements for industry scale adoption.

(continued from page 14) that needs to be manufactured. In combination these factors can significantly improve efficiency and cost effectiveness per silicon wafer (especially valuable when manufacturing capacity is tight).

A chiplet approach also enables construction of chips with a silicon area bigger than the reticle limit (currently 33 mm x 26 mm = 858 mm2; see the IEEE IRDS chapter on lithography [11] for projected trends). Larger chips are often very desirable when addressing the highest performance data center and HPC processing requirements. However, even with a chiplet approach, the maximum practical size of a commercial volume chip will still be limited by thermal, mechanical warpage, etc. considerations.

Chiplets can also help reduce project costs, scale innovation and delivery capabilities, and reduce time to solution.

Chiplets can be combined in different arrangements to create many combinations of useful chip configurations without requiring new die developments. Customized chips can be created which reuse existing chiplets created internally, by customers, and/or by 3rd parties. As mentioned above, there is no need to port all IP to be used in a chip to a single target 16 | MEPTEC REPORT

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process node.

However, there is no “free lunch” with chiplets. It is important to manage the associated trade-offs around tiling overheads, thermal and input/output (I/O) escape constraints, and associated supply chain and economic considerations. The die-to-die interface that connects chiplets together in a package will typically consume more area, power, and performance overhead than on-die connectivity would require. Packaging, assembly, and test costs and durations will generally be higher for multi-die chips than monolithic chips. Any additions to cycle time (processing and/or transit times) or supply chain uncertainty will often require additional inventory to be carried. It is often impractical to co-package multiple “hot” die or die that each require a lot of external PCB connectivity. Purchasing external chiplets typically incurs margin stacking and additional inventory carrying costs.

Chiplets built to be 3D stacked with other chiplets have historically needed to be carefully co-designed (e.g. due to thermal, power delivery, signal integrity, etc. considerations), hindering the ability to reuse them in other contexts. Finally, chiplets are not economically optimal in cases where a single “sweet spot” monolithic alternative is feasible and attractive.

The Broad Adoption and Scaling Challenge Assuming we focus on the growing class of usages for which the benefits outweigh the costs, what is required to trigger broad multicompany chiplet adoption to access these benefits at industry scale?

The industry must address key adoption and scaling prerequisites including: • Fully specified interface standards (see figure 2 for details) • Sufficient production volumes to achieve “critical mass” (needed to jump start the network and learning effects that are key to creating and sustaining a viable ecosystem) • Enabling building blocks and tools/ flows/methods to help easily apply these building blocks • Broad market production capabilities for the associated production flow (including assembly and test) As mentioned above, sufficient production volumes to achieve “critical mass” are needed to jump start the network and learning effects which in turn are key to creating and sustaining a viable ecosystem. Likewise, enabling building blocks and tools/flows/methods are needed to help easily apply these building blocks. As Adner has observed [12], ecosystem carryover is often a great approach meptec.org

for HBM. Likewise, specifying relatively simpler interfaces that can work with either standard or advanced packaging is ideal since these can more easily ride the technology curve to take advantage of future bump pitch scaling (hybrid bonding is especially promising in this regard [17]).

Figure 3. Chiplet packaging and physical connectivity taxonomy with examples,

whereby existing, successful ecosystems can be leveraged (including their building blocks, tools, etc.) to create new ecosystems.

For chiplets, it is valuable to carryover the high volume PCIe (and related Compute Express Link - CXL) ecosystems as well as build on the AIB ecosystem to jump start a viable chiplet ecosystem.

PCIe and CXL provide a proven model for interoperability between XPU (CPU, GPU, etc., where the “X” in “XPU” stands for any compute architecture that best fits the needs of the application [13]) and other die built by different suppliers, address system-on-chip (SoC) construction issues (e.g. address space configuration, reset, initialization, register access, etc.) and security considerations. Together they can address both address a broad variety of transactional use cases (load/store data transfer via the PCIe or CXL.io protocols, memory access via the CXL.mem protocol, and cache coherent accelerator and I/O access via the CXL.cache protocol).

Likewise, PCIe/CXL provide a uniform software model that blurs the distinctions between whether functions are integrated on die, in package, or at the board or system level. This software uniformity can be especially important for providing uniform cloud to edge solutions. With CXL/PCIe compatible chiplets and separately packaged (and potentially scaled up or out) counterparts, we can create many configuration variants using a smaller meptec.org

number of software compatible plug and play building blocks. This kind of reuse is key to portfolio cost economics.

By also providing “raw” access to the chiplet physical layer, it is possible to support SerDes, optical I/O chiplets, as well as to support streaming interfaces that continuously transfer large volumes of unstructured data. These interfaces are often needed when partitioning specialized analog or mixed signal functionality on a different die than digital logic.

Microbumps and/or hybrid bonding advanced packaging capabilities facilitate low overhead and high density I/O escape.

Of course, even with the benefit of ecosystem carryover and complete interface standards, additional work must still be done in several important areas including design automation tooling, test [14], reliability [15], modeling and simulation [16], etc. as described in the IEEE Heterogeneous Integration Roadmap [3] and other places.

From a physical connectivity perspective, it is best to initially focus on specifying 2D and 2.XD compatible interfaces (see figure 3 for an illustration of chiplet packaging and physical connectivity taxonomy). As is mentioned above, typically 3D chiplets need to be carefully codesigned with the other die in the stack (due to thermal, power delivery, etc. considerations). However, it is reasonable to specify a 2D/2.XD interface to a 3D stack of chiplets much like JESD235 has done

Conclusion To summarize, a chiplet approach has tremendous potential. However, there are some important adoption and scaling prerequisites that we must meet to achieve the desired benefits. In addition to having well-defined standard interfaces for interoperability, it will be important to have sufficient production volumes to achieve “critical mass” to drive the associated network and learning effects. I/O (optical, SerDeS, etc.) and XPU attach are promising use cases to help drive market demand and associated production volumes. Carrying over the PCIe/CXL ecosystem to support XPU attach can help jumpstart a broad chiplet ecosystem while providing a reusable software model that enables uniform cloud to edge solutions.

By addressing these prerequisites, the industry can create a rich and innovative chiplet ecosystem. High performance chiplet express lanes will interconnect the separately constructed and manufactured functions that Gordon Moore described in 1965, fundamentally reshaping how companies collaborate to build semiconductorbased systems in the future. ◆ Author Biography

Rob Munoz is a Principal Engineer in Intel’s Design and Engineering group located in Austin, TX. His day job is architecture for custom/semicustom/ standard products targeted at wireless infrastructure (largely the radio access network portion). He also co-leads the cross-Intel Chiplet Working Group. He has been with Intel since November 2014, joining as part of Intel’s acquisition of LSI/Avago’s networking business.

At LSI/Avago/Agere he was previously a Distinguished Engineer focusing on architecture and systems engineering for the Axxia and PayloadPlus multicore/ network processor product families. He started his career at Bell Labs in Columbus, OH where he worked on telecommunications signaling systems. He has an MS in Computer Science from UT Austin and currently has 15 granted patents.

FALL 2021 MEPTEC REPORT | 17

TECHNOLOGY Acknowledgements The perspective I have shared is based on the work of Intel’s internal Chiplet Work Group. I especially want to thank Dave Kehlet, Tanay Karnik, Ramune Nagisetty, Peter Onufryk, and other collaborators in this effort over the last 4+ years.

References

[1] Gordon E. Moore, “Cramming more components onto integrated circuits”, Electronics, Volume 38, Number 8, April 19, 1965, reprint downloadable from https://newsroom.intel.com/wp-content/uploads/ sites/11/2018/05/moores-law-electronics.pdf [2] Don Scansen, “Chiplets: A Short History”, EE Times, March 14, 2021, https://www.eetimes.com/ chiplets-a-short-history [3] Heterogeneous Integration Roadmap, IEEE Electronics Packaging Society, https://eps.ieee.org/technology/heterogeneous-integration-roadmap.html [4] David Kehlet et. al., “Advanced Interface Bus (AIB) Die-to-Die PHY Deep Dive”, CHIPS Alliance, August 10, 2021, https://chipsalliance.org/wp-content/uploads/sites/83/2021/08/CHIPS_Alliance_AIB_ Deep_Dive_081021.pdf (slides) and https://www. youtube.com/watch?v=FPQkZk5x-z4 (recording) [5] Intel® eASIC™ Devices, Intel Corporation, https:// www.intel.com/content/www/us/en/products/details/ easic.html [6] Intel® 5G Network Infrastructure Fact Sheet, Intel

Corporation, https://newsroom.intel.com/wp-content/ uploads/sites/11/2020/10/Intel-5g-network-infrastructure-fact-sheet.pdf [7] Microsoft Project Catapult, Microsoft Corporation, https://www.microsoft.com/en-us/research/ project/project-catapult [8] JESD235D: High Bandwidth Memory (HBM) DRAM, JEDEC, March 2021, https://www.jedec. org/standards-documents/docs/jesd235a [9] “Embedded Multi-Die Interconnect Bridge”, Intel Corporation, https://www.intel.com/content/www/us/ en/silicon-innovations/6-pillars/emib.html [10] “Up Close with Lakefield – Intel’s Chip with Award-Winning Foveros 3D Tech”, Intel Corporation, https://newsroom.intel.com/news/up-close-lakefield-intels-chip-award-winning-foveros-3d-tech [11] Lithography 2021 update, International Roadmap for Devices and Systems, IEEE, 2021, https:// irds.ieee.org/images/files/pdf/2021/2021IRDS_Litho. pdf [12] Brian Leavy, “Interview Ron Adner: managing the interdependencies and risks of an innovation ecosystem”, Strategy & Leadership, VOL. 40 NO. 6, 2012, pp. 14-21, https://thewidelensbook.com/pdfs/ StrategyAndLeadership.pdf [13] “Match Every Application to Its Optimal Architecture with XPU”, Intel Corporation, https:// www.intel.com/content/www/us/en/architecture-andtechnology/xpu.html [14] Pooya Tadayon et. al., “Moore’s Law and the Future of Test”, Chip Scale Review, May – June 2021, https://www.chipscalereview.com/wp-content/

uploads/2021/05/ChipScale_May-Jun_2021-Intel.pdf [15] IEEE Reliability Committee, IEEE Electronics Packaging Society, https://cmte.ieee.org/reliability [16] “Chapter 14: Modeling and Simulation”, Heterogeneous Integration Roadmap, IEEE Electronics Packaging Society September 2020, https://eps.ieee. org/images/files/HIR_2020/ch14_ms.pdf [17] “Packaging: Hybrid Bonding Test Chip”, Intel Corporation, August 13, 2020, https://newsroom. intel.com/wp-content/uploads/sites/11/2020/08/intel2020-architecture-day-fact-sheet.pdf

Legal Disclaimer

© INTEL CORPORATION. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. Check with your system manufacturer or retailer or learn more at intel.com.

Cost reduction scenarios described are intended as examples of how a given Intel-based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. This document may contain information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications, and roadmaps.

COLUMN (continued from page 7) I have attended plenty of meetings that feel like they are inefficient or even a waste of time. I’m certainly not perfect: I have held meetings that were not fully prepared or as efficient as desired. But what I do have is a conscious process of asking myself “why are we meeting, what is expected, and is this the best way to achieve the goals” before each meeting.

And I take a moment to reflect afterwards to see how well it went. There are plenty of good books and tutorials on meeting management, I’m happy to recommend some if desired.

Another “back to school” reminder for those who confuse being busy with being productive. Like school, some ratio of ‘homework’ to meeting time is critical. Some academic rules of thumb are 2 to 3 hours of homework for each hour 18 | MEPTEC REPORT

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of lecture. In school the upper bound on homework is set by the ability to learn independently. The ratio of independent work time versus group time will depend on the nature of the work. However, the bottom line is that no one can get meaningful work done while constantly in meetings. And as we reminded our children there are plenty of studies that show when you attempt to “parallel process”, you are doing neither item well regardless of your perception. May I also suggest if you find yourself doing something else during a meeting, the meeting may not be structured for success.

It is difficult to reflect while you are busy managing a crisis, especially if you are trying to “muster your troops” via Zoom. The classic consultant comment “step back from the stage and observe the show from the balcony” is great advice. As the Feldman Engineering team

is busy running technical conferences and virtual meetings for several organizations, we find it helpful to remember this to best organize, moderate, and provide the needed support to reach our client’s goals.

The bottom line... If you or your organization are not using disruptions, graduations, and transitions as reflection points, then you will not survive. If you do not have the time, do not know where to start, or lack the proper perspective, it is time to get an outside consultant to provide short term guidance and/or strategic assistance for your company.

For more of my thoughts, please see my blog http://hightechbizdev.com.

As always, I look forward to hearing your comments directly. Please contact me to discuss your thoughts or if I can be of any assistance. ◆ meptec.org

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Design of Heterogeneous Integrated Circuits – Chiplets and Modeling Jawad Nasrullah, Consultant, formerly CTO zGlue Inc David Ratchkov, CEO, Thrace Systems James Wong, Head of Engineering, Palo Alto Electron

HETEROGENEOUS INTEGRATION brings the best of different manufacturing lines into one integrated circuit package, helps improve yield with chiplet partitioning, enables ease of upgradability, and helps with packing more functionality and performance in integrated circuits. Monolithic integration, which has been the best option so far, now has prohibitive costs associated with design, and manufacturing with the fabless business model. For value addition and new features, product developers need customizing, exclusive, and value-added integrated circuits with functionality from a variety of manufacturing lines hence chiplet-approach is the way to move forward.

Heterogeneous Integrated Circuits Design Styles A number of design styles and packaging options are available for heterogeneous integration providing various optimization strategies for cost, performance,

and product planning. Multi-chip module (MCM) approach has been used quite successfully for assembling silicon dies from various sources along with other components and sets a baseline reference. While there are new architectural choices in terms of die disaggregation, a key decision facing every chiplet architect is to pick a suitable package integration technology and chiplet interconnect.

This choice is critical not just for cost control but provides a key competitive advantage and is one of the most important early decisions.

Packaging and Integration Choices Figure 1 shows a few popular options and a future trend for stacking. In most of these design styles multiple manufacturing lines are involved for a) silicon (shows with grey), b) package substrate or fanout (shown with green), and c) assembly of components. All of these manufacturing steps have been part of the current chip ecosystem. The packag-

ing and assembly steps, however, need to play a bigger role for heterogeneous integration. Most of the manufacturing lines sell material and components based on area, number of layers of processing, and complexity and yield of processing.

Let’s look at some broad categories.

Multi Chiplet Modules with Substrates and Organics Multi Chiplet Module (MCM) design style, as shown in Figure 1a, is well understood and is being used in the chiplet-based products in the market.

Chiplets get assembled on a substrate, typically built with organic materials.

Such substrates are available readily in the market with improvements in the fine-pitch of wiring and vias (state of the art 10 μm line width and 10 μm line space). Key design challenges are related to routing density. This constraint of wiring pitch limits the utility of such substrates for low wire-count inter-chiplet signaling—typically based on serializa-

Figure 1. IC Packaging Stacking Styles: a) Multi Chiplet Modules b) Chiplets on 2.5D c) Chiplets on Active Interposer d) Chiplets with Embedded Silicon Bridge e) Front End Chiplets and 3D-ICs.

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tion and de-serialization (SerDes) of signal busses. The assembly, however, performs well for quality and reliability due to maturity. Cost-wise, these substrates compete well with high-density printed circuit boards as chip carriers and offer a decent solution as long as architects can optimize inter-chiplet die-to-die communication. Usage of SerDes results in power and latency overhead though.

Chiplets on 2.5D Chiplet and die stacking on a silicon interposer has been successfully used for high-performance applications such as microprocessors and high-bandwidth memory (HBM) combination, and fieldprogrammable gate arrays (Figure 1b).

The issue of wiring density as present in the MCM design style gets addressed in 2.5D by using a base interposer chip that provides dense interconnect at submicron pitch using semiconductor lithography-based fabrication. In HBM interconnect the communication link between the processor and memory requires wiring of several thousand signals and silicon interposer is the mature option for such construction at the moment.

While passive silicon interposers provide adequate fine-pitch wiring density, the thickness of wires is suboptimal to support large switching currents. Additionally, the extra cost of silicon interposer die just for wiring adds cost that is only justified by performance gains. The industry is pushing alternative manufacturing techniques to displace these silicon interposers with high-density redistribution metal layers (RDL) and fanout-out processing. While cost is an important consideration, it is important to note that silicon on silicon type of 2.5D assembly behaves well on thermal and mechanical performance resulting in improved reliability especially for high-performance and high-power computing applications.

Chiplets on Active Interposers Active Interposers extend the 2.5D design style while adding circuitry in the silicon of the interposer (Figure 1c).

Active interposers act like another chiplet providing system-level functionality.

Such interposers have been demonstrated to include connectivity, power management, testability, programmable logic and routing, and other side-band funcmeptec.org

tions. The key idea in such designs is to partition functionality across heterogeneous manufacturing lines for unit cost optimization [1]. Input-output circuitry, for example, does not need the most advanced logic process and instead can be built on an analog-circuit-friendly process and used for multiple products.

This design style is useful in some of the base chip of memory chip stacks. At first glance, it appears that the cost of the active interposer is an add-on, but a detailed look at the bill of material breakdown can reveal opportunities for comparative cost reduction with respect to single-chip solutions or even printed circuit board solutions. The homogeneity of the material stack of silicon-on-silicon is also an advantage similar to the case in 2.5D implementation.

Chiplets with Embedded Silicon Bridges It is quite attractive to use a silicon bridging to connect silicon dies together as shown in Figure 1d. Previous demonstrations have been made to use capacitive coupling bridges and even inductive coupling [2] [3]. Direct conductive attach of silicon dies for bridging has now also been demonstrated in commercial products. Bridge silicon can also be used as a chiplet with built-in functions. The challenge, however, occurs with the issues related to the expansion and contraction of dissimilar materials at dissimilar rates when embedded within. Nonetheless, this is a promising technique and costeffective solutions may be possible.

Front End Chiplets and 3D-IC The real interesting application of chiplets is in the front-end factory of semiconductor fabrications (Figure 1e).

While some of these technologies have been available through academic labs for quite some time, there is a clear path for commercial availability of these technologies in a fabless model. The added advantage of these technologies includes design possibility for extreme power optimization, performance gains via dense vertical interconnects, and a possibility to displace organic substrates altogether.

Chips vs Chiplets Chiplets have uncanny similarities to chips and silicon intellectual property (IP). There are, however, some remarkable differences in particular for the design as shown in Table 1. Chiplets are physical goods unlike intellectual property: someone has to manufacture chiplets and supply them to the assembler with a warranty much like chips. Chiplet suppliers need to provide verification support to the designers in a style similar to what silicon IP vendors do. Most importantly chiplets are designed for package-level assembly as opposed to printed circuit board-level assembly. And the inputoutput (IO) constraints in such applications are different and for example, the IO drive strengths may not work with some test equipment. Additionally, more detailed performance and operational models are needed for chiplets than what has been traditionally supplied with chips or IP.

Table 1. Chips vs IP vs Chiplets.

FALL 2021 MEPTEC REPORT | 21

CIRCUIT DESIGN Chiplet Models Chiplet models can be built with a combination of models from silicon design and printed circuit board design.

Modeling of the physical dimensions and input-output pin locations is a relatively well-understood problem that was first solved for multi-chip modules in the early 1990s. Several model formats exist to help with the artwork generation for substrate design including MCM, AIF, XDA, DTF, and ZEF. These models are sufficient as long as the multi-chip modules are designed as miniaturized printed circuit boards. With die-disaggregation and more complex chiplets, silicondesign level automation requires system modeling covering power, thermal, behavioral, electrical, and testability.

The Chiplet Design Exchange (CDX) workstream at the Open Compute Project (OCP) Open Domain-Specific Architecture (ODSA) subproject is developing a recommendation for chiplet modeling to enable industry collaboration beyond electronic design automation (EDA) software to address the requirements from designers, architects, and chiplet vendors.

ZEF models for chiplets were developed by zGlue Inc and released via an open-source license. These include three main model exchange files, mech. zef, io.zef, and elect.zef. The mech.zef contains the mechanical information of the chiplet. The io.zef contains the input and output information of the chiplets.

The elect.zef represents the electrical information of the chiplets. The filename and contents are case insensitive. There is a new XML version of the ZEF being defined under the same open license.

ZEFXML is an enhancement as it supports multiple value options data such as the IO function along with an associated XML Schema [4].

Design of Heterogeneous ICs The design of heterogeneous integrated circuits requires system-level design aspects to be considered early in the architecture phase. In particular thermal, mechanical, reliability, and system-level testing has to be part of early design exploration. Floorplanning includes extreme attention to thermal cross talk and power delivery design.

The integrity of power delivery requires detailed modeling of components as well 22 | MEPTEC REPORT

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Figure 2. A typical multi-chiplets system with power delivery parasitics and data communication across components.

Figure 3. A power model of a chiplet based system includes a power-dominant radio. Note the system-level model goes through various usage scenarios..

as the interconnect. Signaling quality and its close relationship to packaging system attribute such as interconnect impendence control as well as surface roughness are remarkably different when compared to chip design or printed circuit board design. A typical design flow includes starting with a thermally driven floorplan which in turn drives signaling and testability design. Key design activities include multiple iterations through a)

Floorplan and thermal design, b) Power and Thermal modeling, c) Signaling and IO design, d) Routing, e) Testability, and e) Verification. (see Figure 2) Power and Thermal Design Power and thermal modeling must be one of the earliest architecture considerations for a system design. For a chiplet based system power modeling sets the basic understanding for design meptec.org

limits for heat dissipation, energy, and current handling capabilities. Early architecture exploration of power can be based on quick equation-based analysis, but a methodology is needed to refine the power estimates as the chiplets progress through the design flow. The main target of such modeling should be to correlate the final system power measurements to validate assumptions.

A system-level power model should meet several criteria: • It must enable architectural exploration, where a user can derive estimates under different conditions, such as temperature and voltage, as well as usage scenarios.

• It must enable progressive modular updates and refinement, where the component power models can be easily upgraded.

• It must be capable of representing a rich set of data, such as datasheets, measurements, rough estimates, gatelevel data, and even data with spice-level accuracy.

• It must be able to handle digital and mixed-signal models seamlessly.

Figure 3 shows the result of power modeling of an integrated circuit built with eight chiplets including a radio that dominates energy usage, memory, cache, and voltage regulators. Note that this system is drawing the most amount of power in the radio transmission scenario and that the integrated voltage regulation adjusts system-level voltages for optimum operation. The model was built using the above-mentioned criterion and was the basis for simulating thermal conditions and crosstalk.

Figure 4 shows a thermal map for the system modeled in Figure 3. Note that this thermal condition is still acceptable for the component running hot, but the heat starts to affect neighbors. System architect needs to consider the long-term usage of the system in this scenario for reliability in the field.

Signaling Unlike a fixed wiring stack-up inside a silicon chip, the designers have the option to specify conductor and dielectric thickness to control the trace impedance. On the other hand, the surface roughness, line-edge roughness, and non-planar topography due to back-end meptec.org

Figure 4. Thermal maps generated for the system modeled in Figure 3 for transmit condition. a) Eight chiplets assembled on an interposer and substrate. b) Thermal simulation using power modeling scenarios.

Figure 5. Roughnesses in conductor formation add to channel loss. This is in particularly important to consider and model for high-speed die-to-die and off-chip communication such as SerDes channels.

processing degrade the channel response [Figure 5]. Channel loss degradation primarily comes from the skin effect as the high-frequency signal is confined to rough outer edges of the conductor and roughness in the line width. With dieto-die signaling approaching >20 GHz line rates, these effects need attention, and good signal propagation through horizontal structure and vertical structure becomes important.

Conclusion Designers of integrated circuits need to deeply understand the complexities of advanced packaging. Packaging engineers, on the other hand, not only need to support tight packing and stacking of dies but also support excellent signal propagation and power distribution while maintaining quality and reliability. Packaging options generally available fall in the two categories of a) side-by-side placement and b) stacking of chiplets based on thermal considerations. Power and thermal modeling is, therefore, the key first step in the design of heterogeneous systems and ICs. Chiplets when available as fully tested flip-chip dies are the easiest to work with. The design

complexity, however, requires modeling of various aspects of the chiplets in a variety of design tools. This is a challenge for designers who need to consider thermal, warpage, signal integrity, and power integrity specifications, in addition to performance. To support such design, chiplet providers need to provide machine-readable models describing mechanical properties, tolerances, electrical properties, thermal properties, logical behavior, testing options, and some more. ◆ References [1] https://spectrum.ieee.org/zglue-aims-tomake-it-cheap-and-easy-to-design-and-manufacture-wearables-and-other-iot-hardware [2] R. J. Drost, R. D. Hopkins and I. E. Sutherland, “Proximity communication,” Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003., 2003, pp. 469472, doi: 10.1109/CICC.2003.1249442.

[3] H. Ishikuro and T. Kuroda, “Wireless proximity interfaces with a pulse-based inductive coupling technique,” in IEEE Communications Magazine, vol. 48, no. 10, pp. 192-199, October 2010, doi: 10.1109/ MCOM.2010.5594696.

[4] https://github.com/zglue/ZEF

FALL 2021 MEPTEC REPORT | 23

INTERVIEW

Catching Up with Zoë Conroy Principal Hardware Engineer Cisco

Owing to a very diverse and accomplished association of MEPTEC members, there are many informative, instructional, and entertaining stories to be told. “Catching Up With…” will feature stories from and about our members.

Zoë Conroy (https://www.linkedin. com/in/zoe-conroy) joined the MEPTEC Advisory Board in 2020. This interview was conducted via email and edited for clarity.

Was there much diversity in the Electrical Engineering program at University of Edinburgh when you were working on your Bachelor of Science and Doctoral degrees? If not, what was the experience as a woman in a male dominated environment? If you could have changed one thing what would it have been?

When I was there, less than 10% of students were female, and probably <5% for PhD. My whole career the ratios have been like this, so you get used to being a minority. Edinburgh is a great place to go to school, the university is over 400 years old and in a beautiful city with lots of history. The university had a microfabrication facility and the B.SC curriculum had a focus on microelectronics, which was very interesting. If I could have changed one thing, it would have been to study medicine instead, but electronics was really the most fascinating for me.

Are there specific things that the industry should be doing to attract greater diversity that you haven’t seen anyone discussing? Are there things that MEPTEC in particular should be doing?

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This is a good question. Many females leave high school with the right credits to study engineering, therefore there should be information available at the college entry level that shows this is a great career. The other area is retention of females who are already in an engineering career. Why do many leave at this point in their career? Employers need to look at their business models and ask themselves why this is happening? Recent worldwide social events have empowered people to recognize microaggressions and have the courage to speak up more about them. MEPTEC could partner with other GSA (Global Semiconductor Alliance) WLI (Women’s Leadership Initiative and IEEE WIE (Women in Engineering), for example, to advertise/share their events.

Wow, your PhD thesis “A VLSI hardware neural accelerator using reduced precision arithmetic” is a hot topic in ultra-low power machine learning these days especially as neural networks are being deployed in very low power microcontrollers and mobile devices at the edge.

When you were working on your PhD was there much discussions about the types of applications we are seeing today?

Professor Alan Murray, my advisor at Edinburgh, was one of the world’s leading researchers in Neural Networks at that time. We were designing arrays of neurons in silicon, then programming them to learn. The focus at that time to was find the most efficient silicon design to enable the biggest array of neurons. We would then program the silicon to recognize patterns. Most of the applications at that time were military. My primary inter-

est was learning chip design, which led me to Wolfson Microelectronics.

What was it like at Wolfson Microelectronics performing the entire integrated circuit (IC) design, verification, and engineering validation of customer devices? How big was the company when you were there and was there explosive growth as this was a very hot area in the 1990’s?

Were they always a fabless company and what were the challenges as being fabless was a new concept then?

Wolfson was a small startup of about 30 people based in Edinburgh where we designed chips for other large companies like HP and Qualcomm. I designed one of the first DTMF (dual tone multi-function) generators chips for Qualcomm. I had two great mentors there who taught me a lot about analog design. And I still use those principles today in doing testing for Cisco’s silicon photonic chip sets.

How did you go from Wolfson Microelectronics in Edinburgh to HewlettPackard in Böblingen Germany?

After three years of designing ICs, I wanted to get more hands on experience working directly on silicon in the lab.

This led me to change jobs and go to HP’s Semiconductor Test Division in Böblingen, Germany, as an application engineer.

There were not many jobs in the United Kingdom for electronics at that time and being part of the European Union then, UK citizens could work anywhere in Europe without a visa. Working at the product division close to the research & development team started my career in meptec.org

automated test equipment (ATE).

And how did you get from Germany to Silicon Valley?

HP was such a global company with many opportunities to move internally.

I was fortunate to relocate to HP Santa Clara Semiconductor Systems Center and then later to the field office on Evelyn Avenue in Mountain View. I was supporting customers like S3, ArtX, Qualcomm, and Nvidia where we got their first applications running on the newly introduced HP 93000 tester.

What were the biggest challenge in helping customers “get up the learning curve” on then state-of-the-art digital testers likes the HP 82000 and HP 83000?

The 82000 was just about end of life, it was never a production system and was used mainly in labs for characterization.

The 83000 was a new tester to the market when I started at HP. Sales were growing rapidly and all customers were new to the system. The need for training and new software features to support new types of chip designs and production were huge.

For example, there was no equation-based timing, no ability to do asynchronous clocking, or differential signals. The way the waveform table interacted with the vector patterns set was a new paradigm shift in setting up timing and waveforms and took a while for engineers to get the hang of. A main advantage of the 83000 platform was its incredible timing accuracy and reliability. I think those have been winners for the platform’s longevity.

At the end of your tenure at HewlettPackard which then become Agilent Technologies, you were focused on supporting new and upcoming fabless companies here in Silicon Valley.

There were lots of ‘unknown’ companies then - some minor and some have really taken off. Any recollections about working with them back in the days when not many knew the concept of fabless supply chain? Any surprises on companies that failed or meptec.org

those that are now power houses in the industry?

I worked in field applications for a few years. This was the coolest job for someone early in career. Company car, free gas card, driving around the valley and flying around the country and world visiting customers and doing pre-sales calls with the sales teams. You were ‘thrown to the lions’ many times with tough technical questions in the pre-sales meetings, with potential new customers not wanting to switch platforms, but knowing they needed to the get the advanced technical and reliability features of the 83000 and 93000 platforms to be successful.

The temptation is always huge to “do the startup thing” in Silicon Valley where hot, new companies are starting all the time. After realizing I had “hit the glass ceiling” at HP, I was enticed to move on.

I spent at least a year supporting a new graphics company called S3. They really drove the start of the fabless model and the fast growth in graphics controllers. They were releasing new revisions of controllers every quarter and really focused on time to market, and fast cost cutting for products in production. They drove some the initial test-house ramp for the 83000 in Asia. Also at that time, HP designed its own processors for its workstations in Fort Collins. They were a fast adopter of the 83000 for processor testing and had many on their test floor there and also at the Inkjet/Printer division in Corvallis. Soon after the S3 rise to power,

a new start-up called Nvidia emerged.

Test engineers from existing companies using the 83000 moved to Nvidia and took adoption of the platform to Nvidia.

It has been interesting to see the rise and fall of graphics controller companies, like S3, ArtX, ATI, and Silicon Graphics and the emergence of Nvidia as a long-term leader.

What was it like moving from HP, a big company, to Procket Networks a small but fast growing networking startup just at the end of the Dot Com bubble in 2000? And what was the jump from being an individual contributor to the manager who owned everything test related?

The temptation is always huge to “do the startup thing” in Silicon Valley where hot, new companies are starting all the time. After realizing I had “hit the glass ceiling” at HP, I was enticed to move to Procket Networks, a new networking company design the next-gen chipset for core routing. My learning growth was huge, moving from helping others to get the tester running at HP to being responsible for releasing production programs and running JEDEC qualifications. I ended up managing a great team of test technical experts, with whom I am still friends today. This was fun, hard work, and a great experience.

Procket was founded by two processor architects from Sun Microsystems and a routing protocol guru from Cisco. The programmability of the networking processors was ahead of its time and brought about a new design concept for routing silicon. The company was desperate to go public. But being in the middle of the industry bubble burst in the early 2000’s, going public was never going to happen.

Various acquisition offers came in, with the final one being from Cisco whose interest was to acquire the design teams to design the next generation silicon and hardware for Cisco’s products.

How did the acquisition and integration of Procket Networks by Cisco go? Cisco is legendary for having built a very robust process for doing FALL 2021 MEPTEC REPORT | 25

INTERVIEW

these acquisitions that they have done for dozens of companies.

to do this are definitely immature or still at the design of experiment phase.

bridge the gap. If these are utilized correctly, they could be quite effective.

Many Procket people did not want to be acquired by Cisco! I always joke that we ‘went kicking and screaming’. Procket was a very close community and at Cisco the Procket engineers got split across various Cisco functions, our product was canned, and we all started working on new Cisco hardware. Cisco has acquired several companies for their silicon technology – Procket was early on, followed by others such as Core Optics, Lightwire, Leaba, Luxtera and Acacia. I have had the pleasure of working with all of these acquisitions – they have provided tremendous strategic technology benefit to Cisco that forms the foundation for future Cisco hardware.

What are the biggest challenges both technically and people wise in your recent roles at Cisco?

You’ve been involved in mentoring and the community in general. Are there specific causes that are of greatest interest to you?

In your roles at Cisco as a Hardware Engineering Manager and Principal Engineer what is some of the groundbreaking work you have done?

Cisco is always on the bleeding edge of new technology. I am in a central Technology and Quality team that constantly comes up with innovations in silicon, packaging, and printed circuit boards (PCB) to support all products. Some of the most notable work I have been responsible for are design for test and test for our internally designed silicon photonics products.

How mature do you think the test and packaging industry is in terms of silicon photonics?

Silicon photonics - actual silicon to generate or manage the photonics - in optical modules has been shipping in volume for several years. The technology is always pushing for higher levels of integration, lower power, and higher bandwidths which constantly challenges today’s packaging and assembly technology. Therefore, I would say while the older technologies and ways to do photonic modulation are mature the need for cheaper and lower power modules is increasing rapidly with datacenter growth. And the new and innovative ways 26 | MEPTEC REPORT

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The biggest challenges are bringing new innovations to high volume manufacturing in the fastest possible time to market.

From efficient testing, passing reliability tests, and working with suppliers and contract manufacturers remotely to ramp new products.

From past discussions and presentation you’ve made, you have done a lot of work trying to correlate test at the system level (sometimes run by the product operating system) all the way down to the individual semiconductor devices. This is clearly a non-trivial task so what does it really take to make this work? Are there any key insights that the industry needs to learn to make this more practical?

How does this improve the overall product quality?

This is an interesting and ongoing problem. As I mentioned I worked at HP on the 83000 and 93000 testers, therefore I understand ATE test hardware and test development ATE coverage, ATPG tests, memory built-in self-test (MBIST), and built-in self-test (BIST) in general. I previously believed ATE testers and silicon design for test (DFT) was good enough until I worked at Cisco. However, at Cisco I regularly see first-hand structural (ATE) to functional (system level) test gaps. The main reason is that in the end application, especially for networking products, high bandwidth data traffic exercises the chip is a very different way from ATPG tests.

The higher structural test coverage is (dc scan, ac scan (transition fault and path delay) and programmable MBIST), the lower system device defects per million (DDPM) failure rate. However, teasing out the last few uncovered defects is difficult. Traffic patterns do not run easily on ATE so some type of system level test is needed. There is a lot of industry interest in adding more sensors to silicon to

I have spent quite a bit of time volunteering at my children’s schools, on the parent teach association (PTA), running events, fundraising, and assisting in the classroom. More recently I have become an AVID (Advancement Via Individual Determination) mentor for high school students. Much of this involves helping with college applications. We meet weekly with students in the program for 1-2 years. Getting to know the students and helping them is very rewarding work.

Please talk about what the Krause Center for Innovation does, your role on the advisory board, and why it is important.

The Krause Center of Innovation at Foothill College focuses on advanced professional learning for teachers. Part of it involves using new technology in the classroom, and I have been honored to be on the board on behalf of Cisco.

What have you learned during the pandemic lock down and work from home in terms of managing and productivity? Anything you would change in hindsight?

I have to give kudos to Cisco, as a networking company our transition to work from home was seamless. With tools like Webex and already being a global workforce where many of us took early and late meetings from home, we were well prepared. I would say productivity is the same, but I miss the live face to face interaction with colleagues. Everyone has a different personal situation and story during the pandemic. For myself, I was multitasking home-schooling a child and work meetings. The upside is that I learned many interesting things about world history and biology and we read some really good books. ◆ meptec.org

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