MEPTEC Report Spring 2021

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

Volume 25, Number 1

ONL I N E E V E N T A P R I L 2 8 & 2 9, 2021

Supply Chain Security page 21

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Challenges of Advanced High-Speed Digital Product Test page 13

PVT Aware Production Testing page 18

Interview - Catching Up with Herb Reiter

50 Years in the Semiconductor Industry and Over a Dozen Major Lessons Learned

page 23

INSIDE THIS ISSUE

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UP FRONT Hello 2021–The weather has turned warmer, so we are definitely in full on spring mode.

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CALL TO ACTION Measures can be taken by government and industry to avoid a sudden shortage of mission critical FPGA components.

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MEMBER NEWS from Delphon, Amkor, Aehr Test Systems, Intel, Disco, Namics, Integra and more.

COUPLING & CROSSTALK As more truly smart devices are deployed at the edge, greater independence and privacy become achievable.

SPRING 2021

MEPTECReport

UP FRONT The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council 141 Hewitt Street, Summerville, SC 29486 Tel: (650) 714-1570 Email: bcooper@meptec.org Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown Sales Manager Gina Edwards

MEPTEC Executive Director Ira Feldman

MEPTEC Advisory Board Board Members Dave Armstrong Advantest Ivor Barber AMD Calvin Cheung ASE (US) Inc. Jeff Demmin Keysight Technologies Abram Detofsky Intel Neal Edwards AMD Jaspreet Gandhi Xilinx Ravi Mahajan Intel Emeritus Advisors Seth Alavi Sunsil Joel Camarda Anna Gualtieri Elle Technology Phil Marcoux PPM Associates Mary Olsson Herb Reiter eda 2 asic Consulting, Inc., Retired In Memoriam Ron Jones

Contributors Adam Cron Synopsys Stephen Crosher Synopsys Ira Feldman Feldman Engineering Corp.

Martin Hart TopLine Corporation Vineet Pancholi Amkor Technology, Inc. Herb Reiter eda 2 asic Consulting, Inc., Retired

MEPTEC Report Vol. 25, No. 1. Published quarterly by MEPCOM LLC, 141 Hewitt Street, Summerville, SC 29486. Copyright 2021 by MEPCOM LLC. All rights reserved. Materials may not be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members of MEPTEC. For nonmembers, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere.

For advertising rates and information contact Gina Edwards at 408-858-5493.

Hello 2021 – Spring Ahead!

Ira Feldman Executive Director, MEPTEC

Last week we performed the semiannual ritual of changing our clocks to “spring ahead” for Daylight Savings Time. And the weather has turned warmer here in Silicon Valley. So, we are definitely in full on spring mode. Not to mention progress in the rollout of vaccines and lowering infection rates is improving the mood here.

E. Jan Vardaman of TechSearch International kick-started the year with “Outlook for 2021: Are There Supply Limitations to Growth?” as the first Semiconductor Industry Speaker Series (SISS) speaker of the year in January. This was quickly followed by excellent presentations by Carl Zweben (Advanced Thermal Materials and Composites Consultants), Bharath Muthiah & Ravi Agarwal (Facebook), and John Park (Cadence Design Systems). If you missed any of these, you will find the slides and recordings on our website (www. meptec.org). There are plenty more presentations queued up for the SISS hosted semi-monthly by MEPTEC and IMAPS. In February, we also hosted a new virtual event Too Hot to Test. There were three days of great technical presentations addressing the test challenges including power delivery and thermal cooling of leading-edge advanced computing devices. We examined the issues that are “heating up” during test as devices are becoming larger from the test, packaging, and design perspectives. Slides and videos are available at events.meptec.org.

Our next event on April 28 & 29 is focused on Supply Chain Security. This free virtual workshop will address the cross-functional issues facing packaging, test, and design engineers to ensure what is delivered contains the properly functioning device and nothing more. Not only are electronic systems becoming more complex, chiplets and other advanced packaging are creating potential security issues with new “attack vectors”. See the confirmed speakers at events. meptec.org and register today to participate.

Lastly, a little left-over business from 2020. MEPTEC is a member and corporate sponsor supported organization. If you have not already joined or renewed for the year, please do so now. If your company is interested in sponsoring our programs, please let us know as corporate sponsorships allow us to provide all of these virtual events free of charge. For assistance with membership or sponsorships please contact Bette Cooper (bcooper@meptec.org).

Let’s make 2021 an even better year for everyone. Do share your suggestions and feedback as to how MEPTEC can best serve you. And don’t be shy!

Stay safe and healthy!

Ira Feldman Executive Director, MEPTEC ira@meptec.org +1 650-472-1192

SPRING 2021 MEPTEC REPORT | 3

CALL TO ACTION

Does the FPGA Industry Face Peril? Pt. VII Martin Hart TopLine Corporation

PART VI OF THE WINTER 2020 MEPTEC Report titled “Call to Action” cited a potential risk to product line continuation of defense grade and radiation hardened (RADHARD) FPGA devices after the acquisition of XILINX by AMD. Also cited is the dependency of the FPGA device supply chain that relies on a single source subcontractor during the final assembly step involving solder column attachment.

Sustainability and manufacturing resiliency of defense grade and RADHARD FPGA devices are vital for the National Security of the United States and its allies. Peace in the new World Order may depend on strength and our readiness to respond to threats. FPGA devices are vital components that are ubiquitous inside black boxes that keep defense systems operational and warfighters flying.

A sudden surge in demand for ruggedized FPGA devices can quickly exceed the industry’s capacity to meet such demand.

Likewise, an unplanned disruption in manufacturing capability can bring the supply chain to its knees while customers wait for deliveries that never come. Today, nine of America’s largest device makers that manufacture defense grade FPGA components rely on a single subcontractor to attach copper wrapped solder columns as the final production step in the manufacture of rugged FPGA components.

Break in the Supply Chain Industry veterans still woefully remember the painful impact on the FPGA supply chain in 2013 when IBM declared their intention to exit the ceramic column grid array (CCGA) business that houses ruggedized FPGA chips. IBM was the primary fabricator for many fabless makers of FPGA devices, most notably Xilinx. After IBM issued an end-of-life notification, their entire world-class column attachment production line was summarily crated-up and sat idle for 5 years 4 | MEPTEC REPORT

SPRING 2021

before being put back into service by a licensee. After considerable consternation, Xilinx moved production of rugged FPGA packages to Kyocera and selected a sole-source subcontractor, known as Six-Sigma, to perform column attachment services. XILINX, who was recently acquired by AMD, provides roughly half of the Free World’s defense grade and RADHARD FPGA devices for aerospace.

The defense industry remains vulnerable today should this said subcontractor suddenly discontinue operations or fail to meet a surge in demand. The industry is wary that a natural disaster, such as an earthquake or fire, can debilitate a single-source supplier. Also of concern is business continuation due to the loss of a key manager caused by death or retirement. Potentially, an acquisition of a solesupplier, even by a non-hostile entity can suddenly cause a disruption in the supply chain.

Diminishing Supplier Base A diminishing supplier base is of ongoing concern in the semiconductor industry. The U.S. Department of Defense (DOD) provides guidelines to identify and mitigate dependency on services provide by single-source subcontractors. A useful document SD-22 titled, “Diminishing Manufacturing Sources and Material Shortages (DMSMS), a Guidebook of Best Practices for Implementing a Robust DMSMS Management Program” sets forth resources to aid FPGA makers striving to broaden their supplier base for components that are critical to the welfare of National Security.

Delays to Qualify Alternative Subcontractors for Column Attachment Services Even under optimum circumstances, it might take over two years for the most able alternative column attachment subcontractor to traverse though the demand-

Example of Column Grid Array (CCGA) Package for FPGA device.

ing certification process by the Defense Logistic Agency (DLA), an arm of the DOD. In March 2020, travel by DLA employees to conduct facility audits was shelved, due to COVID-19 restrictions.

As of the date of the publication of this article, DLA has not resumed travel to conduct QML-38535 audits and to certify subcontractors.

Summary Solder column attachment is very much the “Achilles Heel” in the assembly process of defense grade FPGA devices.

A series of unplanned crises involving column attachment services can bring the entire FPGA industry to a halt. Fortunately, alternative subcontractors already exist and are ready, willing and able to attach solder columns. VPT Components and Micross Components have ample experience attaching TopLine-made solder columns. Other subcontractors, including Silitronics and Golden Altos, are developing plans to provide column attachment services in the future. A prudent approach is for FPGA device makers to qualify alternative subcontractors to attach solder columns now, rather than wait for disaster to strike.

Conclusion Measures can be taken by government and industry to avoid a sudden shortage of mission critical FPGA components to keep warfighters flying. Affirmative steps should be initiated now to elevate the priority in securing and qualifying a second source capability to attach solder columns sooner, rather than later. ◆ meptec.org

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MEMBER NEWS

Completion of New Building Construction at Nagano Works Chino Plant

DISCO CORPORATION has completed construction of a new seismically isolated building (Building B) at Nagano Works Chino Plant (Chino City, Nagano).

With completion, the total floor area of the new plant, including the existing building, is approximately 7.5 times greater. This expansion enables further enhancement of the product supply system for future demand in semiconductors and electronic components.

Due to widespread use of high-performance smartphones and increase in base stations and data centers

accompanying the start of 5G service, demand for semiconductors and electronic components, including memory, sensors, and condensers, is increasing worldwide. As a result, need is also rising for DISCO’s precision processing equipment and precision processing tools (blades/ wheels) among device manufacturers, semiconductor manufacturing subcontractors, and electronic component manufacturers. Demand is expected to expand midto-long term as well, with future technologies such as IoT, AI, self-driving technology, and telemedicine as

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DELPHON APPOINTS JOSEPH MONTANO AS PRESIDENT

drivers of growth. Therefore, DISCO needed to further enhance its product supply system.

Production floors in the existing building (Building A) are operating at almost full capacity. The new expansion enables flexibility in adapting to further increase in demand. In addition, construction of another new building (total floor area: approximately 67,800 m²) is in progress at Hiroshima Works Kuwabata Plant (Kure City, Hiroshima) and will be completed in August 2021.

For more information visit www.disco.co.jp. ◆

NAMICS New Adhesive Enables Next-Generation, Flexible Hybrid Electronics NAMICS HAS ANNOUNCED THEIR newest product, H9230D, a stretchable conductive adhesive. This new material is designed for flexible hybrid electronics – a new and exciting area in electronics which boasts both flexibility of lightweight and thin circuit boards, as well as the processing power of semiconductors.

H9230D is a new stretchable, conductive adhesive that is used to mount rigid components onto flexible hybrid substrates while providing an electrically conductive path. H9230D was designed for attaching components such as LEDs, capacitors, and small chips to flexible meptec.org

substrates. New component attachment materials are needed for flexible electronic devices which, because they are mounted on soft, flexible substrates, and require materials to be ductile.

H9230D provides an ideal alternative to solder for FHE applications. While adhesives must be cured, the temperature requirements for affixing conductive adhesives are much lower than they are for soldering.

To learn more about NAMICS, stretchable inks, and how we can become your innovation partner visit https://namicsusa.com/. ◆

DELPHON has announced the appointment of Joseph Montano as President.

Reporting directly to CEO Jeanne Beacham, Joe will serve a critical role in the company’s leadership team as Delphon continues to grow through new product innovations and future acquisitions. Joe has spent more than 25 years in the electronics and electronic materials technology segments. He has an extensive technical and commercial background, with experience spanning from the R&D bench to executive management. www.delphon.com

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AMKOR FACTORY INTELLIGENCE ENABLES INDUSTRY 4.0

AMKOR TECHNOLOGY has recently unveiled new measures that help the company achieve Industry 4.0 initiatives, extending its leadership in quality and efficiency excellence. Leveraging artificial intelligence, machine learning and interconnected systems, Industry 4.0 challenges companies to surpass factory automation and achieve factory intelligence. Amkor now uses real-time, inprocess decision making to drive gains in quality, asset utilization and efficiency.

The application of Industry 4.0-era tools reduces cycle times for advanced packaging processing. Since implementing Industry 4.0 initiatives, Amkor has seen a 60% improvement in productivity for process engineers from EDA, and Fault Detection & Classification (FDC) will enable real-time quality control. www.amkor.com

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SPRING 2021 MEPTEC REPORT | 5

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MEMBER NEWS 

AEHR RECEIVES $1.2 MILLION ORDER FOR MULTIPLE WAFERPAKS™

AEHR TEST SYSTEMS has announced it has received a $1.2 million order for multiple WaferPak™ Contactors from one of its lead FOX-XP test and burn-in system customers for their installed base of FOX multiwafer test systems. The orders are for increased volume of production test of the customer’s silicon photonics devices for data center-oriented fiber optic support. The WaferPaks are expected to ship over the next quarter. www.aehr.com

 INTEL INVESTS

ADDITIONAL $475 MILLION IN VIETNAM

INTEL CORPORATION has announced it has invested a further US$475 million in Intel Products Vietnam (IPV). This new investment is in addition to Intel’s US$1 billion investment to build a state-of-the-art chip assembly and test manufacturing facility in Saigon Hi-Tech Park (SHTP), first announced in 2006. This takes Intel’s total investment in its Vietnam facility to US$1.5 billion.

Intel Products Vietnam is an important part of Intel’s worldwide manufacturing presence. As Intel redefines its position in the industry from a CPU to a multi-architecture XPU company, IPV will continue to diversify and improve its local operations so that it can take on more complex technologies and new products to enable Intel to tap new market opportunities. IPV has more than 2,700 employees and serves customers around the world. www.intel.com

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6 | MEPTEC REPORT

Intel, DARPA Develop Secure Structured ASIC Chips Made in the U.S.

Intel’s newest, leading-edge manufacturing facility is Fab 42 in Ocotillo, Arizona. Fab 42 connects to three other Intel fabrication plants, making the site Intel’s first mega-factory network. (Credit: Intel Corporation)

INTEL AND THE U.S. DEFENSE ADVANCED Research Projects Agency (DARPA) have announced a three-year partnership to advance the development of domestically manufactured structured Application Specific Integrated Circuit (ASIC) platforms. The Structured Array Hardware for Automatically Realized Applications (SAHARA) partnership enables the design of custom chips that include state-of-the-art security countermeasure technologies. A reliable, secure, domestic source of leading-edge semiconductors remains critical to the U.S. “We are combining our most advanced Intel® eASIC structured ASIC technology with stateof-the-art data interface chiplets and enhanced security protection, and it’s all being made within the U.S. from beginning to end. This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10nm semiconductor process,” said José Roberto Alvarez, senior director, CTO Office, Intel Programmable Solutions Group.

As the sole U.S.-based advanced semiconductor manufacturer, Intel promotes supply-chain security by utilizing facilities within the U.S. to

manufacture, assemble and test custom chips for the SAHARA partnership.

“Structured ASICs have advantages over FPGAs that are widely used in many Department of Defense applications. In partnering with Intel on the SAHARA program, DARPA aims to transform currently fielded as well as future capabilities into structured ASIC implementations with significantly higher performance and lower power consumption,” said Serge Leef, a program manager in DARPA’s Microsystems Technology Office.

“SAHARA aims to dramatically shorten the ASIC design process through automation while adding unique security features to support manufacturing of the resulting silicon in zero-trust environments.

Additionally, Intel will establish domestic manufacturing capabilities for the structured ASICs on their 10nm process.”

Intel® eASIC™ devices are structured ASICs, an intermediary technology between field-programmable gate arrays (FPGAs) and standard-cell ASICs. These devices provide lower unit-cost and run on lower power compared with FPGAs and provide a faster time to market and lower non-recurring engineering cost compared with standard-cell ASICs. ◆

Deca Collaborates with ASE and Siemens to launch APDK™ DECA HAS ANNOUNCED the introduction of its new APDK™ (Adaptive Patterning® Design Kit) methodology. The solution is the result of Deca’s collaboration with Advanced Semiconductor Engineering, Inc. (ASE) and Siemens Digital Industries Software.

Deca’s tight collaboration with ASE, and the Calibre® platform from Siemens, allows

SPRING 2021

end customers to realize the power of Adaptive Patterning.

While achieving breakthrough electrical performance, all corners of advanced heterogeneous integration designs are now assured to fall within manufacturing capabilities.

Each APDK bundles the full set of automation, design rules, DRC decks, and templates into a single package,

offering a turn-key design flow. Every design is jumpstarted by a library of templates, while extensive automation guides the designer from initial layout to Adaptive Patterning simulation, and finally through design signoff using Siemens’ Calibre software.

For more information, visit www.ThinkDeca.com. ◆ meptec.org

USI Launches PCIe Gen.4 2U24 Highly Scalable All-flash Array Product for High-performance Storage Market Following the successful launch of SAS storage arrays, USI is now offering the all-flash array product using the PCIe Gen.4 technology.

USI’s all-flash array product is designed to achieve low latency and high performance that boost storage capacity. Its features include an energy-saving compact 2U enclosure, 24 2.5-inch U.2 drive positions, NVMe dual channels and managed/unmanaged hot-plugging support. It also supports dual node hot-pluggable I/O control cards, with a 32 lane PCIe Gen4.0 interface in each node. In addition, it has a 1,300W hot-pluggable redundant power supply, a 3.5-inch LCD display allowing on-site management, a BMC remote management interface, a gigabit Ethernet interface and configurable external port modules.

USI’s all-flash array’s open software architecture is conducive to customers’ system integration and subsequent development in dynamic configuration and SSD partitioning and combination adjustments according to the PCIe topology.

Visit https://www.usiglobal.com for more information. ◆

Integra Technologies Expands Silicon Photonics Capabilities INTEGRA TECHNOLOGIES, a world leader in semiconductor packaging, assembly, test, characterization and related services, has announced the successful implementation of a high accuracy fiber array waveguide attachment system focused on the Silicon Photonics market. This latest set of tools is based on the doublesided HexNano Alignment System from Physik Instrumente L.P. (PI).

Shortly after the implementation, Integra was able to successfully support numerous customers and products with their fiber attach requirements.

Integra Technologies made the investment in this and other silicon photonics equipment to support a market that accounted for $0.8 billion in 2019 and is expected to reach $3.77 billion by 2027. Some of the key factors propelling the growth of the market are increasing demand for highspeed broadband services, deployment of 5G technologies in developing nations, and growing demand for CMOSintegrated silicon photonics meptec.org

technology. Photonic devices contain optical systems that use silicon as the optical medium. Since silicon is used as a substrate for most ICs, the manufacturing of hybrid devices, in which electronic as well as optical components are integrated onto a single microchip, becomes more streamlined and standardized.

Silicon photonics is increasingly used in the data transfer between microchips, through optical rays. Moreover, they are capable of carrying a large amount of data in a shorter amount of time compared to traditional electrical conductors.

For more information, please visit https://www. integra-tech.com/. ◆

Rare Open-Access Quantum Computer Now Operational at Sandia National Labs

ALBUQUERQUE, NM — A NEW Department of Energy open-access quantum computing testbed is ready for the public. Scientists from Indiana University recently became the first team to begin using Sandia National Laboratories’ Quantum Scientific Computing Open User Testbed, or QSCOUT. Sandia National Laboratories physicist Susan Clark leads the team that built the Quantum Scientific Computing Open User Testbed. The ion-based quantum computer was made for outside researchers to use.

Quantum computers are poised to become major technological drivers over the coming decades. But to get there, scientists need to experiment with quantum machines that relatively few universities or companies have. Now, scientists can use Sandia’s QSCOUT for research that might not be possible at their home institutions, without the cost or restrictions of using a commercial testbed.

“QSCOUT serves a need in the quantum community by giving users the controls to study the machine itself, which aren’t yet available in commercial quantum computing systems. It also saves theorists and scientists from the trouble of building their own machines. We hope to gain new insights into quantum performance and architecture as well as solve problems that require quantum computation,” said Sandia physicist and QSCOUT lead Susan Clark.

Last month, Sandia began running the testbed’s first user experiment for scientists from Indiana University. Researchers from IBM, Oak Ridge National Laboratory, the University of New Mexico, have also been selected to begin experiments soon.

QSCOUT resides at Sandia’s Microsystems Engineering, Science, and Applications complex, which also produces microelectronics for the nation’s nuclear stockpile. ◆ 8 | MEPTEC REPORT

SPRING 2021

Infineon’s New Wi-Fi 6 Solutions Bring Reliable, High Performance Connectivity to Smart Homes

DIGITALIZATION IS ACCELERATING in all areas of life. From home entertainment to health tech to in-car entertainment, the number of connected consumer devices used in homes or on-the-go continues to accelerate, increasing the demand for wireless connectivity. With the new AIROC™ Wi-Fi 6/6E and Bluetooth® 5.2 product series, Infineon Technologies AG is responding to consumers’ demand for secured and convenient wireless connectivity and helping to reduce congestion of home networks.

“In view of the accelerated growth of connected consumer devices in smart homes, Wi-Fi 6 has the power to enable robust and reliable data connections and the best user experience,” said Thomas Rosteck, president of Infineon’s division Connected Secure Systems. “Infineon empowers device manufacturers to easily develop smart and trusted solutions that make IoT work: from sensors and microcontrollers to power to secured connectivity and software – we now provide all required components from one source.”

Wi-Fi 6, the latest generation of Wi-Fi to hit the market, is specifically built to improve reliability and performance, even in high device density environments.

Driven by the Covid-19 pandemic, more and more people are increasingly working, studying and entertaining at home. Online gaming devices with virtual reality capabilities, sports devices that stream workouts live or connected kitchen gadgets are

increasingly congesting the home network environment.

Unlike previous generations of Wi-Fi that focused on peak device speeds, Wi-Fi 6 includes advancements to relieve network congestion, and to improve network efficiency, device battery life, latency and range in addition to peak speeds.

Building on the success of previous generations of Wi-Fi and the advancements brought by Wi-Fi 6/6E, the Wi-Fi Alliance® predicts that Wi-Fi will add five trillion US-dollars to the global economy by 2025.

Infineon’s AIROC™ series of wireless connectivity components Infineon is expanding its AIROC wireless portfolio of high-performance, reliable and secured offerings with combined Wi-Fi 6/6E and Bluetooth 5.2 combo capabilities.

The AIROC Wi-Fi 6/6E combo solutions operate in the 2.4 GHz, 5 GHz, and the newest, greenfield 6 GHz spectrum to deliver robust performance and minimal latency, making them ideal for high-quality video and audio streaming applications like game consoles, AR/VR, smart speakers, media-streaming devices, and automotive Infotainment. Applications that require instant response – such as security systems and industrial automation – will also benefit from Infineon’s new products.

Further information about the Internet of Thins is available at: https://www.infineon.com/cms/en/about-infineon/make-iotwork/. ◆ meptec.org

Xilinx Collaborates with Fujitsu to Support 5G Deployments in the U.S. XILINX, INC. HAS ANNOUNCED THAT the company is supplying its leading UltraScale+ technology to Fujitsu Limited for its O-RAN 5G radio units (O-RUs). Fujitsu O-RUs using Xilinx technology will be deployed in the first O-RAN-compliant 5G greenfield networks in the U.S. Fujitsu is also evaluating Xilinx RFSoC technology to further reduce cost and power consumption for additional future site deployments.

Fujitsu O-RUs are ideal for a broadrange of spectrum and multi-band applications for 5G O-RAN networks. The Xilinx UltraScale+ devices used within Fujitsu O-RUs deliver the best balance of cost economies as well as the adaptability and scalability required for the evolving needs of 5G O-RAN network requirements.

Additionally, Xilinx will continue to work with other O-RAN ecosystem partners to ensure continued validation of the hardware and software necessary for worldclass 5G networks.

“We are proud to collaborate with Fujitsu in the development of their multigeneration 5G radio units using our industry-leading UltraScale+ solutions, which

EPOXY for Chip

Coating & Glob Top Applications

will be deployed in a major greenfield 5G network,” said Liam Madden, executive vice president and general manager, Wired and Wireless Group at Xilinx. “As the market needs for 5G continue to evolve, Fujitsu also recognized the importance of integrating Xilinx adaptable RFSoCs to address the evolution of standards for nextgeneration radio deployments.”

“Our Fujitsu design team worked closely with Xilinx on our O-RAN radio units to enable greater flexibility and cost savings while also delivering greater innovation as well as new capabilities for 5G networks,” said Masaki Taniguchi, senior vice president and head of the Mobile System Business Unit at Fujitsu. “Together, Xilinx’s UltraScale+ portfolio of solutions with Fujitsu’s leading radio platforms deliver a solid foundation for enabling the great benefits of O-RAN that are central to 5G deployments. We look forward to continuing our collaborative efforts with Xilinx to integrate its RFSoC family into our next-generation solutions.”

The first greenfield 5G O-RAN systems will be deployed this year. For more infor-

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mation about Xilinx’s wireless 5G O-RAN solutions, visit: https://www.xilinx.com/ applications/wired-wireless/wireless.html Follow Xilinx on Twitter, LinkedIn, and Facebook.

Xilinx, Inc. develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies - from the cloud, to the edge, to the endpoint. Xilinx is the inventor of the FPGA and Adaptive SoCs (including our Adaptive Compute Acceleration Platform, or ACAP), designed to deliver the most dynamic computing technology in the industry. We collaborate with our customers to create scalable, differentiated and intelligent solutions that enable the adaptable, intelligent and connected world of the future.

For more information visit xilinx.com. ◆

Conference: November 1 - 4 Exposition: November 3 - 4 Virtual Event Begins November 15 Minneapolis, Minnesota, USA *Co-located with:

2021 CALL FOR

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Become a part of the industry’s strongest technical program addressing all aspects of electronics manufacturing. Plan to present in-person or virtually at the annual SMTA International Conference. Full technical paper is required for inclusion in the published proceedings.

Proposals are also being solicited from individuals interested in teaching professional development courses related to surface mount technology, advanced packaging, and electronics manufacturing.

Due Date: May 1, 2021

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COLUMN COUPLING & CROSSTALK

By Ira Feldman Electronic coupling is the transfer of energy from one circuit or medium to another.

Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought-provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Gathering Storm Clouds!

“The Cloud” sounds fluffy, amorphous, and fast moving. Like those who see different shapes in the clouds, The Cloud means different things to different viewers.

However, in addition to beautiful days, clouds can deliver thunder, lightning, and rainstorms which are dangers just like the ones from The Cloud often not foreseen by users – technology novices and experts alike. As users we should be in control of how our devices use The Cloud for our benefit. Metaphors and semantics are important, but very simply we should not let marketing images obscure the true dangers and limitations of The Cloud and our ability to choose when, what, and where information is best processed.

Why worry now? Especially since some organizations have been using cloud computing since the early 2000’s? With the explosion in the number of Internet of Things (IoT) devices and the accelerating rate of adoption, the potential for unintentional or deliberate harm increases.

Many users have no understanding of how smartphones and other IoT devices work from a computing standpoint including how much these devices rely on The Cloud for processing and data storage let alone knowledge of the associated risks. And coupled with this are “suppliers” of hardware, software, and web platforms who take short cuts on product security. (Even the hyperscale giants!)

What are the solutions? Like putting the proverbial genie back in the bottle, it is far too late to eliminate The Cloud. There are many benefits of ubiquitous computing – everything from mobile access from meptec.org

anywhere to not managing one’s own information technology (IT) hardware infrastructure to the connectedness to others. And governments have not succeeded in regulating most aspects of the Internet in meaningful ways out of ignorance, a desire not to break it, corporate lobbying, or a combination of all of these.

Complicating this: things are simply “different” with The Cloud as we try to map physical concepts to the virtual world.

Did you know when you “buy” a movie on most of the digital platforms, you are really “renting” it for an indefinite period of time? You’ll see complaints from people who bought movies only to find out they can no longer be watched due to licensing or other restrictions.

As more truly smart devices are deployed at the edge, greater independence and privacy become achievable.

Because everyday things become different and more complex while cloud companies focus on doing what is in their best interest – not necessarily the same as their customers’ – and regulations are ineffective; what does that leave for solutions? Avoiding The Cloud may simply be impossible unless you can give up all of your computers, laptops, smartphones, and countless other devices… Did you say: No! Not my Nest thermostat or my WiFi enabled coffee pot!?

Practical solutions are based upon smarter users and smarter devices. As a consumer and a professional who develops, builds, and uses business processes, I like to consider only what data is required to provide the desired functionality. This may ultimately be more important than the desired functionality, especially if the cost or risk of providing the data exceeds its value.

Recently I was requested to pay athletic fees to one of my son’s coaches via a “cash

app”. Well, obviously the app would need my banking information which I wasn’t too keen to share… Even before the app setup asked for banking information, it was insisting that it have full access to the over six-thousand contacts in my address book on my smartphone. At that point it was “no way”! I deleted the app without finishing the setup and simply wrote the coach a check. The risk of the app sending “join Ira in using this terrific app” emails or even worse leaking my banking information to everyone far exceeded the convenience promised by the app.

Beyond education and helping users to make smarter decisions, new products are increasing the intelligence “at the Edge” of The Cloud. As devices become more capable through increased hardware performance and more efficient algorithms and software, computation activity is moving from the data center to the device itself.

This transition is not only making these devices at the edge more intelligent it is enabling privacy, autonomy, and lower power consumption. Devices are not just smartphones but include application specific hardware like thermostats, televisions, video doorbells, door locks, automobiles, and “intelligence modules” for traditional whitegoods (refrigerator, stove, washer, dryer, etc.) – i.e. the entire Internet of Things (IoT).

Many early IoT devices rely entirely on the computation power of The Cloud to enable the end application. These early IoT devices might have sensors such as sound, temperature, light, vision, etc. which send the raw data to The Cloud to apply the “smarts”. Voice commands such as “Hey Siri” or “Hey Google” on our phones and other devices originally sent all the voice data to The Cloud to do the processing.

The latest smartphones are processing more of the speech data themselves but still need to connect to The Cloud to process speech that is outside of the simplified models on your smartphone and to access other services like searching the web.

A self-contained sensor detecting how many people are in a room to predictively adjust the heating and ventilation system (HVAC) is not just possible but a practical example of such an edge device. Last month at the tinyML Summit (www. tinyml.org), organized by Bette Cooper, myself, and others who are also involved with MEPTEC, not only was this example used but the “building blocks” of it were demonstrated. The approach shown uses a camera with a vision processing neural SPRING 2021 MEPTEC REPORT | 11

COLUMN network to count the number of people in the room. This neural network can be run on the sensor unit and does not require the video be sent to The Cloud for processing.

Building the smarts at the edge in this example has multiple advantages: • Privacy – the sensor only needs to report the number of people found in the room to the HVAC controller. It does not store or otherwise send a video to The Cloud in which individual people may be identifiable.

• Autonomy – the sensor can provide the data required by the heater or air conditioner without an internet connection and without the time delay it would take to transmit one or more frames of video to The Cloud for processing and wait for the response.

• Power Efficiency – single or multiple frames of video contain many orders of magnitude, more data than a single number. And energy consumption per unit (bit or byte) increases with the distance and speed over which they need to be transmitted. This is true within the device itself (between the processor and memory for example) and between the sensor and The

Cloud. By drastically reducing the power consumed for each count, the count can be performed more often and/or if power usage is low enough, a battery-operated sensor becomes practical. A battery-operated sensor also enables new usage configurations like placing the sensor with the camera and the thermometer further away from the air conditioner resulting in more accurate room temperature control.

The goal of the tinyML Foundation, which organizes the tinyML Summit and other related events and activities, is to enable ultra-low power machine learning at the edge. What is unique is that the community engagement and technology discussion is “full stack”- from the semiconductor device design, packaging, and manufacturing all the way through the application software and data models.

Without this end-to-end approach building devices with the performance and efficiency required is simply not possible. What good is optimizing your neural networks if they don’t fit on the hardware architecture?

Or why double the amount of memory on the device when you can half it by adjust-

ing the quantization of the data? Clearly cross-functional approaches are required to build these challenging applications and systems.

As more truly smart devices are deployed at the edge, greater independence and privacy become achievable. Not only from The Cloud itself but by enabling fully autonomous devices including vehicles like drones and self-driving cars. To achieve these “smarts” at the edge it is essential to pay attention to the entire product lifecycle – from design to manufacturing to software to support. Lassoing any cloud is difficult - ”The Cloud” more so. If your team does not have the vision or big picture perspective to do so, be sure to reach out to consulting firms and independent specialists with the necessary experience and expertise.

For more of my thoughts, please see my blog http://hightechbizdev.com.

As always, I look forward to hearing your comments directly. Please contact me to discuss your thoughts or if I can be of any assistance. ◆

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TECHNOLOGY

Challenges of Advanced High-Speed Digital Product Test Vineet Pancholi, Sr Director, Test Technology Amkor Technology, Inc.

AS DIGITAL SEMICONDUCTOR devices have become more powerful and the number of devices per system have grown, there is an increased need to move larger amounts of data at higher speeds between the devices and the external world. This has led to an explosion in the number and types of highspeed digital serial interfaces. In addition, all popular high-speed digital serial interface standards have increasing data rate roadmaps. As each new generation of these interfaces have ever increasing performance and functionality, they pose significant test challenges.

These high-speed digital serial interfaces for logical processors include Peripheral Component Interconnect Express (PCI Express or PCIe), Ethernet, Interlaken, Display Serial Interface (DSI), MIPI DigRF (M-PHY, D-PHY, C-PHY), Thunderbolt and others.

Another important digital interface for processors is JEDEC’s Wide I/O volatile memory controller interface. Logic processors are employed in a variety of applications which include but are not limited to computer processors, network processors, graphics processors, artificial intelligence (AI) processors, applications processors found on mobile devices and embedded processors found in applications like point-of-sale systems. PCIe is by far the most popular high-speed digital serial test interface for inter-IC communications. The PCIe standard allows the single root complex processor to send and receive data to multiple peripheral component end points [1]. With the everincreasing demand for faster and faster compute capabilities, the need to transmit and receive data between the processor and peripherals within the application has increased as well. PCIe data rates have increased with every release generation, 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps and meptec.org

FIVR Input Voltage Rails Ethernet Tx P/N [0,1]

Interlaken Tx P/N [0,15]

Ethernet Rx P/N [0,1]

Interlaken Rx P/N [0,15]

VREF Display Tx P/N Pure Clock (100 MHz) D+

Display Rx P/N

Processor (DUT)

Pure Clock (100 MHz) D-

PCIe Rx P/N [0,3]

Slow Speed Serial I2C. SPI. UART JTAG TAP

USB3 Tx P/N [0,3]

DDQ Bus 64 Bit I/O [0,1]

USB3 Rx P/N [0,3]

DDQ Strobe Bus

PCIe Tx P/N [0,3]

DUT Ground

Figure 1. High-level block diagram and interfaces including fully integrated voltage regulator (FIVR) input.

are expected to hit 32 Gbps in the not-sodistant future. Similar increases in data rates have also been observed for nonPCIe high-speed digital serial interfaces.

Recently, USB3.x and Thunderbolt with their higher data rates have gained popularity for externally pluggable power, storage and display peripherals to the application platform. Figure 1 shows an example of possible processor outputs.

None of these high-speed serial digital interfaces full signal chains are functionally tested in production at their native data rate with a matching automatic test equipment (ATE) digital instrumentation. Popular ATEs include tester platforms from vendors like Advantest, Teradyne, Cohu and others. The data rate sweet spot of pin electronics for digital instrumentation on these tester platforms is between 1.6 Gbps and 3.2 Gbps. This data rate is sufficient to drive scan test content used to test the logic cells on these processors. While most of the die’s logic area is tested with scan, structural

based functional test (SBFT), built in self-test (BIST), and custom content, the physical layer (PHY, physical front end – Tx and Rx) is production tested with an on-load board loop back Design For Excellence (DFX) technique. Typical, production load boards utilize low-loss relays to allow switching between loop back signal paths and DC test of the I/O. HIGH-SPEED DIGITAL I/O LOGIC The Serializer/Deserializer (SerDes I/Os have transaction, data link and the physical blocks that are responsible for formatting the transmitted and received data (See Figure 2).

Figure 2. PCIe high-level block diagram [2].

SPRING 2021 MEPTEC REPORT | 13

TECHNOLOGY The physical block includes the SerDes and data encoder/decoder segments. The logic implementation layers are tested with scan, BIST and SBFT logic content.

HIGH-SPEED DIGITAL I/O SIGNALS Production testing of the high-speed SerDes interface requires load board development that presents a test environment which mimics the application’s design environment in terms of signal path impedance loading. This means that the device under test (DUT) is powered with a clean power source and reference clocks (not shown in Figure 2). Typical test methodologies use common reference clock Rx architectures, which distribute the single common clock to both the Tx phase-locked loop (PLL) and Rx PLL. The loop back differential signal traces connecting the Tx to the Rx are matched within reason and present a balanced 100-Ω differential pair trace width.

AC-coupled paths include capacitors in the loop back paths.

Single-ended

Vhigh 1

0

1

0

1

1

0

1

0

1

Vlogic

Vlow Differential

V+

VDM

V-

VCM

VCM = Common-mode voltage VDM = Differential-mode voltage

Figure 3. Single-ended versus differential signal basics [3].

As shown in Figure 3, differential signal pairs employ two complementary voltage signals to transmit one digital bit signal [3]. One carries the signal (V+) and the other one carries the inverted signal (V-). The receiver extracts the information by detecting the potential difference (VDM) between the inverted and noninverted signals. The two voltage signals are balanced to have equal amplitude and opposite polarity relative to a commonmode voltage (VCM).

Differential signals have several key benefits that make them ideal for high-

speed digital signals and clocks. These include ideally zero current flowing through the ground connection, immunity to electromagnetic interference (EMI) and crosstalk, low operating voltage and higher timing precision.

Bench PHY characterization tools are typically more advanced and comprehensive relative to production test equipment. These tools have the capability to showcase a dashboard with all the relevant digital transmission statistics like the bit error rate (BER) bathtub curve and jitter components (Random Jitter (RJ), Deterministic Jitter (DJ) and Periodic Jitter (PJ)). Advanced arbitrary waveform generators (AWGs) have superior intrinsic performance at these data rates and have the capabilities to dial in a specified magnitude of injected jitter components. Test content developers periodically use such engineering tools; however, these tools are not mandatory for production testing.

PHY design verification includes receiver sensitivity and stressed eye gen-

Figure 4. Keysight Scope capture of a 2.5 Gbps K28.5 waveform generated on a Keysight Arbitrary Waveform Generator.

14 | MEPTEC REPORT

SPRING 2021

meptec.org

Key Si Integrated Heat Spreader (HS) Thermal Interface Material (TIM) Active Si (flip chip or wirebond) Wirebond die attach material

HIGH-SPEED PRODUCTION ASSEMBLY PACKAGES Several advanced packages such as flip chip ball grid array (FCBGA), Flip Chip chip scale packaging (fcCSP) and other qualified packages support all the high-speed digital requirements. The die package includes parasitic components including impairments added to the Tx and Rx signal paths from the bump or bond wire, the substrate trace and the solder ball [4, 5] as modeled in Figure 5.

Advanced packages require a rigorous package qualification process. This process includes all thermal, mechanical and electrical package performance aspects of qualification. As part of electrical package qualification, all new performance envelope extensions are simulated and then verified with an electrical verification loop. Each customer product has unique application requirements in terms of operating frequencies and bandwidth. The package design team routinely performs custom simulations for high-speed digital signal paths.

Critical shapes, geometrical dimensions, package assembly processing and material type determine the overall package performance [6]. The simulations ensure right-the-first-time success with performance targets of insertion loss better than meptec.org

TxDUT Die

Rx+ Rx-

Package

Bump I I Bond Wire Bump I I Bond Wire

Substrate Solder ball Wirebond

S-Ball Tx+

Bump I I Bond Wire

Wirebond bondfinger

Bump I I Bond Wire

S-Ball TxS-Ball Rx+ S-Ball Rx-

100Ω Differential Signal Path

Figure 5. Die-to-package pin out parasitic components contributing to the performance.

-3 dB, return loss better than -10 dB and the signal-to-signal crosstalk better than -45 dB at specific operating regions.

HIGH-SPEED PRODUCTION TEST ENVIRONMENT Potential impairments to the signal path are an integral part of the production test tooling environment. The socket pogo pin, the material type, the signal pads, the surface traces and vias on the load board impact the overall performance metrics. These design considerations are important even to implement loop back of these signals (see Figure 6).

Improper ground shielding of differential pairs, via stubs and inadequate equiva-

DUT Pin

eration, transmitter tests, DC tests and timing verification (See Figure 4). Signal bus timing and levels are tested during production testing, while intrinsic jitter and the impact of injected jitter are mostly characterized on the bench. The test methodology (and hence the Tx and Rx test list) does depend on the process technology and the end application.

High data rate or high clock rate differential signals have a smaller eye height and width - the higher the data rate, the higher the transmission parasitic losses.

Therefore, signal path optimization is critical. Also, Table 1 shows how test intervals tighten with increasing data rate.

Tx+

Substrate Trace

Table 1. Unit intervals for popular data rates.

Flip chip die bump

lent series resistance (ESR) surface mount components can result in sub-par performance. The socket and printed circuit board (PCB) material type play an important role. Good trace layout design guidelines, like top layer traces without vias and ground stitches along the trace path, can ensure minimal crosstalk.

Higher and higher data rates exacerbate the impacts of all these impairments. Test development teams work closely with the probe card and load board design house to ensure all production test requirements are met.

The requirements for different applications can vary greatly. For example. server applications are data transaction

S-Ball Tx+

Socket Pin

Pad Tx+

Pcle Tx+

S-Ball Tx-

Socket Pin

Pad Tx-

Pcle Tx-

S-Ball Rx+

Socket Pin

Pad Rx+

Pcle Tx+

S-Ball Rx-

Socket Pin

Pad Rx-

Pcle Tx-

100Ω PCB Differential Traces

Socket

Load Board Figure 6. PCIe on load board loop back to enable production testing of the PHY [7].

SPRING 2021 MEPTEC REPORT | 15

TECHNOLOGY intensive with several concurrent highspeed channels for effective bandwidth.

Desktop applications are not as power hungry and may require fewer highspeed digital transmit and receive ports.

Mobile applications (handhelds and wearables) are battery powered and have a limited number of extreme data rate requirements. By design, server and desktop applications may be able to afford molded packages like FCBGA and fcCSP or stacked die within a Packageon-Package (PoP), while mobile applications may require die or Wafer Level Chip Scale Packaging (WLCSP) designs.

In some cases, the end application may also mandate extended temperature and humidity operation. For example, automotive and military ranges are more stringent relative to consumer, commercial and industrial operation. These variations require production testers and material handling (prober and handler) capabilities for the whole gamut of package types and applications.

An experienced test development team carefully architect the test program’s test list sequence to ensure each functional block is tested to enable streamlined and efficient test execution flow. The purpose of structural scan test pattern content is to identify silicon IC fabrication and assembly packaging defects. The typical high-level production test flow includes these test insertions – Wafer Probe, Burn In, Final Test and System Level Test – prior to customerspecific backend processing and shipping instructions. The end user application noted above may mandate customization of the test flow and test limits. Crosstalk between multiple I/O lanes may be minimized by testing these lanes sequentially, if the number of lanes to test are small and the test time for each lane is small.

In the case of PCIe, the end application for the customer part might be a root complex, a bridge or an end point. The high-speed digital production test interface handling is similar. Experienced test development teams have the expertise to develop test content and production testing for each product application type.

Most processor architectures in this category implement a dedicated Design for Test (DFT) Test Access Port (TAP), which is IEEE 1149.1 compliant [8]. This five-pin serial I/O interface is typically 16 | MEPTEC REPORT

SPRING 2021

dedicated for test access to the DUT. The standard allows implementation of both public and private instructions with access to custom device test features.

With increasing digital logic and hence the need of additional test content, a new higher speed TAP interface has recently been proposed with the IEEE 1149.10 [9] standard. IEEE 1149.1 TCK rates of up to 100 MHz have served the industry well for over two decades. In some cases, TAP is used to write specific device fuse bits or to load test content via test patterns into the DUT to initiate tests like BIST or to read out scan results. The TAP may include DFX access to highspeed I/O structures in addition to other useful test features not mentioned in this article. Test developers may use such DFX device features for production testing of these high-speed interfaces.

Advanced production testers include digital sub-system instrumentation from vendors like Advantest, Teradyne, Cohu, NI and others. Advantest’s V93K and T2000 testers, Teradyne’s UFlex, J750 and other family of testers, Cohu’s Diamondx and PAx testers each have digital pin electronics with a slightly different scan test implementation. Different performance envelopes of these testers cater to the variety of customer products with a variety of scan data I/O clock rates over 500 MHz, modulo 2, 4, 8, 16 channels, memory depths over 10s of giga-vectors, impacts to load board designs and multisite capabilities. This results in offering scan content solutions at a variety of price points. The objective is to make testing easier by providing a simple way to set and observe every flip-flop in the DUT. Full scan design implementations use automatic test pattern generation (ATPG). These designs do not require sequential pattern generation and combinatorial tests are much easier to generate by the device designer, for adequate test coverage. Experienced production test developers routinely help implement such tests for customer devices.

SUMMARY High-speed serial digital interface I/O test data rates continue to increase towards 32 Gbps. The present ATEs do not provide test solutions for production test of these interfaces at their native

speeds, primarily relying on scan to test out fabrication defects. While bench characterization using differential signal techniques can verify designs, they cannot be deployed as production test solutions. Experienced test development teams can circumvent the ATE deficiencies that may be expensive to address by implementing DFX, BIST and signal path calibration. The loop back technique extends the ATE life and enables testing at native data rates. This requires extending the calibration plane on the probe cards, load-boards and sockets to the device under test. When implemented, this technique provides an accurate, atspeed and cost-competitive test solution.

Production test equipment cost is kept in control with DFX test methods that allow testing the PHY with on load board loop back. With its experience as a leading packaging supplier, Amkor has the necessary test tools to help customers with advanced production test implementations. ◆ REFERENCES [1] PCI Express® Base Specification, Revision 3.1a.

[2] PCI Express® Test Attribute Specification

comparison by generation, Internet Source.

[3] Differential signal, Internet Source.

[4] High-Speed Differential Interconnection

Design for Flip-Chip BGA Packages,

Internet Source.

[5] Package Model Proposal, Internet Source.

[6] M. F. Caggiano, J. Ou, S. Bulumulla and

D. Lischner, “RF electrical measurements

of fine pitch BGA packages,” in IEEE

Transactions on Components and Packag ing Technologies, vol. 24, no. 2,

pp. 233-240, June 2001, doi:10.1109/ 6144.926388.

[7] S. Arora, A. Aflaki, S. Biswas and

M. Shimanouchi, “SERDES external loop

back test using production parametric-test hardware,” 2016 IEEE International Test Conference (ITC), Fort Worth, TX, 2016,

pp. 1-7, doi: 10.1109/TEST.2016.7805841.

[8] IEEE 1149.1-2013 - IEEE Standard for

Test Access Port and Boundary-Scan Architecture, Internet Source.

[9]

IEEE 1149.10-2017 - IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture, Internet Source.

meptec.org

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PVT Aware Production Testing Stephen Crosher, Strategic Programs Director Adam Cron, Principal Engineer Synopsys

THE TOPIC OF EMBEDDING PROCESS, voltage, and temperature (PVT) monitors in silicon is heating up. Embedded sensors will help close the loop between Electronic Design Automation (EDA) tool models and system applications, whether on the tester or in the field.

But the open-loop power/thermal mitigation application space started many years ago. This is because it was always known that the manufacturing test process excites more of an SoC simultaneously when compared to its mission mode of operation, compounded by a desire to use closeto-maximum test speeds – and this means more power and thermal issues. Academic investigations had confirmed that there certainly was a correlation between switching activity and power. Chip design automation tools began addressing these issues with Design-for-Test (DFT) and Automatic Test Pattern Generation (ATPG) techniques. But the mitigation techniques were driven by trial and error.

Embedded PVT monitors as well as other sensors will help ensure that the application of mitigation techniques aligns with the needs of the application. As shown in Figure 1, the correlation between inchip sensor data and production test data will provide insight to device behaviors and trends, promoting an opportunity for increased test efficiency and reduced device stress.

During the production phase, one or more manufacturing tests are applied to chips. These tests may be applied at the wafer stage or at the packaging stage of the manufacturing process, or both.

For large SoCs, these tests are typically applied via scan chains built by the EDA tools. These scan chains allow ATPG tools to easily load all the flip-flops of an SoC with deterministic values while these flipflops are set to their shift mode of operation. Then, after switching to the mission mode of operation (often called the cap18 | MEPTEC REPORT

SPRING 2021

Figure 1. PVT-Aware Testing.

ture phase of the test), one or more functional clocks are applied to the design.

Once complete, the flip-flops switch again to their shift mode to unload the results of this pattern and load the next pattern.

The offloaded results are compared with the expected results to verify correct operation of the circuitry. Manufacturing defects such as gross failures (open and shorts) and more subtle failures like timing fluctuations due to process variations are detectable when a sufficient set of scan vectors are applied during production test.

Manufacturing test mitigations performed by EDA implementation tools try to address issues during both the shift and capture phases of the testing process. DFT solutions addressing shift power reduction can include q-gating and scan chain loading techniques that either try to reduce the switching activity of the functional cones of logic in the fanout of flops in the scan chains, or reduce the switching activity of the flops performing the shift operations, themselves. Capture power reduction techniques typically leverage clock gating logic, either functional or DFT-only, to reduce the number of clocks firing in the capture phase of a pattern. ATPG solutions try to achieve the same goals as the above hardware mitigation techniques. ATPG is

usually less efficient at solving the problem, but the multiplicity of options can be combined to favorable effect without over-constraining either domain. Recent advances in the modeling of power effects at the cell level in the ATPG domain have led to more accurate matches between power use estimated by the ATPG tools and that measured by sign-off applications, with the side-benefit of fewer patterns.

During the production test of large SoC designs with significant logic gate counts, we see high circuit activity during scan test. The high gate densities within advanced node designs equate to high and pronounced power densities within the die, resulting in what is often irregular self-heating producing localized thermal hots spots. Such hot spots often manifest in or around processor cores, high speed interfaces, and high bandwidth memory (HBM) – a problem which is further exacerbated if the final application possesses a 2.5D or 3D chiplet arrangement, where configurations of stacked die can exhibit higher thermal densities and restricted heat dissipation. If uncontrolled during the testing phase, the scan sequence can result in significant power being consumed and therefore thermal stress being applied to the device at a point of comparative meptec.org

infancy in its existence. Secondary issues can also emerge with the likelihood of probe pin burn-out being increased. So even before being deployed into the field within a product, the silicon has endured a thermal stress and power consumption unlikely to be seen again during its operational lifetime. Also, worth considering is the data collection metrology of test data collected, as when under an openloop control scheme, power consumption variability from device to device will be pronounced due to inter-chip deviation of process corners and leakage.

By ‘closing the loop’ with localized, high accuracy, responsive thermal feedback during the scan testing phase, there is an opportunity for PVT-aware decisions to be made by the Automated Test Equipment (ATE) in order to throttle clock frequency, and hence regulate activity and overall power consumption (representative plot shown in Figure 2). The resultant benefit is that by allowing early-life device stress to be reduced and to tighten the spread of results of device power consumptions over many wafers, detrimental effects attributable to heating such as electro-migration, accelerated aging, and decomposition can be minimized.

Counter to the thermal stress issue is a scenario of under-clocked scan frequencies, where the die under test is sufficiently ‘cool’ such that higher speed testing can be accommodated without undue stress.

By accurately sensing in-chip temperature conditions, an opportunity is presented to increase and optimize the scan test frequency, hence potentially offering test time improvement. In the absence of being able to apply supply variation schemes, dynamic scan clock frequency adjustment provides a convenient lever with which to control and manage test conditions. Under such control mechanisms, the opportunity for increased test time efficiency will correlate to thermal sensor accuracy and placement granularity. Temperature sensing circuits able to be highly proliferated throughout the die and able minimize measurement errors between sensed temperature versus actual junction temperature allows for tighter scan frequency control and subsequently greater test time optimization. Further benefit can be realized by increasing accuracy through the calibration of thermal sensing circuits, assuming that the test meptec.org

Figure 2. Power-aware testing, controlling switching activity.

Figure 3. Test failure showing PVT context.

environment is sufficiently temperature controlled, and the time to calibrate can be tolerated within test time budgets. Calibrated sensor accuracies of approximately +/-1˚C over a commercial temperature range is a reasonable expectation, which will be dependent on the technology node targeted.

The ability to analyze and diagnose the root cause of device failure is enhanced if related data sets can be enriched by supplementary information. By including embedded sensor data, further context can overlay primary results information and provide insight as to why a particular device and scan vector has failed.

Elevated localized die temperature, inherent IR drops, dynamic droops in voltage supply, or silicon being manufactured on the extreme edges of process spreads may provide clues as to why devices have failed. A PVT-aware diagnosis of failing parts offers a complementary perspec

tive to determine failure, but in order to be fully beneficial, the supplemented data requires time-stamping and locality information to be in-sync with scan information. Once these data threads are aligned, not only can the investigation into mid-production failures be aided, but potential in-field failures can be predicted.

On this latter point, imagine devices being deemed as ‘good,’ having passed the predetermined suite of tests but also having exhibited anomalous behavior indicated by unusual in-chip sensor readings. Based on the supplementary PVT information, the further color and context provided can allow for better known good die decisions to be made. Pass margins can be adjusted based on sensor information opening the opportunity for underlying failure mechanisms, undetected by binary testing, to be exposed that would otherwise not be exhibited until in-field operation. Adding a greater degree of optics to screening SPRING 2021 MEPTEC REPORT | 19

TESTING and selective deployment of silicon is of particular interest to those sectors striving for high reliability, good examples being within automotive contexts where advanced technology silicon is being integrated within product where lifecycles may be in excess of 15 years.

The potential use cases for embedded sensing are far reaching within the test context and presents the industry with an opportunity to further improve upon the two fundamental desires: to improve performance, and to improve semiconductor reliability. The concept of PVT-aware testing applies beyond the production test environment, and opportunities exist to apply the same principles of enhanced, contextualized test and diagnosis to products during mission mode, while operational in its intended system. Such in-field testing is not only beneficial to feedback trends of failure to improve wafer or package testing, but to also provide feedback for generational improvement of the design flow, where margins of the operational design space can be adapted. Adaptive high-bandwidth test solutions applied

to the silicon while in-situ offer the ability to apply manufacturing-level testing through functional interfaces such as Universal Serial Bus (USB) and PCI Express, providing a channel for the efficient transfer of large-scale test data. Concepts of data captured and analytics at each stage of the silicon lifecycle offers much promise. The ability to share meaningful, contextualized information between design, manufacture, test, deployment, and in-field phases of a product’s lifecycle is, without doubt, a ‘hot topic’ worth handling. ◆ Stephen Crosher Strategic Programs Director, Synopsys

Stephen is Programs Director for the Silicon Lifecycle Management initiative within Synopsys, working with customers to establish value based success through the adoption of in-chip sensing and analytics technologies. Former founder and CEO of Moortec Semiconductor, Stephen has over 25 years’ experience working within the electronics and semiconductor design community and in particular in the provision of embedded monitoring solutions for advanced node silicon technologies.

Adam Cron Principal Engineer, Synopsys

Adam Cron is a Principal Engineer at Synopsys working with customers worldwide on complex DFT, ATPG, and Security issues for digital ICs. He is part of the Hardware Analytics and Test R&D group, and has been with Synopsys for over 23 years. A Syracuse University graduate, Adam also worked in test-related fields at Motorola and Texas Instruments for over 36 years in the industry. Adam is Chair of IEEE Std 1838 which standardized 3D-IC test access, and is an IEEE Golden Core recipient. He has authored various papers and book chapters through the years, and is frequently a moderator, panelist, or invited speaker at various testor security-focused conferences.

About Synopsys

Founded in 1986 in North Carolina, USA, today Synopsys is among the “Top 15” largest software companies in the world and a recognized leader in the areas of Electronic Design Automation (EDA), Technology Computer Aided Design (TCAD), and Software Quality, Integrity and Security (APPSEC) tools and services. Headquartered in Mountain View, California, Synopsys employs over 14,000 engineering and support staff globally.

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INTERVIEW

Fifty Years of Working in the Semiconductor Industry and Over a Dozen Major Lessons Learned Herb Reiter eda 2 asic Consulting, Inc., Retired

I have been asked to share some of what I learned during my 50 years as user and supplier of semiconductors and Electronic Design Automation (EDA) tools and methods. Here are brief summaries of my roles and more importantly the major lessons learned in this industry, in chronological order: AFTER STUDYING ELECTRICAL engineering for five years at the technical college in Linz, Austria, I graduated as MSEE in the class of 1971. Our school was well respected in the industry, and every graduate had several job opportunities to choose from. I chose the SIEMENS Central Laboratory in Munich as my first employer. My role was to develop the transmit/receive interface card between 120V cross-country phone lines and an RS232 interface into the T1000, the industry’s first electronic teletype. It received/transmitted “highspeed” ASCII signals (50 bits/sec !?) about 20 miles to a telex exchange and/ or other teletypes. YouTube shows what a T1000 looked like and how “fast” it worked in those days: SIEMENS T1000 Fernschreiber/Teletype/Teleprinter/TelexPhone/TELEX/i-Telex-YouTube [1] 1st Lesson: It takes many well-coordinated people across a large corporation to develop a complex product, manufacture it cost-effectively in high volumes, and sell it profitably worldwide. _________________________________

After working with discrete components (transistors, diodes, resistors, inductors, opto-couplers, …) at SIEMENS for more than two years, I joined a much smaller company in Munich to broaden my scope. I managed manufacturing operations and development of various data logging systems for telecom, automotive and marine applicameptec.org

tions, even for a research project in a nuclear power plant. I liked this versatile role but realized that I lacked knowledge about business topics.

2nd Lesson: If you run a small company, you must have development partnerships and a reliable supply chain to succeed. _________________________________

German law requires that companies share the profits made from inventions with the actual inventors. I registered more than a dozen analog circuit design patents during my work on the T1000 teletype. This product was highly profitable. And in early 1976 SIEMENS sent me a big check for my share of these profits. This large amount of money, tuition free higher education in Austria, and part-time work allowed me to finance my living expenses during a 4-year MBA program in Linz. Improving my communication, planning, legal, marketing, organizational, and financial skills was a good investment and allowed me to get job interviews at many employers in Germany and Austria.

planning speech recognition solutions. c) Spending an entire day with the very intelligent Dagmar Berghoff in a recording studio in Hamburg.

She was the main German TV News speaker, like Tom Brokaw was in the U.S. We recorded sample sentences in her voice, with many different paces and intonations, to make them suitable for data compression and storage in a “large” EPROM (16k bits!? of erasable programmable read-only memory). DigiTalker enabled Ms Berghoff to tell every Audi Quattro luxury car driver when a door was ajar, the gas tank was running low, etc.

How did drivers react to talking chips in 1981? Most of them promised to turn this feature off right away. They reasoned that hearing another voice, in addition to their always nagging spouse, was simply too much. That was the end of the revolutionary DigiTalker and my first experience with marketing ICs.

1980

3rd Lesson: Understanding technology is valuable. Complementing engineering knowledge with understanding of business considerations and human behavior is useful.

4th Lesson: Creating a market for a new product is much harder than introducing a good solution that meets current market need.

In 1980 a young and energetic Herb joined National Semiconductor’s European headquarters in Munich as product marketing engineer for a revolutionary speech synthesis chip, branded DigiTalker. Highlights of this job were: a) Business trips across Europe. b) Getting to know Jim Soloman, leader of National’s analog division, and Joe Costello, R&D expert improving speech synthesis and

National assigned me right away to another bleeding-edge technology: Bipolar Programmable Logic Devices (PLDs). I started this role with 20 PLD samples on my desk and no PLD opportunities nor revenues to expand from. It took me, together with in-house as well as external partners, about two years to build an ecosystem for the 14 and 16-pin PLDs in Dual Inline Packages (DIPs).

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INTERVIEW We created data sheets and application notes, qualified several programmer vendors and a design software partner to make PLD customization more user friendly. We trained National’s field application engineers how to use PLDs and they offered training seminars across Europe. All these efforts resulted in PLD revenues of more than $ 1 million per month. However, these happy times did not last. When AMD introduced the faster and lower power CMOS 22V10 with 28 pins and much more logic, the demand for National’s PLDs vanished.

5th Lesson: a) If YOU do not obsolete your legacy products, somebody else will, and b) A higher level of integration always wins. _________________________________

At the end of 1983, National transferred me to their worldwide headquarters in Silicon Valley to market another bleeding-edge technology: Bipolar gate arrays (a.k.a. ASICs). At that time offering faster computers was the primary goal of system companies – regardless of component cost and power dissipation. My ECL gate arrays were a perfect fit. They made money for National, but only for several years. When much lower power CMOS gate arrays became widely available, offered reasonable speed, more pins, and many more gates, I became the official “funeral director for bipolar gate arrays” at National.

6th Lesson: Performance per Watt, not raw speed, is a key success criterion for an IC’s success. _________________________________

I do not like funerals, so it was time for me to move on. Right after the big earthquake in 1989, I joined the CMOS ASIC technology leader VLSI Technology (a.k.a. VTI) in San Jose as alliance manager for European partners – Philips, ARM, EM, ZMD, and others. My boss, the VP of Strategic Alliances, taught me how complementary and profitable wellmanaged corporate alliances can be – if they are win-win partnerships.

After three years of alliance management, VLSI’s CTO offered me a strategic product planning position on his team.

I became the worldwide missionary for 24 | MEPTEC REPORT

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ASIC core technology innovations and market researcher for new ASIC requirements. In parallel with this strategic role, I managed first a development program for a 400+ pin tape-bonded package for the CPU in Apple’s Newton, the grandfather of today’s iPads. When VLSI developed a family of chips for a high-end graphics workstation, they needed 300 to 800 pin high-power packages. I managed the development cooperation between IBM Endicott and VLSI to develop and qualify five tape ball grid arrays (TBGAs) for volume production.

7th Lesson: These two big, important, and highly visible packaging programs showed me how complex and important IC packaging technology is and how critical the right packages are for the success of semiconductors. _________________________________

The long and expensive development of ASICs encouraged more and more customers in the 1990s to switch to offthe-shelf application-specific products (ASSPs) for their system designs. VLSI gave me the opportunity to market ASSPs, specifically QAMs, QPSKs, MPEG decoders, modems, and controller chips for digital set top boxes and other consumer applications.

8th Lesson: Adding intellectual property (IP) to an ASIC increased the IC’s value significantly. _________________________________

As IC complexities and pin-counts increased steadily and low unit cost became much more important, the need for user-friendly and high-productivity IC design and verification tools increased rapidly. VLSI’s in-house electronic design automation (EDA) team could not keep up with all the new requirements.

And VLSI, the former ASIC leader, was no longer competitive and encouraged Philips to acquire them.

9th Lesson: a) It was great to work at an integrated device manufacturer (IDM). I was able to get all needed IC design and manufacturing experts into one room, map out project plans, then manage their execution in regular meetings and with agreed upon action items, and b) If a company’s capabilities

in important areas (e.g., EDA) are not competitive, they need to find competent partners or buy these capabilities externally – otherwise they will lose market share, get acquired, or die.

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As more and more analog circuits got replaced by digital circuits in computers, communication and consumer products, EDA tools for accurate timing analysis (a.k.a. timing closure) became critically important.

How can a hardware guy in a hardware company (VLSI) address this EDA challenge/opportunity? It was impossible, so I joined ViewLogic, a medium size EDA company, in Fall 1996. They needed an alliance manager for a small support team (called ASIC Vendor Program) serving the biggest ASIC vendors worldwide in developing libraries as well as evaluating, qualifying, and integrating Motive and two other tools into their design flows. ViewLogic’s best product was Motive, a user-friendly and accurate static timing analysis (STA) solution.

Our customers liked Motive and my team’s support. These customers in turn encouraged Synopsys to acquire ViewLogic.

10th Lesson: Having walked in the customers’ shoes for almost 20 years – at National and VLSI – helped me significantly to understand their requirements and build strong partnerships between ViewLogic and their key customers – the largest ASIC vendors. All of them were, like National and VLSI, integrated device manufacturers (IDMs). They had demanding corporate teams for developing libraries and for evaluating, qualifying, and integrating merchant design tools into their product groups’ IC design flows. _________________________________

End of 1997 Synopsys acquired ViewLogic for ~ $ 400 Million. Because the big ASIC vendors suggested it, Synopsys put me in charge of their Semiconductor Vendor Program (SVP) to manage these alliances in the U.S. My now much larger team supported library developments, tool evaluations, and design flow integrations of many tools: PrimeTime, Design Compiler, VCS, Formality, TestMax, and others. We also expanded a meptec.org

project I started at ViewLogic jointly with TSMC (a dedicated wafer foundry): we developed TSMC’s first and second reference design flows for fabless IC vendors. In other words, SVP worked with the largest IDMs and fabless/fab-lite IC vendors to develop the infrastructure they needed to quicker and easier design ASICs and ASSPs, using Synopsys tools.

Our customers and Synopsys’ top management liked the significant progress my U.S. team made and expanded my responsibilities to include Synopsys’ local SVP teams in Japan, Taiwan, and Europe. However, major differences with my direct boss finally led me to resign.

Leaving my great team with 25 excellent engineers was difficult but necessary.

11th Lesson: Your manager’s personal objectives can undermine the success of your company’s most important programs. _________________________________

During 1999 it became obvious that the emerging internet would significantly impact the semiconductor industry. Early 2000 I joined Barcelona Design, one of the many “.com start-ups”, as alliance manager for their big customers. Our team of highly educated Stanford Ph.D.’s really impressed me and our customers.

However, meeting the Ph.D.’s ambitious goal to quickly revolutionize analog circuit design with web-based optimization engines was more difficult than expected. Somebody needed to be blamed for the lack of success. Management chose the only person without a Stanford Ph.D. at Barcelona – and encouraged me to resign. A month later they tried to get me back.

12th Lesson: Analog circuit design is a creative art. Algorithms, computers and networks could not compete with analog gurus – certainly not at that time and maybe never. _________________________________

I did not mind leaving Barcelona, because I already had plans to start my own company – to bring developers of EDA tools and big ASIC/ASSP manufacturers closer together.

Early 2002 I founded eda 2 asic Consulting, Inc. to focus on building alliances between small EDA vendors meptec.org

and large ASIC/ ASSP vendors. The relationships I had built with these large ASIC vendors at ViewLogic and Synopsys opened many doors for me and my consulting clients. I really enjoyed these rewarding years as a “corporate matchmaker”. However, the 2008 financial crisis encouraged the large semiconductor vendors to focus only on large EDA suppliers. This forced many small companies, including my clients, to cut budgets for consulting services.

While one door closed, another one opened: Many large semiconductor vendors were no longer IDMs but fab-lite or fabless companies [2] and needed to work with partners to build a complete and cost-effective supply chain. They needed industry organizations, like the Fabless Semiconductor Association (FSA), to help streamlining the complex supply chains, accelerating essential innovations, and driving best practices and industry-wide standards.

The FSA, later renamed to Global Semiconductor Alliance (GSA), offered me in early 2008 the opportunity to manage their EDA Working Group. I gladly accepted. After a few working group meetings, we concluded that our focus should be the emerging 3D-IC technology. We expected it to require many new EDA tools which would offer EDA vendors new growth opportunities. However, in the following years it became obvious that combining multiple dice in an IC package faces significantly bigger EDA and manufacturing challenges than expected, e.g., heat dissipation, thermal-mechanical forces, power and signal integrity, wafer thinning and bonding/debonding, TSV filling/revealing, die and interposer warping, microbump cracking, and many others. All of these increased 3D-IC development challenges and unit cost. When the path to profitable 3D-IC design and manufacturing flows looked much steeper than expected, the working group lost momentum and stopped meeting at the end of 2012.

Maybe I am crazy, but for me 3D-IC technology is the best opportunity to

2002

encourage our component-focused semiconductor industry to design and manufacture much higher value (= more profitable) system building blocks. That is why I consulted with these 3D-IC focused industry organizations from 2013 until my retirement in 2020: - SEMATEC’s 3D-IC team to address development of equipment and manufacturing flows for 3D-ICs, - Silicon Integration Initiative (Si2) to develop 2D & 3D-IC design flows, best practices, and standards, - Electronic System Design (ESD) Alliance to encourage our industry to expand from the component-focused activities and target more profitable system-level building blocks, - SEMI through my work as a blogger for 3D InCites [3], a media company. I was able to engage with many of SEMI’s 2000+ worldwide member companies that span all areas of the electronic systems’ supply chain. SEMI teams have initiated and coordinated, so far, more than 1000 manufacturing standards.

They are also organizing workshops and conferences on technical and business topics worldwide. And they even play a major role in getting the US government’s attention for our industry’s needs and are working with other countries’ governments. SEMI’s Heterogeneous Integration Roadmap (HIR) efforts are an essential and industry-wide contribution to the proliferation of 3D-ICs and advanced packaging technologies.

My almost 20 years of eda2asic Consulting services were challenging but interesting and rewarding. My broad background helped me to learn quickly and contribute in many different ways at each one of the many companies and organizations.

Final Career Lesson: The most important factor for my success as a consultant were the many friends and supporters that gave me opportunities to be of service. THANK YOU ALL !

_________________________________ Just like a vintage car, an aging human body also needs a lot of maintenance. During the most recent “service call”, my doctor suggested that I should fully retire. My wife liked this idea very much, therefore I decided to take my SPRING 2021 MEPTEC REPORT | 25

INTERVIEW MÜHLBAUER DIE SORTING

Q: What was it like to move from Munich to Santa Clara in the 1980’s?

A: Transferring within National Semiconductor made this change relatively easy for me. But a few strong impressions remain: a) I was shocked about the cost of housing and, compared to Munich, the limited public transportation network. b) The few window offices and the many tiny cubicles was another big change for me. c) My British English caused some problems for me in California, especially when I asked my secretary for a “r…..”.

(Americans call it “eraser” and use the other term to refer to a prophylactic.) d) At the first meeting with my new boss, I learned that Californians are very efficient and would not call me by my official given name “Herbert” but expect me to respond to a shortened “Herb”.

On the positive side, I liked the many more lanes on highways, the leisurely pace of highway driving (compared to 100++ miles/hour on the Autobahn in Germany), and how easy it was at that time to find a parking spot. I also must admit that many ladies, after they learned that I was born in the country where the “Sound of Music” was filmed, 26 | MEPTEC REPORT

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A: DigiTalker was an NMOS chip, operating at several kHz clock frequency.

Memories were tiny and expensive. If anybody would have told us what Siri does today in an iPhone, we would have laughed at this dreamer.

A: EDA developers at UC Berkeley introduced SPICE simulation in 1972.

With IC complexities up to a few hundred gates, nobody complained about better electronic design automation tools in the 1970s. When CMOS technology allowed much larger gate arrays, in the mid ‘80s, basic gate-level simulation, place and route, layout versus schematic verification, extraction, timing analysis, test tools, etc. became more important.

Today, with billions of gates in a chip, designers must have a range of planning, implementation, and verification tools to successfully design and integrate one or several dice into an IC package.

The DS Variation ecoLINE fits the current market demand for more flexibility.

MÜ

Q: When struggling with basic speech synthesis at National, did I or anybody around me expect how easy it is today to utilize speech recognition and synthesis to improve human productivity?

Q: How has EDA changed over the years?

MOST FLEXIBLE DIE SORTING SYSTEM

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A few more questions and answers… not to mention additional lessons...

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DS VARIATION ecoLINE

LB

2020

were nice to me… because they wanted to know more about Austria.

MÜH

aging body “out of service”, after 50 years of working hard on the “bleeding edge” of semiconductor technologies.

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6-in1 system flip & non-flip wafer-to-wafer tape & reel / reel-to-reel100% traceability waffle pack / gel-pack®/ JEDEC tray

_________________________________ Q: What is lacking in our industry in terms of infrastructure/relationships/ technology/etc.?

www.muhlbauer.com

A: In my role as “matchmaker” between EDA developers, IC designers, and manufacturers I found that we all need much more education about partners’ requirements and capabilities to minimize iterations and avoid catastrophic failures. Multi-company working groups – under the umbrella of industry organizations, like the HIR working groups at SEMI and the semimonthly webinars at MEPTEC, are perfect examples for addressing these challenges well.

In addition, experienced people at practically every company need to establish much better personal relationships with experts at complementary companies to make projects/programs succeed in a timely manner. These expert relationships were (and still are) a key success factor at IDMs and especially useful to complete large projects on schedule and within budget. ◆ REFERENCES

[1] https://www.youtube.com/watch?v= lCZmVXGyVQQ [2] https://semiwiki.com/eda/1840-a-brief- history-of-the-fabless-semiconductor-ecosystem/ [3] https://www.3dincites.com/

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