MEPTEC Report Spring 2022

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

Volume 26, Number 1

SPRING 2022

MEPTECReport Addressing the Semiconductor Industry Workforce Needs: Microelectronic Engineering Education at Rochester Institute of Technology page 14

+

Revising 5G RF Calibration Procedures for RF IC Production Testing page 10

INSIDE THIS ISSUE

3

UP FRONT Springing Back – Wow! What a crazy? busy? frantic? start 2022 has been so far.

4

CALL TO ACTION The DoD should consider offering incentives to encourage the private sector to qualify alternative sources of solder columns.

5

18

MEMBER NEWS from Henkel, Analog Devices, Infineon, Finetech, USI, Intel, FormFactor, EdgeCortix, and OpenFive.

CATCHING UP WITH Jaspreet Gandhi, Director of Advanced Product Development at Xilnix joined the MEPTEC Advisory Board in 2020.

UP FRONT The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council 141 Hewitt Street, Summerville, SC 29486 Tel: (650) 714-1570 Email: bcooper@meptec.org Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown Sales Manager Gina Edwards

MEPTEC Executive Director Ira Feldman

MEPTEC Advisory Board Board Members Dave Armstrong Advantest Ivor Barber AMD Calvin Cheung ASE (US) Inc. Zoë Conroy Cisco Jeff Demmin Keysight Technologies Abram Detofsky Intel Neal Edwards AMD Jaspreet Gandhi AMD Ravi Mahajan Intel Emeritus Advisors Seth Alavi Sunsil Joel Camarda Anna Gualtieri Elle Technology Phil Marcoux PPM Associates Mary Olsson Herb Reiter eda 2 asic Consulting, Inc., Retired In Memoriam Ron Jones Contributors SangHo Byun Amkor Technology Korea Jaspreet Gandhi Xilnix Martin Hart TopLine Corporation Venancio Kalaw Amkor Technology Philippines JeongYon Kim Amkor Technology Korea Santosh Kurinec Rochester Institute of Technology Mon Lopez Amkor Technology Philippines Vineet Pancholi Amkor Technology, Inc.

Springing Back Ira Feldman Executive Director, MEPTEC

Wow! What a crazy? busy? frantic? start 2022 has been so far. Not only is the semiconductor industry busy with continued high demand, but we are all trying to figure out the “new normal”. For some, it is a very slow “re-engagement” with the outside world as they remember how to socialize and interact with others. And at the other end of the spectrum, there are those off at full speed attempting to make up for lost time. Combined with this a flurry of in-person and virtual events.

MEPTEC started the Road to Chiplets series off this year with Heterogenous Integration (HI) Testability in March 2022. We discussed the challenges of and best-known methods for Chiplet and other HI testability. If you missed any of the excellent presentations or the lively panel discussion from this event you can find them on events.meptec.org including links to the YouTube videos.

On May 10-12, we will continue with the Road to Chiplets – Design Integration. We will discuss the role and challenges of Design Integration in the upcoming storm of Chiplets at this free virtual event. Properly implementing and developing methodologies to manage DI is essential to make Chiplets commercially viable.

We started the MEPTEC-IMAPS Semiconductor Industry Speaker Series webinars off strong in early February with an excellent presentation from Jan Vardaman of TechSearch International reviewing her outlook for 2022. And Professor Santosh Kurinec of Rochester Institute of Technology presented their very successful model for workforce development which she also details in a companion piece in this issue of the MEPTEC Report. We be announcing other upcoming SISS webinars shortly and appreciate any recommended presenters or topics.

I look forward to hearing your suggestions and feedback as to how MEPTEC can best serve you. Please don’t be shy!

Stay safe and healthy!

HyeongSik Youn Amkor Technology Korea

MEPTEC Report Vol. 26, No. 1. Published quarterly by MEPCOM LLC, 141 Hewitt Street, Summerville, SC 29486. Copyright 2021 by MEPCOM LLC. All rights reserved.

Materials may not be reproduced in whole or in part without written permission.

MEPTEC Report is sent without charge to members of MEPTEC. For non-members, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere. For advertising rates and information contact Gina Edwards at 408-858-5493.

Ira Feldman Executive Director, MEPTEC ira@meptec.org +1 650-472-1192

SPRING 2022 MEPTEC REPORT | 3

CALL TO ACTION

FPGA Single Point of Failure Martin Hart TopLine Corporation

Category Assessment A SINGLE POINT OF FAILURE FOR critical applications within the Defense Industrial Base are Field Programmable Gate Arrays (FPGA) that rely on solder columns to connect to PC boards.

A surprisingly small number of civilians, primarily engineers and department managers in the supply chain, continue to make policy decisions that could have a profoundly harmful effect on U.S. national security. 90% of ruggedized FPGA that use solder columns are supplied by a tiny solesource subcontractor located in Silicon Valley, California.

Supply chain decision makers have decided through their actions, or inaction, not to qualify an alternative supplier for solder columns. This policy of depending on one supplier without a back up overlooks the potential that the current solesource subcontractor of solder columns certainly cannot continue to provide this vital service forever.

Vulnerable Choke Point is Ignored It is well known by thought leaders within the Defense Industrial Base that solder columns are the “Achilles Heel” for sustainability and resiliency of ruggedized FPGA components in the supply chain.

Warfighters and missiles cannot be operable without solder columns attached to FPGA components.

Our Nation does not have a “Plan B” to immediately step in and fill the supply chain void should a demand surge exceed the capacity of the current sole source supply of solder columns.

Subject matter experts estimate that as a consequence of COVID-19, it may take three years for the U.S. Defense Logistics Agency (DLA) to clear its backlog schedule and resume field audits for the purpose of certifying a second source of solder column attachment services.

In the meanwhile, the defense industrial base remains vulnerable, A study released by the National Defense Industrial Association (NDIA), 4 | MEPTEC REPORT

SPRING 2022

Column Attachment Production Lines

Single

Skilled Labor Pool Mature Innovation Limited Business Continuation Next 5-years

Uncertain

Business Continuation Beyond 20-years

Doubtful

Current Production Capacity

Line is Full

Potential for Delayed Delivery

High

Probability for Price Increase

High

Forecasted Customer Demand for Columns

High

Surge Readiness Questionable Capability to Expand Production

Limited

Threats by Force Majeure

Earthquake/Fire

Terrorism / Espionage / Civil Unrest

Potentially

Equipment Condition Aging Threats to IP / Hacking

Unknown

Potential for Business Interruption

Probable

Risk Analysis of Relying on Sole Subcontractor of Solder Columns. titled, “Vital Signs: The Health and Readiness of the Defense Industrial Base” generally indicates a grade of “Unsatisfactory, Fail” for the readiness of the U.S. defense industrial base.

Risk Summary The current source of 90% of the industry’s column attachment services will not last forever. It is risky for the Defense Industrial Base to expect that such services will be around 5 years from now, let alone another 20 years.

Small enterprises with aging owners rarely grow their businesses by investing in new equipment and hiring fresh management.

A number of risk factors suggest low confidence that the business is assured of being capable of meeting a demand surge.

Summary Major producers of defense-grade

FPGA components, including market leaders Microchip, Texas Instruments, Xilinx and others seem satisfied with relying on a sole source for the critical last step of attaching solder columns.

The industrial base is reluctant to expand their reliance beyond the current single source subcontractor who provides 90% of America’s solder column attachment services.

Conclusion The Department of Defense (DoD) should consider offering incentives to encourage the private sector to qualify alternative sources of solder columns.

Defense grade FPGA components depend on solder columns to keep warfighters operational.

America remains vulnerable to losing her leadership position in the world as the primary source of these devices. ◆

meptec.org

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MEMBER NEWS Infineon Doubles Down on Wide Bandgap by Investing More than €2 Billion in a New Kulim, Malaysia Frontend Fab to Expand Market Leadership in Power Semiconductors INFINEON TECHNOLOGIES AG is strengthening its market leadership in power semiconductors by adding significant manufacturing capacities in the field of wide bandgap (SiC and GaN) semiconductors. The company is investing more than €2 billion to build a third module at its site in Kulim, Malaysia. Once fully equipped, the new module will generate €2 billion in additional annual revenue with products based on silicon carbide and gallium nitride.

The expansion, following the company’s long-term manufacturing strategy, will benefit from the excellent economies of scale already achieved for 200-millimeter manufacturing in Kulim. It will complement Infineon’s leading position in silicon, based on 300-millimeter manufacturing in Villach and Dresden. The new investment will greatly rein-

force the overall competitive advantage, which is based on the combination of technology leadership, a broad product portfolio and deep application know-how, following Infineon’s “Product to System” approach.

“Innovative technologies and the use of green electrical energy are key in reducing carbon emissions.

Renewable energies and electro-mobility are major drivers for a strong and sustainable rise in power semicon-

ductor demand,” said Jochen Hanebeck, Chief Operations Officer at Infineon. “The expansion of our SiC and GaN capacity is readying Infineon for the acceleration of wide bandgap markets.

We are creating a winning combination of our development competence center in Villach and cost-effective production in Kulim for wide bandgap power semiconductors.”

For more information visit www.infineon.com. ◆

OpenFive and EdgeCortix Collaborate on an AI Accelerator Custom SoC EDGECORTIX® INC., THE AI-FOCUSED fabless semiconductor company that enables best-in-class power-efficiency with near cloudlevel performance across infrastructure and embedded edge devices, and OPENFIVE, a leading provider of custom silicon solutions with differentiated IP, have announced they are collaborating to develop and deliver a highly power-efficient and high-performance custom 12nm FinFET SoC that accelerates artificial intelligence processing for real-time edge applications.

The IP driving EdgeCortix’s SoC is the Dynamic Neural Accelerator® (DNA) architecture, designed with a unique software-first approach, forming a tight coupling between today’s neural networks and an underlying lowpower domain-specific hardware architecture.

This is backed with robust software to seamlessly process applications across different meptec.org

machine learning frameworks. The IP is optimized for real-time processing (e.g., batch 1), delivering value and performance for customers in business sectors including defense, autonomous vehicles, satellite and 5G communications, smart cities and manufacturing. EdgeCortix’s SoC features a unique and proprietary runtime reconfigurable architecture that enables the SoC to deliver over 10x efficiency gains over traditional GPUs. OpenFive is contributing its low power, leading-edge deep-submicron FinFET design methodology that will make it possible to efficiently implement the complex SoC in TSMC’s 12nm FinFET process, together with packaging and supply chain experience to ensure a smooth ramp up to volume production.

For more information, please visit www. openfive.com or contact: info@edgecortix.com for more details or to schedule a demonstration. ◆



INTEL TO ACQUIRE GRANULATE

INTEL CORPORATION announced an agreement to acquire Granulate Cloud Solutions Ltd, an Israel-based developer of real-time continuous optimization software. The acquisition of Granulate will help cloud and data center customers maximize compute workload performance and reduce infrastructure and cloud costs. Over the past year, Intel and Granulate have worked together under a commercial agreement to collaborate on workload optimization on Xeon deployments. This collaboration resulted in gains in performance and decreases in costs for customers running on Intel processors. The transaction is expected to close in the second quarter of 2022. www.intel.com



USI AWARDED S&P GLOBAL BRONZE CLASS IN SUSTAINABILITY YEARBOOK 2022 USI has been recognized as a S&P Global Bronze Class company in their first invited participation of the S&P Global ESG Index Corporate Sustainability Assessment (CSA).

The Sustainability Yearbook 2022 is based on the 2021 CSA that evaluated over 7,500 companies across 61 industries. The Yearbook highlights the best-performing companies among industry peers and in terms of financially material environmental, social, and governance (ESG) metrics. USI was honored with the Bronze Class award for the Electronic Equipment, Instruments & Components industry group. www.usiglobal.com

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SPRING 2022 MEPTEC REPORT | 5



MEMBER NEWS 

FINETECH USA ADDS CLEAN ROOM SPACE TO ITS CUSTOMER APPLICATIONS CENTER

FINETECH has announced the completion of a Class 1000 (ISO 6) clean room to its US facility in Amherst, New Hampshire. The building houses the Finetech eastern sales and applications support team. Its extensive demonstration room houses numerous die bonders and rework systems. The addition of the cleanroom significantly improves Finetech’s ability to bond customer parts using it’s most accurate R&D and production models. With placement accuracies of 0.3 µm on the FINEPLACER® femto 2, and 0.5 µm on the FINEPLACER® lambda 2, the new controlled environment gives more customers the opportunity to bond realworld samples. www.finetechusa.com

 HENKEL E-MOBILITY

BUSINESS UNIT ESTABLISHES A STRATEGIC PARTNERSHIP WITH PEM MOTION HENKEL has entered a strategic partnership with RWTH Aachen University’s Production Engineering of E-Mobility Components (PEM Motion GmbH) to collaborate on research projects in the field of e-mobility. By building a strong partnership between industry and academia, the organizations will pioneer next generation battery technologies, explore material requirements for their realization and in the development of safer and more sustainable batteries. PEM Motion has more than 70 employees in Europe and North America at a total of five locations. www.henkel.com

◆

6 | MEPTEC REPORT

Analog Devices’ Wireless Battery Management System Achieves Top Automotive Cybersecurity Qualification ANALOG DEVICES, INC. HAS ANNOUNCED its Wireless Battery Management System (wBMS) is certified to the highest standard of automotive cybersecurity engineering and management. ISO/SAE 21434 is the new standard for cybersecurity risk management throughout the lifecycle of the vehicle from concept, product development and production, to operation, maintenance, and decommissioning of electrical and electronic systems. TÜV NORD Mobilität, the assessor for this qualification, affirmed that ADI’s wBMS is the first automotive system that it has certified for ISO/SAE 21434. The assessment confirmed that ADI performed appropriate assurance measures within the product development to fulfill the CAL 4 requirements.

Since announcing the industry’s first wBMS with General Motors in 2020, ADI has brought this technology to mass production as a turnkey solution for vehicle manufacturers with security designed in at every level. The transition of battery packs from wired to wireless connectivity enables automotive manufacturers to scale their electric vehicle fleets into volume production across a wide range of vehicle classes, and wBMS provides the modularity, flexibility, and scalability to streamline the design and assembly processes with connector-free batteries. With this reliance on wireless communication, ensuring transparency, security, and ease of deployment for the system are critical.

“We conducted an intensive assessment to verify that ADI’s wBMS conforms to ISO/SAE 21434 requirements. With ADI considering the CAL 4 classification conditions throughout product development, the cybersecurity assurance measures complied with the highest requirements,” said Leif-Erik Schulte, Senior Vice President at TÜV NORD Mobilität. “This system certification is a key element to build trust across the full electrification ecosystem – from energy storage to OEMs to consumers – to support EV adoption and help reduce emissions.”

For more information visit the Analog Devices website at www.analog.com. ◆

FormFactor Introduces High-Power Semiconductor Wafer Probing System for Automotive, Renewable Energy, and Industrial Applications FORMFACTOR, INC. HAS introduced the TESLA300 high power semiconductor probing system. Designed specifically for IGBT and power MOSFET device measurements, the TESLA300 provides accurate data at up to 10,000 V and up to 600 A current on 300mm wafers.

Integrating new anti-arcing and wafer automation capabilities, the TESLA300 enables high-throughput, unattended testing over a wide thermal range to speed development and lower production cost of power devices.

Automotive, energy and

SPRING 2022

industrial applications drive growth today in power devices; analysts at Yole Développement (Yole) projected in February 2021 that the market for this technology in electric and hybrid electric vehicles would grow at 26% CAGR between 2020 and 2026 to $5.6B in 2026. To meet market demand, major IDMs and foundries are researching new materials and beginning to manufacture power devices on 300mm wafers. With its unique features and 300mm automation capabilities, the TESLA300 system provides ideal support for both R&D

technical requirements and niche production test applications.

TESLA300 key features include: • Accurate, high-yield, drainto-source resistance (Rds) • Industry-leading measurement performance.

• Flexible wafer handling, up to 300mm in wafer size, with semi or fully-automated configuration.

• Full thermal testing from -60 to +300°C. • Integrated, TÜV-certified safety system.

For more information, visit www.formfactor.com. ◆ meptec.org

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SPRING 2022

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TESTING

Revising 5G RF Calibration Procedures for RF IC Production Testing Vineet Pancholi, Senior Director, Test Technology | Amkor Technology, Inc. HyeongSik Youn, Director, Test Engineering; JeongYon Kim, Director, Test Development Department Manager; SangHo Byun, Senior Director, Master Test Engineering; MinHo Chang, Vice President, Test Development Division Manager | Amkor Technology Korea Venancio Kalaw, Radio Frequency & MEMS, Test Development Engineering; Mon Lopez, Director, Development Department Manager | Amkor Technology Philippines

Tester

IF (Tx, Rx)

mmWave Up/Down Converter

RF (Tx, Rx) RF (Tx, Rx)

Vector Signal Transceiver

DUT Load Board

Load Board Interface RF (Tx, Rx) IF (Tx, Rx)

mmWave Up/Down Converter

RF (Tx, Rx)

Converter

DUT Load Board

Source: NI mmWave Transceiver Block Diagram Figure 1. Test system configuration for mmWave RF testing.

MODERN RADIO FREQUENCY (RF) components introduce many challenges to outsourced semiconductor assembly and test (OSAT) suppliers whose objective is to ensure products are assembled and tested to meet the product test specifications.

The growing advancement and demand for RF products for cellphones, navigational instruments, global positioning systems, Wi-Fi, receiver/transmitter (Rx/Tx) components and more keeps growing and driving the demand for more advanced 5G cellphone and Wi-Fi components.

In any RF test system, the ability to achieve instrument-port accuracy at the device under test (DUT) enhances measurement accuracy and repeatability.

Unfortunately, the non-ideal nature of the cables, components, traces and switches and other items in the paths between the instruments and the DUT can degrade 10 | MEPTEC REPORT

SPRING 2022

measurement accuracy.

While current calibration methodologies may have worked in the past, the mmWave advancement in RF technologies demands calibration procedures be revised for the specification extensions. It is important to consider key major points of signal path calibration, namely: system calibration, cable calibration, load board trace de-embedding and golden units’ calibration as well as how to use these aspects as a unique advantage in developing calibration standards. mmWave RF Test Proper selection of test equipment, connectors, adapters and system-level calibration enables accurate measurements to evaluate the true performance of 5G components or devices, see Figure 1. At mmWave frequencies, signals are

more susceptible to impairments, requiring extra consideration in the selection of test solutions, cables and connectors.

System-level calibration is also essential to achieve accurate measurements.

RF Calibration Calibration ensures the measurement system produces accurate results. All non-idealities in the paths between the test system instruments and the device under test can degrade the measurement accuracy or result in flatness errors. One must extend the measurement accuracy from the test system signal source’s output or its measure input to the DUT’s test port as shown in Figure 2. Measurement of the frequency response of the test fixture, cables and connectors may be required to obtain an accurate, calibrated measurement. meptec.org

5G promises substantial improvements in wireless communications, including higher throughput, lower latency, improved reliability and better efficiency. Achieving these goals requires a variety of new technologies and techniques, like higher frequencies, wider bandwidths, new modulation schemes, massive multiple input, multiple output (MIMO), phased-array antennas and more.

These technologies bring new challenges in the validation of device performance. One of the key measurements is error vector magnitude (EVM), which is a system-level specification for modulated signals as they are delivered to and received from the DUT. In many cases, the EVM value must remain below a specific threshold—and getting an accurate measurement requires that the test system itself have a low noise floor (i.e., a low EVM).

The two types of calibration methods used to account for and correct these measurement errors are vector and scalar calibration.

Vector Calibration The vector calibration method requires measurements of both the magnitude and phase characteristics of the RF path. This can be done by either performing a network analyzer calibration at the DUT’s input and output ports or by using a calibrated network analyzer to measure the scattering (S) parameters[1] of the RF path. The latter method provides a complete, complex-valued characterization of the signal path.

Scalar Calibration The scalar calibration approach characterizes only the magnitude characteristic of the RF path, which is equivalent to measuring only the magnitude portion of the S21 transmission coefficient in a vector calibration. A common technique involves driving one end of the path with a signal generator and measuring the signal at the other end with a power meter. The magnitude portion of the path response (loss) is determined by subtracting the source power level (in dBm) from the measured power level (also in dBm). This is repeated at multiple frequencies across the band of interest to determine the overall magnitude characmeptec.org

Figure 2. RF calibration setup.

Figure 3. Scalar RF calibration procedure.

teristic.

Scalar calibrations can achieve acceptable results when high-quality components, adapters and cables are used in the system. This helps minimize measurement uncertainty and increase measurement repeatability. However, when compared to a full vector calibration, scalar calibration is less likely to detect changes in impedance match along a signal path.

Figure 3 shows the procedure for performing a scalar RF calibration. The calibration test program is executed and designates the DUT board and tester to perform the path calibration. Then, calibration data is collected by using external equipment (power meter, signal

generator, spectrum analyzer). The collected calibration data is compared with the most recent calibration data and the calibration data is applied - if the deviation is within the specified error range.

If the deviation is out of the error range, inspection and repair are performed and the calibration procedure is repeated.

DUT Socket Calibration RF calibration is performed in two steps, calibration of the DUT Rx signal path and calibration of the DUT Tx signal path. To do this, the design and manufacture of a calibration kit is proposed.

In Step 1, the calibration loss factor measurement environment is derived by the calibration of the DUT Rx Signal SPRING 2022 MEPTEC REPORT | 11

TESTING Path. The calibration kit connected to the pogo RF signal pin should be perfectly matched with the signal trace. To measure the power level of the input signal accurately with a power sensor, a power meter is used to null out the power sensor and then the signal generator and the power sensor should be applied to accurately measure the loss factor for the input signal trace to the DUT. These loss measurements are frequency dependent and must be made at each production test frequency. All calibration loss factors are stored in a file to be applied during production testing.

In Step 2, the calibration loss factor measurement environment is configured to perform the calibration of the DUT Tx Signal Path. Loss factor for all input and output pogo RF signal pins can be measured by using a signal generator and a spectrum analyzer so that the RF signal trace between the input pogo RF signal pin and the output pogo RF signal pin can be accurately calibrated. In addition, it is possible to calculate only the loss factor for the output pogo RF signal pin by substituting the loss factor of the input pogo RF signal pin previously measured in Step 1. Through this process, the loss factor can be calibrated out for the round-trip RF signal path from the load board over each production test frequencies.

To fully calibrate the entire trace up to the DUT, the loss factor for the pogo pins connecting the printed circuit board (PCB) and the DUT must be considered.

At relatively low frequencies, the loss factor for a pogo pin may be negligible and may be excluded from the RF calibration. However, as 5G New Radio (NR) uses the mmWave frequency band, a considerable amount of RF signal loss may occur even in the same type of pogo pins. The pogo pin’s loss contribution is included as a loss element to calibrate.

Since it is difficult to accurately measure the pogo pins losses in the existing socket structure, a new calibration and test socket feature was developed to accurately measure these losses.

There are two basic techniques used to correct for the systematic error terms.

These are short, open, load, through (SOLT) and through, reflect, line (TRL).

The differences in the calibrations are related to the types of calibration stan12 | MEPTEC REPORT

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This uncalibrated test system has unknown signal quality at the input to the DUT (S1’). A common mistake is to simply use equalization in the measure side (M1’) but this occurs after the DUT and it also removes some of the imperfect device performance to be characterized.

In this calibrated test system, the system and fixturing responses have been removed, enabling a known-quality signal to be incident on the DUT (S1). The measurement errors can also be removed (M1).

Figure 4. Test plane movement to the DUT through calibration.

Before System Calibration 28 GHz with ~900 MHz Bandwidth

After System Tx and Rx Calibration 28 GHz with ~900 MHz Bandwidth

Before system calibration: these OFDM frequency response corrections for an uncalibrated system show variations of nearly 7 dB in raw amplitude and 45 degrees of phase shift across a 900 MHz bandwidth at 28 GHz.

After system calibration: the same OFDM response for a calibrated system, showing variations of only 0.2 dB and 2 degrees.

Figure 5. OFDM modulation frequency response before and after calibration.

meptec.org

Calibration enabled the signal generation of a 1 GHz wide signal with an EVM of less than 0.7 percent at 28 GHz. This EVM occurs at the input plane of the DUT. Figure 6. OFDM frequency response before and after calibration.

dards used and how the standards are defined. They each have their advantages, depending on frequency range and application.

A Case Study [2] At 5G carrier frequencies and bandwidths, the test fixture can impose a significant channel frequency response on the test system and adversely affect EVM results. The measurement includes the characteristics of the test fixture and the DUT – making it difficult, if not impossible, to determine the true performance of the DUT. Calibration can move the test plane from the test system connector to the input connector of the DUT (see Figure 4).

Figure 5 shows the results of analyzing the effect of calibration on the RF modulation test for orthogonal frequencydivision multiplexing (OFDM). Frequency response characteristics were compared for a 900 MHz bandwidth (BW) signal at 28 GHz. The upper trace shows the amplitude response with a significant roll meptec.org

off at the upper end of the bandwidth.

The lower trace shows the phase response, which also has considerable variation over the BW. When the calibration is not applied, a large deviation occurred in the magnitude (7 dB) and phase (45 degree) of the frequency response characteristics. When the calibration was applied, the variation in the magnitude (0.2 dB) and phase (2 degree) of the frequency response characteristics was obtained.

Figure 6 shows the demodulation results after calibration for single-carrier 16 quadrature amplitude modulation (QAM) signal. The upper-left trace shows a very clean constellation diagram. This implies that the equalizer response in both magnitude and phase is flat and within specification, indicating that the equalizer is not compensating for any residual channel response in the test fixture. The lower-left trace shows the spectrum with a bandwidth that is nearly 1 GHz wide. The middle lower trace shows the error summary: EVM is approxi

mately 0.7 percent, which is acceptable margin when compared with the device specifications. This system would be ideal for determining a device’s characteristics.

Summary RF calibration is a required process for production testing of semiconductor RFICs that translates into acceptable throughput, margin and yield. Reliable and repeatable calibration ensures consistent results that make it easier to pinpoint product or design problems and thereby minimize delays in development and manufacturing. RF Calibration at Amkor is a vital setup for successful production testing of customer parts. ◆ References [1] “S-Parameters,” Microwaves101.com, Link.

[2] “Comparison of the “pad-open-short” and “open-short- load” deembedding techniques for accurate on-wafer RF characterization of highquality passives,” IEEE Transactions, Volume: 53, Issue: 2, Feb. 2005.

SPRING 2022 MEPTEC REPORT | 13

EDUCATION

Addressing the Workforce Need for the Semiconductor Industry: Microelectronic Engineering Education at Rochester Institute of Technology Santosh K. Kurinec, Fellow IEEE, Professor, Department of Electrical & Microelectronic Engineering Rochester Institute of Technology

Figure 1. A view of the RIT cleanroom facility designed for educating semiconductor engineers; https://my.matterport.com/show/?m= CbLo4VXhbrY

APPLICATIONS OF SEMICONDUCTORS are increasingly globally, with chips being the key components in most new gadgets, devices, and vehicles today, and in potential game-changing applications such as artificial intelligence, quantum computing, advanced wireless networks, and more.

According to the Semiconductor Industry Association, (https://www.semiconductors.org/) the global semiconductor chip industry is expected to reach US $1trillion by 2030.

The semiconductor industry has enjoyed overall growth over the last four decades, however, as the critical dimension 14 | MEPTEC REPORT

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of complementary metal-oxide semiconductor (CMOS) transistors continue to shrink and approach the atomic size limit, the research and development costs to maintain that growth are rising steeply. As a result, there are only a few leading chip manufacturers that continue pushing the advancement of technology nodes at the cutting edge. As a result, it will be continuing progress made in materials, device structures, and fabrication equipment, that semiconductor industry leaders believe will enable the scaling trend of Moore’s Law to be extended by another decade.

There are also emerging market sectors

such as automotive, biotech, health-tech and others, where heterogeneous integration technologies are needed. These markets look for emerging devices with new functionalities including sensing, power management, memory, high bandwidth, low latency connectivity, and more. Fueled by growing demands in different markets, microelectronics manufacturing becomes ever more important and chip supply plays a key role in continuing economic growth.

One of the most pressing challenges is that a significant amount of the manufacturing of semiconductors has moved overseas, and with it, the research, development and meptec.org

Figure 2. RIT sophomore students learning the lithographic process as part of a metal oxide semiconductor transistor fabrication course from design to test.

workforce talent that goes with it. If this trend continues, the US will be in danger of losing its innovative edge in electronics and computers.

Leadership in semiconductor research, design, and manufacturing requires access to the best and brightest scientists and engineers from around the world. In the global race for talent, the U.S. educational system is failing to produce enough workers and students with the necessary STEM expertise. If the US hopes to maintain the dominant market share in semiconductors, and maintain its innovation edge, it is imperative to invest in the education of a highly skilled workforce. The mission is now to dramatically expand the pipeline of talented workers to fill the significant workforce deficits reported by companies worldwide. Currently, most of the K-12 and undergraduate students with interest in science and technology are attracted to AI, to machine learning, and to technology companies like Apple, Google, Facebook, and others that employ software and data science. However, these students fail to recognize that the driver behind these fields and successful companies is the semiconductor industry and the advanced chips being fabricated with microelectronic engineering.

The challenge to developing the workforce for the future of the semiconductor industry is to create an awareness of the field and the career opportunities it offers in our K-12 and undergraduate communities.

A semiconductor engineer is one who is involved with the design and manufacture of semiconductor devices or integrated circuit chips. Specifically, these engineers may be process, product, design, or manufacturing engineers. The educational programs in the Microelectronic Engineering Program at the Rochester Institute of Techmeptec.org

nology (RIT) have been designed to meet this critical need. Microelectronic engineering students need a broad fundamental education in mathematics, statistics, chemistry, physics, optics, imaging, materials science, electronics, and computers. Only a special program can provide the depth and breadth of study needed in all of these areas. Since its inception forty years ago, the RIT Bachelor of Science (BS) program in Microelectronic Engineering (MicroE) has graduated hundreds of top quality engineers for the semiconductor industry.

Today the program is supported by a complete 150 mm CMOS line equipped with i-line and g-line lithography; laser mask writer; diffusion; ion implantation; plasma, chemical vapor deposition (CVD), physical vapor deposition (PVD) and atomic layer deposition (ALD) processes; and device design, modeling and test laboratories.

With the successive advancement of the semiconductor industry, the program has evolved to meet the changes and challenges of the industry. Figure 1 shows a dollhouse view of the RIT’s cleanroom fab facility with a link to get a virtual tour.

The BS degree is a five-year program that consists of laboratory-based courses on IC fabrication, photolithography, thin film processes, design of experiments, chip design, simulation, and testing. Elective courses are offered on various tracks – computer engineering, materials science, advanced logic and memory devices, and heterogeneous integration. The program integrates a minimum of one year Co-op /internship experience, where, after the second year, students alternate school with paid employment in the semiconductor industry. Microelectronic engineering Co-op students are employed across the United States as well as in Europe and the

Pacific Rim. An undergraduate research experience is built into the curriculum in the form of two semester capstone senior design course. The graduating students present their research/design work at the Annual Microelectronic Engineering Conference (AMEC), widely attended by representatives from the industry and academia. Most of the advanced processes, such as high-k dielectrics, silicides, submicron lithography, reactive ion etching, self-assembled doping, and devices like tunnel- and ferroelectric field-effect transistor (Fe FETs), phase change memory, thin film transistors, bipolar junction transistors (BJTs), light emitting diodes (LEDs), solar cells, insulated-gate bipolar transistors (IGBTs), and micro-electromechanical systems (MEMS) sensors have been developed through the undergraduate capstone projects. Figure 2 shows a typical lab class in the cleanroom with a wafer in process and final devices under test.

The success of the BS program led to the development of Masters programs in Microelectronic Engineering at RIT. Unique dual BS-MS programs with Materials Science, Electrical Engineering, and Computer Engineering have been established, as well as a Masters in Microelectronic Engineering that is offered online to allow engineers with traditional engineering / science BS degrees working in the semiconductor industry to enhance their understanding of the semiconductor device physics / fabrication / manufacturing issues. RIT also has a PhD program in Microsystems Engineering in which the graduate students can use the in-house CMOS and MEMs fabrication capabilities in their research.

Created in 1982 to address the workforce needs of the emerging home computSPRING 2022 MEPTEC REPORT | 15

EDUCATION er industry, the RIT BS in Microelectronic Engineering is the only ABET accredited program of its kind in the nation. While many of the original semiconductor companies from the 1980’s have evolved over the past forty years, today’s companies are still looking to RIT for their workforce needs. In the past fifteen years, Micron, Global Foundries, Intel, Northrop Grumman, and AMD have been the top employers of our Co-ops and graduates. A good number of our graduates have gone on to pursue PhD level research at other institutions, have been hired at national labs and university fabs, and some have launched their own start-ups. A sample testimony to the program was given by Dave Kewley, Senior Manager, Mask Technology Programs at Micron Technology, Boise, Idaho, who said “The RIT MicroE program produces semiconductor generalists who perform well in a variety of process, device, and support roles within Micron. They tend to come up to speed in their role and begin to add value faster than their peers from other universities.”

A similar testimony given by Andrew Ryan, Fab Engineer, Intel, Arizona, states “Intel has a long history of recruiting and hiring students from RIT’s Microelectronic Engineering program given how well prepared these students are when they join Intel, demonstrating a much lower learning curve and the ability to contribute in a meaningful way very quickly. They leverage their unique blend of hands-on experience in RIT’s fab and semiconductor/ device theory from school into the ability to make high impact to our business and in many cases go on in their careers to lead some of our most important strategic efforts.”

Reinaldo Vega, an RIT Microelectronic Engineering alum who went on to pursue a PhD at UC Berkeley and is presently with IBM Research as a Senior Engineer, Device Performance Lead Advanced Technology Definition, and an IBM Master Inventor shares “As a student in the Micro-E program, I geeked out on the entire curriculum like a mad scientist in a candy shop. The theoretical and practical knowledge I gained about device physics and process integration put me on par with students who were senior to me during my Ph.D. studies and made it easy for me to hit the ground running when I started my professional career. My Co-op 16 | MEPTEC REPORT

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Figure 3. A roadmap for rapid generation of semiconductor workforce.

experiences taught me real-world skills outside of the classroom and helped me build a professional network early on. The undergraduate senior capstone project tested everything I learned and gave me the opportunity to show what I was really made of. The RIT Micro-E program laid the foundation for everything that I have accomplished since and, if you think American semiconductor technology is already quite advanced, imagine how much further ahead we could be if every American university had a program like this. This program is a diamond in the rough.”

Here is another example of how MicroE graduates move successfully towards higher responsibilities “RITs clean room facilities allowed me to gain firsthand knowledge of the tools, materials and characterization techniques used in semiconductor manufacturing while the coursework gave me fundamental understanding of the devices we were creating.

The experience gained in RITs microelectronics program helped jump-start my career, being able to contribute immediately upon entering the workforce. The Microelectronics BS and MS programs enabled me to connect the dots, solve complex problems faster and coordinate holistic solutions”, says Keith Tabakman Senior Manager, R&D Portfolio Planning, Finance & Operations at GLOBALFOUNDRIES. The challenge of finding qualified workers exists at all skill and education levels, from technicians to doctoral-level engineers. As we look to the future of semiconductor industry workforce, rapid increases in the talent pool will be an attractive option. One way to acceler-

ate the creation of domestic talent is to promote community college science and engineering students to transfer to Co-op based engineering programs after they complete basic science and math courses.

A graduate of the community college science and engineering programs could be out in industry on Co-op only one semester after joining the BS program. Incoming high school graduates will be ready in two years, which is still better than having to wait four years with conventional BS degrees. In addition, while the students gain experience during the Co-op, their financial burden is lowered with the paid internships. Figure 3 summarizes how an investment today in scholarships for AS graduates to move onto the BS program will pay dividends sooner.

One such community college student, now a microelectronic engineer is Brian Novak, currently at Northrop Grumman as an Emerging Technology Process Integration Engineer, who states “I believe that transferring from Hudson Valley Community College (HVCC) to RIT is really what started my career. It introduced me to a wide range of deeper subject matters than what was covered in community college whether in the classroom, hands on in the lab, the research the faculty does or out on co-op. Admittedly I spend more time in a test lab than a cleanroom now - but I am able to do so successfully because of the EE classes that were included under the MicroE umbrella. What differentiates my skill set is that I can feed those results back into the foundry to improve the device at the fabrication level. And, of course, had I never transferred to RIT I would never have developed as deep a passion for learning that led me to obtain meptec.org

my MS as well.”

To sustain and grow domestic invention and production of semiconductor technologies, substantial investments in hard infrastructure (equipment and facilities) is needed to modernize educational curricula and provide research & training facilities. Institutional, industry, and government support have been critical in maintaining and upgrading the RIT Microelectronic Engineering facilities in the past and will be even more critical in the future. We have already addressed the emerging workforce shortage resulting from the continued growth of the industry and foreign competition. In addition, many are predicting that the total number of graduates from US high schools will peak in 2023 and start to decline. These two factors should be driving a nationwide focus on reaching out to our younger generation and for universities to strengthen undergraduate programs with hands-on experiential experiences with an innova-

Figure 4. A MOS transistor cartoon depicting workforce depletion inhibiting supply of talent for the semiconductor industry.

tion focus. It all comes with a large need for a joint societal, governmental, industrial, and academic vision. As we draw the future semiconductor front end, back end, packaging, and integration roadmaps, we must envision the educational roadmap required to achieve these futuristic goals.

Allowing for a little artistic leeway, the challenge as shown in Figure 4 is presented by asking “are we ready to commit the resources to strengthening the field to

enhance the flow of talent from our K-12 institutions to meet the needs of the semiconductor industry?”

On this the 40th anniversary of the launching of the RIT Microelectronic Engineering Program to address the workforce needs of the semiconductor industry, we would be remiss not to acknowledge and thank those industrial affiliates who have brought us to this point, and the alumni who entrusted with their education and now represent the program out in the working world. A special thanks to Dr. Lynn Fuller, the founding Department Head, whose drive and vision brought the program, and many of us the faculty, the success we have enjoyed to date. It is now time to look toward the next forty years and new generations of faculty and students. We are celebrating 40th Anniversary on April 8, 2022 (https://www.rit.edu/ engineering/rit-microe-40th-anniversary) and would welcome interested participants to join. ◆

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SPRING 2022 MEPTEC REPORT | 17

INTERVIEW

Catching Up with Jaspreet Gandhi Director – Advanced Product Development Xilnix

Owing to a very diverse and accomplished association of MEPTEC members, there are many informative, instructional, and entertaining stories to be told. “Catching Up With…” will feature stories from and about our members.

Jaspreet Gandhi (https://www. linkedin.com/in/jasgandhi/) is Director – Advanced Product Development at Xilnix and joined the MEPTEC Advisory Board in 2020. This interview was conducted via email prior to the close of Xilinx’s acquisition by AMD and edited for clarity.

You grew up in the state of Punjab, India where you attended the Punjab Technical University to study Chemical Engineering. What was it like being at a brand-new institution among one of its first graduating classes?

If I recall it right, in 1997 Chemical Engineering was offered in only 2 institutions affiliated to PTU. My college (BCET) was established in 1995 and ours was the 3rd batch graduating in 2001. Those formative years played an integral part in channelizing my interests, behavior development, and lifelong friendships. Access to new labs combined with subjects like mass transfer, CRE (chemical reaction engineering), and petroleum engineering fueled my interest in process engineering. I have vivid memories of college sponsored industry trips to fertilizer, paper manufacturing, soft drink bottling, and power generation plants where we witnessed batch and continuous operations. During my final year, I got the much-coveted opportunity to work at Indian Oil Corporation’s petroleum refinery as an intern 18 | MEPTEC REPORT

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Business fundamentals are the same anywhere and everywhere.

Business models, offerings, and operational execution is different. for six months. I was just blown away by the scale of unit process engineering to run those sky-high distillation columns, reactors, distribution pipelines, flares, feedstocks, etc. all under centralized control. As wonderful the experience was, I don’t recall much about my project work now beyond it was something on fluid bed reactor optimization. Apart from academics, I did take part in extracurricular activities; organized inter college fest, onstage skit performance, and chaired the hostel mess committee. Regular bantering with batchmates/ seniors kept the fun in life while a disciplined learning approach and curiosity propelled me forward.

For your Master’s degree in Material Science & Engineering you went to the University of Cincinnati. How did you pick that program from a world away? What did you learn about people presuming a large change in culture?

I love talking about this story. Right after graduation, I started working as a Process Engineer in a bicycle tire/tube manufacturing company (Ralson India Ltd) where natural and butyl rubber tubes were experiencing chronic yield loss due to punctures eventually delaminating from the brass valves. Several design of experiments (DOEs) were run to no avail.

I started researching on this topic and came across an article in the company library “Rubber to metal bonding by organofunctional silanes” by Prof.

William J. Vanooij from University of Cincinnati. I read it with great interest but didn’t understand all details. I wrote Prof. Vanooij an email explaining our problem to which he responded enthusiastically and our discussion journey started. In his true nature, he was excited to find a solution and offered to send various silane samples for trial. Lo and behold, silane coated brass valves

Professor William Vanooji, ca. 2005 (via KTH Royal Institute of Technology COSI 2005 website)

meptec.org

Your first post-graduate job was with Moen doing materials reliability and compliance testing of kitchen and bath accessories. As consumer plumbing fixtures are a world away from semiconductors, are there things you learned there that are still fundamental to your work in semiconductors?

2006 Moen Design Reliability Lab.

showed astonishing adhesion results such that the tensile testing machine needle made a 360 turn without skipping a beat. Field results after high temperature steam curing matched the lab data with zero punctures. It was a gratifying experience.

The sense of accomplishment, however, was ephemeral after learning the licensing costs for the use of this technology. I was surely disappointed but as they say “Don’t think problem, think opportunity”. I expressed my interest in grad studies to Dr. Vanooij and he encouraged me to apply for Material Science at University of Cincinnati. I had already taken the GRE (graduate record examination) and was in the process of graduate school applications, so the timing worked out great. I arrived in United States on August 17, 2002 with a full scholarship and joined Dr. Vanooij’s research group as a research assistant thereafter. He had me plugged into various areas of organo-functional silane research: from solution chemistry, film analysis to application methods as coupling agents, corrosion protection coatings, to non-stick cookware, and dental implants. My Master thesis title was “Electrodeposition of silanes for corrosion protection of metals” sponsored by American Electroplater and Surface Finisher Society (AESF). I got the chance to publish eight papers under his guidance and presented my work at various conferences. I am indebted to Dr. Vanooij for shaping my professional career as it is today by inculcating critical thinking, innovative mindset, and reach broadening skills. Unfortunately, he passed away in 2012. meptec.org

Definitely. Business fundamentals are the same anywhere and everywhere.

Business models, offerings, and operational execution is different. At Moen I learned about compliance standards, test development, metrics, supplier & product quality, Production Part Approval Process (PPAP), conformance audit procedures, and structured problem solving.

Not to mention budgeting and resource management which is cardinal to any industry (definitely semiconductors) for efficient operations.

Another experience I would like to share is that kitchen and bathroom faucets at Moen were not treated any different for trace metal leaching prevention and had to follow rigorous NSF (National Sanitation Foundation) standards before shipment. In other words, water from a kitchen faucet isn’t purer than a bathroom faucet especially if they share the same distribution line. That said, I still haven’t been able to convince my family to drink water from a hotel bathroom faucet. That’s a story for another day…

Do you like plumbing? Do you tackle plumbing projects at home? (Editor’s note: I hate plumbing. Even when you think you’ve got something right it may start leaking a few hours or days later…)

I don’t. O-ring replacement and silicone caulking have worked for me for minor leaks, but I don’t try big projects anymore due to bad experiences in the past.

I’m happy to call a professional!

How did you make the jump from Moen to Micron?

I moved to Micron to satisfy my inherent desire for technology research and development (R&D). I came across a posting for Materials Engineer at Micron, Boise and applied. I had never heard of Micron before and my only association with Idaho was buying authentic “Idaho potatoes” at Kroger. After the phone interview, Micron was gracious enough to invite me and my wife (newly married) for an onsite visit and paired us with a local realtor to show around Boise. We had mixed feelings about the city of 4-5 exits compared to Cleveland, but the onsite interview, job scope, open dialogue and final offer cleared all doubts.

We moved to Boise in January 2007.

Was there a big culture shock moving from Cleveland to Boise? Bigger than moving from Punjab to Ohio?

Boise didn’t appeal to us right away but

2016 Inotera Taiwan.

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INTERVIEW

slowly became an acquired taste. Small city nestled in the foothills, wonderful gregarious localities, green belt & outdoor activities a stone throw away, and stress-free access to everything provided a big respite versus big city hustle for sure. The US has the commonality factor of similar language, culture, and infrastructure throughout such that subtleties didn’t create a big culture shock. However, moving from Punjab to Ohio was indeed a realization of something totally different as seen in Hollywood movies.

How big was the mindset change from “regular” Advanced Packaging (higher performance materials, etc. for a single die) to 3D stacked die for the Hybrid Memory Cube (HMC)?

While wirebond (WB) and hybrid mix of flip-chip and WB based 3D stacking of NAND and DRAM dies was in high volume manufacturing (HVM) in 2007, the concept of 3D integration for HMC was a paradigm shift in technology development mindset. From through-silicon via (TSV) formation to fine pitch microbumping, thin wafer handling, backside TSV reveal, particle control, front end FAB based unit processes, control systems, key performance indicator (KPI) rigor, metrology/inspection tools, thin die warpage, thermo-compression bonding quirks, thermal management, to you name it; challenges were at every corner.

We experienced numerous failures but strong resiliency and resolve combined with innovations, management support, and the final goal kept the momentum alive. If I were to summarize the amazing teamwork of eight years, I would rename Hybrid Memory Cube as “Hail Micron Collaboration”. I am extremely proud to be part of the development and qualification journey of the HMC. When you first started working on the Hybrid Memory Cube did you think it was a crazy idea? Was the initial process challenges overwhelming? What enabled the team to stay focused to deliver a product that actually works?

I started at Micron in January 2007 and got involved in HMC packaging materials development by late 2007. I didn’t 20 | MEPTEC REPORT

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2016 SPIL SLIT Team.

2019 SPIL Team Recognition.

have much experience with packaging development, so to me it was a new and exciting project. I recall one of my colleagues Dr. Yangyang Sun stacked the very first TSV die manually with her steady hands. I think her placement accuracy could match that of Datacon’s and others die stacking machines of the world at that time. Overwhelming process challenges would be an understatement where TSV voiding, copper (Cu) pumping, Cu silicide formation, wafer/ die breakage, resist & microbump idiosyncrasies, TSV toppling, and zero to poor yield were regular sights of any day.

What kept our focus was the collabora-

tive belief and dedication to the mission: i.e. to break the memory wall as there was no competitive product (High Bandwidth Memory & Wide IO came later) with lots of customer excitement.

Was there anything that drove moving from Micron to Xilinx where you are now?

In 2015, Micron was in the process of transferring advanced packaging R&D operations to Asia. The choice was between an internal move to another functional area or an expat assignment to Asia. For family reasons combined with an avid interest in advanced packaging, meptec.org

we chose to move to the San Francisco Bay Area. How I ended up at Xilinx is another interesting story, thanks to Dr. Suresh Ramalingam. Let’s save that for another time.

When you arrived at Xilinx even though the Virtex 7, the “poster child” for 2.5 D integration had been shipping already, there were and still are plenty of advance packaging challenges. What so far have you found to be the most challenging? And what has been the most satisfying to work on?

At Xilinx, the range of product offerings and application spaces is so mind boggling that it feels like working in multiple startups at the same time. I had worked on die sizes ranging from 0.25 mm2 to approximately 100 mm2 before.

But Xilinx was a completely different ball game, with devices (die sizes) ranging from ~ 50 mm2 to almost 2600 mm2 offered in myriad packaging platforms from monolithic to multi-chip modules (MCM), 2.xD, fan-out (FO), 3D, and photonics. We have worked on previously insurmountable challenges in package architecture, design enablement, chippackage-board codesign, signal/power deliver network (PDN) routing, heterogenous integration, thermo mechanical chip package interface (CPI), board level reliability, etc. Notice I didn’t even mention the processes yet. And don’t get me started on substrates and HBM sourcing which respectfully will each need a chapter of their own. That’s how different the world at Xilinx is for me. I have enjoyed each and every project working with the smartest and most humble team members. Knowledge and learning evolves so do the challenges, hence the most difficult problem from yesterday is the gratifying solution of today with the best yet to come.

How does working at and doing packaging development at Xilinx, a fabless company which outsources its manufacturing, compare with working at Micron which is an Independent Device Manufacturer (IDM) and does almost all of its own manufacturing? meptec.org

Celebrating InFO with Memory on Substrate (InFO_MS) project milestone with TSMC team in Hsinchu, Taiwan in 2019in Hsinchu, Taiwan in 2019.

“Highlighting” advanced technology at ASE Global’s booth at IEEE ECTC conference 2019.

Micron as an IDM is a legacy example of vertical integration with memory architecture, design, and process under one roof (figuratively) compared to Xilinx which is heavily product architecture and system design centric with manufacturing processes outsourced to Asia. They both have their pros and cons but I feel blessed to have experienced both worlds.

I feel empathetic towards foundry/ outsourced assembly and test (OSAT) struggles while simultaneously balancing the ambiguity of multiple product design needs. The experience has helped tremendously to develop a relatively holistic view of technology and product requirements, problem articulation, and engineering of efficient solutions.

As Director – Advanced Product Development at Xilinx you are working on next generation products.

Have you seen anything you would characterize as a totally crazy idea?

Is it mostly variations on the 2/2.5/3D concept or are there things being worked on that are even bigger disruptions?

Absolutely. Disaggregation is stimulating innovation in front end 3D and 2.5D/3D packaging platforms to meet the insatiable bandwidth (BW) density and reduced energy density demands. Think of compute density increasing by >25X in the same device footprint and intra-chip BW increasing by >50x between device genSPRING 2022 MEPTEC REPORT | 21

INTERVIEW

erations. Such a visionary goal cannot be achieved by traditional thinking or even a basic heterogenous integration mindset.

At the integrated circuit (IC) level how to partition the design? The die level, intellectual property (IP), macro or IP splitting, how to place & route to ensure no interference with power delivery, PDN efficiency, and signal routing without compromising EM/IR drop limits all need to be solved at the same time.

Will chip-package-board codesign be enough or customized software solutions be required to adapt to current profiles and switching duty cycles? Once that’s done, how do you dissipate power from such high wattage device? These are just top of the mind items where system level thinking must triumph.

If you start peeling the onion there are challenges in structural & functional test design for robust known good die (KGD), defect tolerance, security, performance indicators, volume diagnosis, derivative products, manufacturability, and many more areas. Design enablement & third party chiplet sourcing & integration will create additional decision vectors in this equation.

Another disruption is on the chippackage optics front where DARPA PIPES program aims to achieve edge BW density of 2 Tbps/mm (100 Tbps per package) at 1 pJ/bit versus the standalone pluggable transceivers of today “only” achieving ~22 Gbps/mm at 30 pJ/ bit. Leaving the electrical-photonic chip design & fiber coupling to other experts, rainbow supply chain management, hybrid packaging architecture, mechanical design, and process integration challenges each individually are enough to keep several engineers fully consumed.

Do you often have to either validate or dismiss crazy ideas? If so, any advice on how to do so without upsetting the ‘genius’ who came up with the idea?

I have spent most of my career in development which requires novelty and crazy ideas. That does not mean every idea is worth pursuing. Filtering out goofs is a must while using critical thinking, engineering experience, and judgment 22 | MEPTEC REPORT

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- Upfront system level considerations to ease chip-package-board signal & PDN routing.

With being an inventor on over eightythree granted patents and numerous technical publications, how do you keep the details clear in your own mind? Do you start thinking about ‘new ideas’ only to find them already covered in your prior patent claims?

Recognition of 50th career patent in 2019

by Victor Peng, CEO of Xilinx.

to vet the deserving ones before further (formal) validation. Active listening and being empathetic to other person’s perspective often helps followed by a reasonable explanation when it is necessary to be dismissive.

If you start peeling the onion there are challenges in structural & functional test design for robust known good die.

If you could get IC designers to integrate or understand one new concept based upon what they always “get wrong” or creates the biggest packaging challenge today, what would it be?

Life would be easy if there was just one big item they miss. How about three?

- IC floor planning must account for packaging thermo-mechanical challenges - Design interoperability between different packaging design and characterization platforms

I feel fortunate to be surrounded with really smart people with lot of zeal and inspiration that stimulates the gray matter. Another trait that has helped me is not to shy away from asking questions but not to ask at the level of pestering either. That’s where I do the homework to connect the dots. If it is still not clear, only then do I resort to subject matter experts for the most distilled information relevant to the problem we are trying to solve.

Continuous learning helps maintain the clarity further. New ideas often come by serendipity while working on a totally unrelated problem. A potential link pops up or forced thinking (thought channeling) enabling dissecting the problem to fundamentals. The majority of the time it is a collaborative effort with enhanced claims. That said since history repeats itself, so can the ideas with a different manifestation as part of the solution.

What do you like to do in your nonwork time?

Non-fiction reading, running, listening to Punjabi music, and partying with family and friends.

Do you like to travel? If so, where is your favorite place to visit? Any special trips that you are thinking of once travel is less restricted as part of the “new normal”?

I have visited four of the Hawaiian Islands. Kauai has been my favorite because of its small size, dramatic transitions, and natural beauty. I would like to visit Thailand one day just to try their authentic food, Maldives to experience over water bungalows, and New Zealand for its scenic splendor as depicted in Lord of the Rings. ◆ meptec.org

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