MEPTEC Report Winter 2020

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

Volume 24, Number 4

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Thermal Management Management Thermal ofICs ICsDuring DuringTesting Testing of

TOOHOTTO TEST

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The power consumptionpage 11

of Artificial Intelligence (AI) and other advanced computing devices has created significant thermal test challenges, including high-power delivery and large-capacity cooling.

Extended Analytics to Accelerate Time to Quality Please submit presentation abstracts by Across End-to-End Value Chain December 18, 2020. Join us for this interactive, live, page 12

WWW.MEPTEC.ORG

cross-functional discussion.

Die Crack Prevention and Detection in Advanced Packaging page 15

Challenges of Advanced Packaging Failure Analysis page 18

Interview - Catching Up with Jeff Demmin page 25

INSIDE THIS ISSUE

3

UP FRONT We are on the verge of saying goodbye to 2020.

And not a moment too soon for many of us!

4

CALL TO ACTION Can measures be taken now to avoid a shortage of mission critical FPGA to keep the balance of peace in the World?

5

MEMBER NEWS from NXP, Kyocera, Intel, Aehr Test Systems, SEMI, Mentor, DECA, Indium, Disco and more.

9

COUPLING & CROSSTALK Without the in-person networking the main reason to attend a virtual event is the content – i.e. the presentations.

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MEPTECReport

UP FRONT The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council 141 Hewitt Street, Summerville, SC 29486 Tel: (650) 714-1570 Email: bcooper@meptec.org Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown Sales Manager Gina Edwards

MEPTEC Executive Director Ira Feldman

MEPTEC Advisory Board Board Members Dave Armstrong Advantest Ivor Barber AMD Calvin Cheung ASE (US) Inc. Jeff Demmin Keysight Technologies Abram Detofsky Intel Neal Edwards AMD Jaspreet Gandhi Xilinx Ravi Mahajan Intel Emeritus Advisors Seth Alavi Sunsil Joel Camarda Anna Gualtieri Elle Technology Phil Marcoux PPM Associates Mary Olsson Herb Reiter eda 2 asic Consulting In Memoriam Ron Jones

Contributors Zoe Conroy Cisco System Ira Feldman Feldman Engineering Corp.

Woo Young Han Onto Innovation Martin Hart TopLine Corporation Chin Jiann Min Advanced Micro Devices (Singapore) Yuri Mitnick Cisco System Bernice Zee Advanced Micro Devices (Singapore)

MEPTEC Report Vol. 24, No. 4. Published quarterly by MEPCOM LLC, 141 Hewitt Street, Summerville, SC 29486. Copyright 2020 by MEPCOM LLC. All rights reserved. Materials may not be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members of MEPTEC. For nonmembers, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere.

For advertising rates and information contact Gina Edwards at 408-858-5493.

Goodbye 2020!

Ira Feldman Executive Director, MEPTEC

We are on the verge of saying goodbye to 2020. And not a moment too soon for many of us! Even the most pessimistic among us fully expect 2021 to a much better year. Yes, the winter may not be kind to some. But hope springs eternal especially with glimpses of ‘normalcy’ in parts of the world this fall.

The MEPTEC Advisory Board has been working on events and programming for 2021 being realistic in our plans. We very much prefer to meet in person here in Silicon Valley. However, the timeline for when we can again do so safely and comfortably is still unknown. Therefore, for now, we are continuing our slate of virtual events.

We are pleased to announce “Too Hot to Test” as our first virtual event for 2021 on February 9 and 10. Power consumption of advanced computing devices, especially those for artificial intelligence and machine learning, have skyrocketed. These are challenging the industry’s ability to safely and economically test such devices due to the high thermal load. This free event will take a cross-functional look at the problem and possible solutions. Please watch for email announcements and check meptec.org for additional details and registration as they become available.

The Semiconductor Industry Speaker Series will continue as a twicemonthly webinar in 2021. We will be covering a wide range of topics including 5G, optical communications, heterogenous integration, new materials, and more.

Not only will be talking technology but we will also have insightful market analysis throughout the year. Please join us for these webinars on alternate Wednesdays at 11:30 am Pacific time. And if you are interested in presenting at a future webinar, please let us know.

Lastly, a little end of the year business. MEPTEC is member and corporate sponsor supported organization. If you have not already joined or renewed for the year, please do so now. If your company is interested in sponsoring our programs, please let us know as corporate sponsorships allow us to provide the virtual events free of charge. For assistance with membership or sponsorships please contact Bette Cooper (bcooper@meptec.org).

I look forward to hearing your suggestions and feedback as to how MEPTEC can best serve you. Please don’t be shy!

Stay safe and healthy!

Ira Feldman Executive Director, MEPTEC ira@meptec.org +1 650-472-1192

WINTER 2020 MEPTEC REPORT | 3

CALL TO ACTION

Does the FPGA Industry Face Peril? Pt. VI Martin Hart TopLine Corporation

Ceramic LGA

PART V OF THE FALL 2020 MEPTEC Report titled “Call to Action” cited that multiple subcontractors are queued and ready to provide column attachment services for aerospace and defense grade Field Programmable Gate Array (FPGA) components. The benefit of that capability may not be immediately mobilized.

Let’s now examine a potential new risk to defense grade and radiation hardened (RADHARD) FPGA devices arising from the acquisition of XILINX by AMD. AMD Acquisition of XILINX has Unintended Consequence: The Potential to Disrupt World Peace XILINX provides roughly half of the Free World’s defense grade FPGA devices, including RADHARD FPGA for aerospace. Typically, defense grade and RADHARD FPGA are built to survive harsh environments. They are generally ceramic packages with solder column terminals, called Column Grid Arrays (CGA), rather than Ball Grid Arrays (BGA) using solder ball terminals. The total market for rugged, defense grade and RADHARD FPGA devices is tiny compared to Commercial Off-the-Shelf COTS devices. At the time of this writing, AMD has announced its acquisition of XILINX. Suddenly the continuing supply of aerospace and defense grade FPGA becomes uncertain. Here’s why: AMD has publicly cited reasons for acquiring XILINX to strengthen its combined offering of high performance computing for data centers. AMD said that it expects to achieve operational efficiencies of $300 million within 18 months after closing the transaction primarily based on synergies in costs of goods sold, shared infrastructure and through the streamlining of common areas. That’s fancy talk for AMD’s intent to offer early retirement, scale-back redundant operations, lay-off employees, 4 | MEPTEC REPORT

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Before Columns are Attached

Column

Solder columns are required instead of solder balls to make FPGA

and possibly shut down unprofitable product manufacturing. The ramifications of AMD’s acquisition of XILINX will become clearer in 2021, as key managers and technical staff most familiar with defense products take early retirement from XILINX, leave the industry, or seek greener pastures with competitors. The erosion of know-how will also contribute to increased risk in the continuation of supply within the defense and aerospace component sectors. Rest assured that after the acquisition is completed, AMD will focus on ferreting out and possibly eliminating divisions and teams that do not fit the combined entity’s vision.

The aerospace and defense product line most likely will not fit AMD’s future vision. The defense and RADHARD FPGA product group is burdened with costs and complexity to comply with the exacting requirements of the Defense Logistics Agency (DLA) which regulates and certifies products before being approved to be on the Qualified Manufacturer List (QML-38535). AMD may scale back or spin-off its line of defense related products. There is a potential to disrupt downstream customers who rely on defense grade FPGA for black box builds and systems that keep warfighters flying and warships sailing if AMD elects to reduce costs by exiting the military products market.

Extenuating Circumstances A secret that is hiding in plain sight is that all major manufacturers of aerospace and defense grade FPGA components rely today on a single source subcontrac-

FPGA

After Columns are Attached

tor to provide copper wrapped column attachment services. This is the final step in assembling FPGA. Solder column attachment is the “Achilles Heel” in the assembly process of defense grade FPGA devices. New builds of military grade FPGA will come to a screeching halt, should a series of unplanned crises hit the current monopoly subcontractor of copper wrapped solder column attachment services. The lack of a fifty-cent solder column can bring the entire FPGA industry to its knees.

Ignoring a weakness in the Supply of Solder Columns Original Device Makers (ODM) that make military grade FPGA are aware of the lack of redundancy and questionable sustainability in today’s supply chain of copper wrapped solder columns. This begs the most important question: Will the aerospace and defense industry be assured of a stable supply of solder column attachment services five years from now? Continuation of supply of defense grade FPGA is not guaranteed.

Conclusion Can measures be taken now to avoid a sudden shortage of mission critical FPGA to keep the balance of peace in the World Order? This can be answered in the affirmative only if makers of defense grade FPGA elevate the need to act in securing and qualifying a second source capability to attach solder columns sooner, rather than later. Our next installment of Call to Action outlines an easy to follow plan. ◆ meptec.org

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MEMBER NEWS

NXP Announces a Complete Suite of Radar Sensor Solutions that Can Surround Vehicles in a 360-degree Safety Cocoon NXP SEMICONDUCTORS, the leader in automotive radar, has announced a complete suite of new radar sensor chipset solutions that can surround vehicles in a 360-degree safety cocoon and enable the identification and classification capabilities of imaging radar. The solutions, comprised of new NXP radar processors and 77GHz transceivers, offer carmakers flexible and scalable configurations that address NCAP requirements for corner and front radar applications while offering 4D imaging radar’s first commercially viable path to volume production.

NXP is enabling the ongoing evolution of radar with 2 new solutions.

New NXP Imaging Radar Solution Imaging radar is a groundbreaking technology that significantly enhances radar’s performance. It delivers multi-modal capabilities and extends today’s available L2+ features, like highway pilot and lane change assistance, by offering superresolution images for precise environmental mapping and scene understanding.

The combination of NXP’s new purpose-built S32R45 radar processor and the TEF82xx transceivers delivers the fine angular

resolution, processing power and range required to not only distinguish between small objects in the distance, but also to accurately separate and classify vehicles and vulnerable road users like cyclists or pedestrians in crowded environments.

NXP Scalable Corner and Front Radar Solution Targeting cost-effective and small footprint NCAP corner radar requirements for high volume vehicle production, the NXP solution also provides scalability for long-range front radar and advanced multi-mode use cases like simultaneous blind-spot detection, lane change assistance and elevation sensing. These advanced applications require extended range and significantly enhanced angular resolution for detecting and clearly separating multiple objects simultaneously and pro-



CUSTOMERS RATE FORMFACTOR ONE OF THE BEST SUPPLIERS IN THE INDUSTRY

vide the ability to surround the car in a 360-degree safety cocoon. NXP’s new S32R294 radar processors combined with the NXP TEF82xx transceivers provide a scalable solution that helps carmakers address both NCAP and advanced corner radar as well as long-range front radar sensor requirements in an effective way, while allowing tailoring for individual use cases.

As the first company to broadly deliver 77GHz RFCMOS radar technology in high volume mass production and as the developer of the groundbreaking S32 automotive processing platform, NXP stands alone in helping its customers optimize their total cost of ownership with maximum scalability and re-use across different radar systems, thereby optimizing their own R&D efficiency.

Get more information at www.nxp.com. ◆

Aehr Test Receives $4.3M Order for Initial FOX-XP™ Test Cell Aehr Test Systems, a worldwide supplier of semiconductor test and reliability qualification equipment, has announced it has received an initial $4.3 million order from a new customer that is a supplier of sensors to a major mobile device manufacturer consisting of a FOX-XP™ production test and burn-in system, a set of DiePak Carriers®, and a FOX Automated DiePak loader/unloader for a new high-volume application for production test and burn-in of mobile sensors.

Shipment of the initial test cell is expected during Aehr’s fiscal third quarter ending February 2021. Aehr expects follow-on capacity orders from this customer later in the current fiscal year for additional test systems, DiePaks, and DiePak loaders.

For more information, please visit Aehr Test Systems’ website at www.aehr.com. ◆ meptec.org

FORMFACTOR, INC. has once again been named a 10 BEST and THE BEST Supplier in VLSIresearch’s annual customer satisfaction survey in three categories; 10 BEST Focused Suppliers of Chip Making Equipment, THE BEST Suppliers of Test Equipment, and THE BEST Suppliers of Test Subsystems.

The survey includes the feedback of worldwide semiconductor manufacturing companies, rating suppliers in 14 categories, and measuring in each – supplier performance, customer service and product performance. www.formfactor.com



DYCONEX AG ORGANIZATIONAL CHANGES

DYCONEX AG has announced organizational changes in the Operations Division.

Over the past eight years, DYCONEX AG has been able to implement various technical and organizational improvements in the Operations Division under the leadership of Stephan Messerli. The successful implementation of several investments under his guidance increased capacity significantly. Stephan will now be replaced in his position as Vice President of Operations by Dr. Jonas Kottman.

His tasks include increasing capacity, implementing further yield improvements, transferring a wide variety of innovative products into serial production and a closer collaboration within the MST Group. www.mst.com

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WINTER 2020 MEPTEC REPORT | 5

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MEMBER NEWS

KYOCERA to Construct New R&D Center in Kirishima City, Kagoshima, Japan



VLSI RESEARCH’S SEMICONDUCTOR ANALYTICS REPORT

Semiconductor sales went into their normal December dive, dropping more than 20% w/w. Yet sales were still above September’s peak. The 4Q20 Semiconductor Sales Nowcast slid to +11%. IC Highlights: Focusing on the overall IC picture this week, 13-week MAs show a classic run to the holidays, with virtually no discernable impact from COVID other than the flat summer. NAND is closing out the year as the highest growth segment. Analog & Power displaced DRAM last week, with Auto and Logic following. Semiconductor Supply & Demand: The week’s status tightened, as the 4Q Nowcast for DRAM jumped to Shortage. NAND moved to tight for the week, while Foundry and OSAT stepped down a class. Out-of-Sample Disruptors: Inflation >4% and a rise in Interest Rates was added with a target horizon of 2022. Electronics’ Prices are slipping as holiday sales and a slowing economy kick in. www.vlsiresearch.com

PALOMAR REACH AGREEMENT

MRSI SYSTEMS, LLC and PALOMAR TECHNOLOGIES, INC. have jointly announce they have reached a confidential agreement that settles all litigation currently pending between the companies.

All terms of the settlement are confidential. This settlement ends the intellectual property disputes between the companies with respect to all currently existing product lines.

6 | MEPTEC REPORT

KYOCERA CORPORATION HAS ANNOUNCED it will begin construction of a new research and development center in January 2021 at its Kokubu campus in Kirishima City, Kagoshima, Japan.

Kyocera has executed a location agreement with the mayor of Kirishima City for the new R&D center, which will focus on new innovations in the fields of information and communications, environmental preservation, and smart energy.

The Kokubu campus is already an innovation hub and site of three strategic R&D groups: Kyocera’s Monozukuri R&D Laboratory, which focuses on advanced material technologies; its Production Technology Division, focusing on manufacturing process innovation; and its Analysis Center, which

develops simulation and evaluation technologies.

R&D programs at the campus currently include 5G smartphone technologies, electronic and semiconductor components used in IoT devices, and key components for new smart energy technologies, such as cell stacks for Solid Oxide Fuel Cells (SOFCs). Intellectual property developed there has found a wide range of other applications as well, in the automotive, aerospace, medical and healthcare fields.

Kyocera will position the new facility specifically as an incubator for open innovation, sharing technical information for human resource development, and networking with inventors outside of Kyocera. ◆

Intel and Consilient Join Forces to Fight Financial Fraud with AI

 MRSI AND

palomartechnologies.com

New facility at Kyocera Kokubu Campus will expand R&D speed, capabilities

◆

CONSILIENT, A NEWLY formed company dedicated to establishing a next-generation system for anti-money laundering and countering the financing of terrorism (AML/ CFT), launched a new secure, federated learning platform powered by Intel® Software Guard Extensions (Intel® SGX).

The artificial intelligence (AI) platform aims to prevent financial crime and enable secure collaboration among financial institutions while helping to protect privacy and secure data.

According to the United Nations, between 2% and 5% of gross domestic product (GDP) is laundered globally

WINTER 2020

every year, which amounts to $800 billion to $2 trillion.

Recognizing the need to move beyond a manual and fragmented monitoring system, Consilient built an intelligent, collaborative and always-on solution that leverages federated learning and Intel SGX to detect financial fraud.

By automating this process through federated learning, access to multiple datasets, databases and jurisdictions are encrypted without ever revealing the data or sensitive customer information to the different parties involved.

Federated learning is a privacy-preserving machine

learning (ML) technique and confidential computing model that enables AI training without centralizing data. Consilient has created a behavioral-based, ML-driven platform that runs on its DOZER™ technology.

ML models can be trained across multiple datasets to detect and analyze “normal” and “abnormal” patterns that humans and most current technologies cannot. This allows participating institutions, authorities and regulators to collaborate while uncovering and managing systemic risks more effectively, efficiently and sustainably without putting private data at risk. ◆ meptec.org

Third-Quarter 2020 Global Semiconductor Equipment Billings Surge 30% Year-Over-Year, SEMI Reports GLOBAL SEMICONDUCTOR EQUIPMENT BILLINGS surged 30% year-over-year and rose 16% to US$19.4 billion from the prior quarter, SEMI announced in its Worldwide Semiconductor Equipment Market Statistics (WWSEMS) Report. SEMI and the Semiconductor Equipment Assoc. of Japan (SEAJ) gather the data from more 80 global equipment companies that provide monthly reports.

The SEMI Equipment Market Data Subscription (EMDS) provides comprehensive market data for the global semiconductor equipment market. A subscription includes three reports: 1) Monthly SEMI Billings Report, a perspective on equipment market trends; 2) Monthly Worldwide Semiconductor Equipment Market Statistics (WWSEMS), a detailed report of semiconductor equipment billings for seven regions and 24 market segments, and 3) SEMI Semiconductor Equipment Forecast, an outlook for the semiconductor equipment market.

For more information or to subscribe, please contact the SEMI Industry Research and Statistics Group at mktstats@semi.org. More information is also available online. ◆

Mentor Adds DECA Technologies to Growing Mentor OSAT Alliance for High Density Advanced Package (HDAP) Designs MENTOR, A SIEMENS business, today announced that DECA Technologies has become the latest member of Mentor’s (outsourced assembly and test) OSAT Alliance – a program to help drive faster adoption of new, high-density advanced packaging (HDAP) technologies like 2.5D IC, 3D IC and fan-out wafer-level packaging (FOWLP) for customer integrated circuit (IC) designs. The Alliance enables mutual customers to better leverage Mentor’s proven HDAP flow to quickly bring to market innovations for internet of things (IoT), automotive, high-speed communications, computing and artificial intelligence (AI). DECA is supporting this objective by making available to Mentor and DECA’s mutual customers a new assembly design kit (ADK) for DECA’s M-Series advanced fan-out wafer-level package (FOWLP) process to be used with Mentor software. meptec.org

Through the alliance, the two companies are offering a comprehensive tool flow that gives mutual customers the ability to create and evaluate multiple complex IC package assemblies and interconnect scenarios in an easy-to-use, data robust graphical environment prior to and during physical design implementation.

The DECA ADK provides mutual customers with a verified sign-off fabrication rule deck for Calibre 3DSTACK that will enable companies to converge on sign-off faster and with less verification cycles.

Mentor continues to spearhead the EDA industry by enabling the entire ecosystem to adopt new technologies via its OpenDoor program and the various alliances that fall under the program.

For more information about Mentors OSAT Alliance program please visit https:// www.mentor.com/company/ partner_programs/. ◆

Indium Corp’s Proven Microdispensing Paste Recommended by NSW

INDIUM CORPORATION’S NEWEST jetting and microdispensing solder paste, Indium12.8HF, has been officially recommended by NSW Automation for use with their newest microfluid dispenser, SD1.

The SD1 Automated Intelligent Micro-dispenser dispenses at a minimum of 80µm, the smallest solder dot in the world, with gaps as small as 20µm, while downsizing the equipment footprint up to 48%. Thanks to the development effort between the two companies, Indium12.8HF is the recommended product to be used on this system to achieve those fine dots and lines. This no-clean, halogen-free solder paste helps deliver exceptional microdispensing performance in standalone applications, such as system-in-package (SiP), jetting into cavities, stencil-replacement, shield-attach, and microBGA. It also complements the stencil printing of Indium Corporation’s best-selling solder paste, Indium8.9HF. Additionally, Indium12.8HF offers a flexible metal load (78-85%) to provide optimal dispensability; Fine-powder adaptability: Type 5, Type 6, Type 7; Has a clear residue with minimal flow-out; Significantly reduces head-in-pillow (HIP); Eliminates or significantly reduces graping; and minimizes reflow spatter.

To learn more about Indium’s new jetting and microdispensing paste visit https:// www.indium.com. ◆

Newly Developed Die Inspection Unit DIS100 Achieves Fully Automatic Quality Management After Dicing DISCO CORPORATION HAS DEVELOPED DIS100, a unit that picks up die from the wafer after dicing and measures die thickness, chipping, backside surface roughness, and die strength* fully automatically. Efficient and highly accurate measurement is achieved by automating all of the existing manual processes.

In addition, DIS100 records measurement data. Therefore, it also improves traceability, as required in quality audits of automotive devices.

R&D Background From a safety perspective, quality management is especially important for automotive devices, for which demand is increasing due to the development of selfdriving and electric vehicles. In addition, high die strength is required for die used in memory devices, which are continually becoming thinner with storage capacity becoming larger.

Because there was no equipment to automatically measure die thickness, chipping, backside surface roughness, or die strength, there were issues caused by manual operation, including measurement variation and high inspection labor costs.

DIS100 achieves stable fully automatic die strength measurement and efficient die quality management.

DIS100 Product Features Fully automatic inspection from die pick up to die strength measurement After the user simply sets a frame cassette to DIS100 after dicing, DIS100 automatically picks up the designated die, measures die thickness, chipping (optional), backside

surface roughness, and die strength (breakage test), and monitors the conditions when the die breaks using a high-speed camera (user-specified).

DIS100 Work Flow 1. Sets cassette 2. Picks up die 3. Sidewall inspection: thickness measure ment, chipping measurement (optional) 4. Backside inspection: surface roughness measurement (optional) 5. Die strength measurement and condi tion monitoring using a high-speed camera (user-specified) For more information please visit the DISCO website www.disco.co.jp. ◆ * Die strength - The largest stress when the die is bent until it breaks. The higher the die strength is, the less die breakage occurs, which contributes to improved yield and reliability for the final devices.

Saying Goodbye to a Good Friend Ron Jones

March 30, 1944 - October 23, 2020

Ron Jones of Saratoga, California passed away on October 23rd of this year. Ron contributed his technical expertise as a member of the MEPTEC Advisory Board for over fifteen years, as well as publishing a column that served-up Industry Insights in the MEPTEC Report for many years.

Ron was CEO and Founder of N-Able Group International, launched in 1996 after spotting a gap in services available to meet a growing need for highly skilled and experienced resources across the burgeoning semiconductor industry. Prior to NGi, Ron was CEO of Thai Microsystems in Bangkok, President of Indy/Olin Interconnect Technologies in California, Corporate VP of Worldwide Operations/GM at Amkor Technologies in Korea, and VP of Operations at RF Monolithics in Dallas. Ron also spent 15 years at Texas Instruments in various operational management positions.

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meptec.org

COLUMN COUPLING & CROSSTALK

By Ira Feldman Electronic coupling is the transfer of energy from one circuit or medium to another.

Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought-provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Competing for Attention As my days “Zoom away”, I continue to think about what virtual events should be. I have hit saturation – not to mention a little bit of dread – with run-of-the-mill virtual events which attempt to simply replicate in-person events online. I try hard not to channel my “inner Andy Rooney” and complain simply to complain. However, after producing over 100 virtual presentations with more than 75 hours of content this year for organizations who have made the virtual pivot, I do have strong feelings about what makes a great virtual event.

What many organizers fail to remember is that we all live in an “Attention Economy”. The most precious resource is someone’s attention! Smartphone applications, especially “social media” platforms, are engineered to capture our attention. So, we spend increasing amounts of time using a given app. The designers of these applications have a vested interest in increasing each user’s engagement since it enables their company to serve up additional highly targeted advertising. Designers use every psychological “lever” possible including the same “tricks” that encourage gambling.

As discussed in my prior column, successful virtual events must be different than in-person events. Without the in-person networking the main reason to attend a virtual event is the content – i.e. the presentations. At an in-person event the technical presentations are the justification for deciding to attend and obtaining corporate approval even if the attendee has other unstated objectives. meptec.org

However, at a virtual event the content is the sole reason to participate so it must be strong enough to stand alone.

In-person events have a much higher cost bar than virtual events (registration fees, travel expenses, and travel time are major factors). Obviously local events are easier decisions to make than international events in far-away cities, since all that is required is a short drive from home, a modest registration fee, and limited time away from your desk.

However, the greater the cost of attending - far from home or at a difficult to reach place - the greater the desire to maximize participation once you arrive.

This is especially true with the fallacy of sunk cost. After one spends considerable time and/or money to attend, it appears better to maximize one’s time at the event engaging with others. It’s pretty

What is missing in many of the virtual presentations I have seen is the preparation, care, and respect for the audience that is expected from a live presentation. rare for someone to fly to a conference, decide it is not a good fit, and change their flights to return home right way.

Sometimes people may return a few hours or a day early but a wholesale change of plans is rare due to an incorrect analysis based upon sunk costs not opportunity cost. Unfortunately, I’ve seen plenty of “parallel processing” where people are working or playing on their laptops while a less than interesting presentation is being given. Or sometimes attendees will ‘hide’ in their hotel rooms to do email or conference calls only to make an appearance at networking and mealtime.

A virtual event upends this entire paradigm even if the entire program is live. The ‘attendees’ can choose when to

tune in or otherwise “connect” to the program. Running late? No problem - connect when you can. Got something more urgent to do? No problem - connect later.

This is made easier with the knowledge that a live program may be recorded for later viewing at one’s leisure. However, how many people really take the time to watch later? Maybe we need to remember this is about work and not ‘leisure’?

Many attendees also admit to working on other things on their computer paying “half” attention to the material being presented virtually - just like virtual conference calls. Lastly, when they are no longer interested or have more urgent things to attend to viewers simply drop off the event. This carries a real danger that in-person events do not have: when there is a weak presenter or a presentation of lower interest in a session many online viewers may disconnect versus waiting to the end of the session. Out of politeness, fear of missing out, sunk cost, or other reasons, few people leave an inperson presentation session due to lack of interest. Leaving mid-session is usually compelled by other issues. Channel surfing in live presentations is much harder than a simple click (starting with the fact that one has to actually get up out of their seat).

What do virtual event organizers and technical program committees (TPC) need to do to capture attention and increase participation? They need to significantly improve presentation quality! Each and every presentation must be on-topic and well executed.

Abstracts and presentations need to be reviewed and revised to be clear, concise, and non-commercial. Presenters must be polished and energetic even if they aren’t regular speakers.

Old games like big names for keynotes to draw a crowd are not helpful online unless they have relevant exciting information to share. Two recent examples of failed keynotes: one a very big name who is rumored to charge $100,000 per presentation gave an uninspiring “interview”. He basically rehashed his well-known views and simply named dropped the sponsors and executives organizing the event. There was no fire or spark in this presentation nor was there any significant relevance to the event. The online audience of about two thousand was roughly the same size as a few of the recent events I have organized with much lower budgets than what was WINTER 2020 MEPTEC REPORT | 9

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WINTER 2020

likely paid to this speaker (let alone the entire event budget). Had the event been live as originally planned, people would have likely attended just to be in the same room as this person. But even then, I doubt it would have been money well spent.

The second example of a poorly executed keynote was a senior executive of a well-known electronics company.

When I heard him speak previously, he was a good speaker. In this particular instance, his pre-recorded keynote was more of an informercial for his company rehashing their current technology.

There were no new announcements, no discussion of strategy, no inspiration just an overview of information that was already well known. His keynote was not helped by his lackluster delivery.

Unless significant rehearsing and editing is done, pre-recorded videos tend to have far lower energy than live presentations.

Honestly, this was 45 minutes of my life that I would like to have back. Unfortunately, the event organizers neither made the slides available beforehand (allowing one to skim the presentation to see if ‘attending’ was worthwhile) nor was the keynote recording made available other than at broadcast time.

What is missing in many of the virtual presentations I have seen is the preparation, care, and respect for the audience that is expected from a live presentation. Perhaps everyone sitting around in their bathrobes at home on virtual events has lulled presenters into a false sense of complacency? Even if the audience is casually attired and suffers from a lack of attention, presenters need to put in significant effort due to audience size and permanence of the presentation. If you practice a presentation for several hours for a room of fifty or five hundred attendees, shouldn’t it be well honed for an audience of a thousand, five thousand, or more? Just because a presenter cannot see or “feel the energy” of a virtual audience, it doesn’t mean the audience is not there. The reach of virtual events is often far greater than in-person events especially when all the costs and logistics are drastically reduced or eliminated. I’m always surprised by the number of people from around the globe who at all hours of the day and night are tuning into an historically

regional event that is now virtual. And I have news for presenters who do not usually worry about the quality of their presentation at a live event since “no one will remember” it later: many virtual events are recorded with significant postevent playback. These recordings leave an enduring record which often have a long life on the internet.

Well executed, in-person and virtual events can look simple, but there are many details that need to be organized for smooth execution and to fully engage the participants. Dealing with people is difficult and doing so at scale is even harder. Successful presenters and event organizers realize that virtual events are about people and not simply a means to “broadcast” material. Without the appropriate audience, virtual events are like a play in an empty theater which means it is meaningless and has no reason to exist. A successful virtual conference, like a play, requires not only an audience and a qualified cast, but the behind-the-scenes efforts of a seasoned producer, a talented director, and other experienced support.

For more of my thoughts, please see my blog http://hightechbizdev.com.

As always, I look forward to hearing your comments directly. Please contact me to discuss your thoughts or if I can be of any assistance. ◆ IRA FELDMAN is the Principal Consultant of Feldman Engineering Corp. which guides high technology products and services from concept to high volume manufacturing. He engages on a wide range of projects including technical marketing, product-generation processes, supply-chain management, and business development. In addition to serving as MEPTEC’s Executive Director he is the General Chair of TestConX. He lives in Silicon Valley (San Francisco Bay Area) and previously was more likely found in an airport than his office. (ira@feldmanengineering.com)

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F E B R U A R Y 9–10, 2 0 2 1 O n l i n e

Thermal Management of ICs During Testing

TOOHOT TO TEST The power consumption

of Artificial Intelligence (AI) and other advanced computing devices has created significant thermal test challenges, including high-power delivery and large-capacity cooling.

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Please submit presentation abstracts by December 18, 2020. Join us for this interactive, live, cross-functional discussion.

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THE PREEMINENT EVENT

CONNECTING ELECTRONIC TEST PROFESSIONALS TO SOLUTIONS

ANALYTICS

Extended Analytics to Accelerate Time to Quality Across End-to-End Value Chain Yuri Mitnick and Zoe Conroy Cisco Systems

Design

Pkg Test Fab IN THIS ARTICLE WE WILL LEVERAGE a concept of KGD, end to end (ETE) supply chain and complexity theory to achieve faster learning cycle to improve performance/yield/quality and reliability optimization of semiconductor components and systems.

In system ETE test flow we are testing for known good (KG) “something” at any point in test flow. We start with the die (KGD), then move to the stack (KG stack).

Then we package the part to get to KG package or KG module. Then we assemble the part on the board and test to get a KG board. The board is assembled into a system and we test to get KG system. Our end goal is to deliver a KG system in the customer environment across the product lifetime. KG at one point may fail at the next step. The question is how to detect the fail early? Then, how to fault isolate and identify root cause? Then finally, how to fix it and avoid this in the future?

The Value Chain in the system industry starts with component design and wafer fabrication. Dies on the wafer are tested at wafer sort, assembled and tested at package test and system level test. The next steps are component assembly on the board, engineering design validation test and further test stages in volume production (for example, in circuit test, diagnostic board test and system test before it reaches the customer (Fig. 1).

At each test point, new parameters are introduced, where these parameters are dependent on the new level of integration and interactions between environment and components. Parameters dependent on test steps introduce higher complexity because the test and characterization is done in a different domain of the supply chain.

Let us review some examples of things can go awry: • Wafer Sort test may detect parametric yield loss due to “process to design” inter12 | MEPTEC REPORT

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Customer

Wafer Test Test After System Assembly

SLT Test Figure 1. Example of Value Chain in the system industry.

action caused by the silicon to simulation gap.

• Package test may have yield loss due to chip to chip interface fallout in multi die package, or due to impact of package parasitics on timing margin or signal integrity.

• System level test may screen failures in system level application due to the deviation of power/thermal/voltage map from the design model and not covered by ATE testing. System testing may also identify fallout in real system environment due to higher power supply noise, insufficient cooling, cabling issues, component mismatch in system environment that was not accounted for in the component model.

Below are some examples of areas to identify interactions and mitigate their impact: • Use wafer sort (WS) data to optimize foundry process target and yield.

• Add Fault isolation to sub-die and down to design node.

• Capture voltage/timing margin measurements at all test steps to map to worst case thermal and noise system environment.

• Match voltage, power and timing across dies and components.

• Map temperature and thermal resistance to reach target thermal performance across dies and within the system • Characterization and monitoring of reliability degradation.

In addition to the technical dimension of the higher number of parameters with interactions, we would like to introduce a relational dimension within the concept of the ETE value chain. The goal is to strengthen collaboration and unleash potential across domain boundaries, at the same time keeping the autonomy of stake-

holders. The ETE Value Chain could be represented as managed flows of products, cash, and information from the customer’s customer to the supplier’s supplier as defined by the business strategy[1]. The ETE value chain process usually goes through five distinct phases: improving transactional efficiency, data sharing, formulation of policy, building relationships, and engaging in joint value creation. Companies that have cross-functional alignment (e.g. sourcing, making, delivering, etc) and clear governance models can make progress faster. Following processes enables better alignment. For example, • Reach goal clarity: Plan upfront with the ETE in mind. Plan across domains.

Build a common language. Be credible, sell a proposal that is a win-win.

• Build a guiding coalition: Build relationships for active collaboration across all product functions – intellectual property (IP), design, test, yield, product development, quality & reliability - to co-optimize for performance, time-to-market (TTM), and cost.

• Orchestrate Cross-Functionally: Define shared metrics with the end product in mind. Enable data flow from the product (test/field, etc.) to supply chain and back to co-optimize process control and future designs.

• Embrace New Technologies. Test and Learn: Share development roadmap and assess the value to the end customer in the ETE chain from early development to volume production.

Let us assess how the technical problem with high number of parameters / interdependencies and presence of organizational and supply chain boundaries could be addressed from system complexity point meptec.org

of view [2]. Complex Systems are systems in which large collections of components interact in nonlinear ways [3]. Nonlinear interactions cause the whole to be “more than the sum of its parts”. Nonlinear implies that the system can’t be understood simply by understanding its individual components. New system properties may result in emergence. For example, forward motion emerges when a bicycle and its rider interoperate, but neither part can produce the behavior on their own. Ant colonies, cells, brains, immune systems, social groups, or economic markets exhibit a self-organization emergent property.

We would like to use the diagram of hierarchy of systems (Fig. 2) by complexity[4] to classify our problem. This hierarchy moves from static system (level 1) to system with transient properties (level 2), stochastic properties (level 3), system with feedback loops (level 4) and then further up to live organisms from plants (level 5), animals (level 6) to humans (level 7).

Then the hierarchy leaps to social organizations (level 8). It even reserves level 9 to a complexity level that is still unknown.

Obviously, new parameters and interactions make the “system” more complex in comparison with the “component” for system hierarchy levels 1 to 4. But a higher level of complexity for the “system” has potential connection with developing collaborative organizations and supply chains (level 8). On the system side (vs component) we deal with more stakeholders, with more suppliers, and the need to overcome more “across domain” barriers. Domain barriers examples are technical background and expertise, R&D allocation, sub industry culture, decision making processes, different technical metrics/standards, etc.

Because a complex system is usually composed of many components and their interactions, it can be represented by a network in which nodes represent the components and links represent their interactions.

Complex networks can largely simplify real systems and preserve the essential information of the interaction structure that leads to emergent complex phenomena.

This approach is used for system modeling in design automation tools. Our goal is to collect relevant and exhaustive data in product development and manufacturing environment to validate and retrain the models to adjust to real system behavior and accelerate learning. meptec.org

Level 9: Systems of unspecified complexity Level 8: Multi-Cephalous systems

Social Organization Level 7: Symbol Processing Systems Humans

Self conscious language users

Level 6: Internal Image Systems Animals Level 5: Blueprinted Growth Systems Plants

Division of labor among cells

Level 4: Open Systems Self-reproducing Level 3: Control Systems

Systems with feedback Level 2: Clockworks

Changing vs. time Level 1: Frameworks

System with static properties Figure 2. Diagram of hierarchy of systems by complexity [4].

To illustrate the concept above, let us study a supply chain that contains three domains: foundry, component, system.

The boundary between system and the component could be represented by system related fail mechanisms, system related operational environment, and reliability degradation (specific to system environment).

• How do we characterize this boundary earlier at component level? Collect the data with system level test (SLT) and monitor degradation in high-temperature operating life (HTOL).

• How do we improve the model of this boundary on a system level? Enable fault isolation (FI) in system test. The FI should enable fail mapping to the component and then to the specific circuit and ideally to transistor level. Characterize environment (Cooling, Voltage, Temperature), map environment impact to process performance (e.g. measure process monitor ring oscillator (PMRO), delay), measure degradation in system ORT, process field data. Then, leverage FI and characterization above to map failure mode to ATE test.

• How can this mapping be extended to cover the component-foundry boundary?

Mapping of the dependence to transistor level enables effective foundry interface, provides data to improve the PDK (physical design kit) model accuracy, and adds system environment parameters to the PDK. It allows the modeling of degradation that is application and system specific.

For any parameters that have low margin to spec and high impact on customer value,

we may try to push envelope and extend requirements down to the foundry process, material and equipment suppliers.

In other words, we can use top down and bottom up approach to model interactions.

• The top down approach maps the specs down: system → design → process performance. For example: map transistor performance at worst case system setup to wafer acceptance test (WAT) and design corner simulations • The bottom up (circuit to system) approach maps “low margin vs spec” parameters to extend component performance model to system environment.

For example: Quantify circuit parametric sensitivity (e.g. Vmin) to extended range of voltage and temperature in customer system setup.

In the context of the value chain, the emergent property of the KGD approach is a more accurate cross boundary model for performance/yield/reliability. More accurate models also support a pareto approach: Investment in the top value items addresses the major system constraints. This model enables faster collaboration and learning through data across ETE supply chain.

The following example provides additional illustration. The thermal map (due to cooling) may be modified in a system environment in comparison to a component environment and may result in a modified power map and voltage drop map or a Si to Simulation (S2S) gap. This may cause memory failure in the system test after passing component test. The sensitivity could be fault isolated to a certain process marginality (e.g. transistor performance degradation). The yield model will include system level yield loss dependencies (e.g. sensitivity to cooling). A quality and reliability (Q&R) risk model will add degradation of memory cell across lifetime to assess failure rate in the field.

How can this example be utilized to enable collaboration?

• S2S mechanism & FI model could be shared with the foundry.

• Cooling and power supply issues could be shared with the system design owners and vendors.

• High stress functional test could be expanded for better coverage by the software owner.

To enable problem solving for the above, we need to extend component anaWINTER 2020 MEPTEC REPORT | 13

ANALYTICS lytics to cover the ETE value chain and “across domain” issues. We need to capture all data in the database (DB) to support effective communication and provide data interfaces for every supplier to cover their design space. Desirable features include cloud hosting across all test insertions, integration of supplier data and enablement of data subset sharing with supplier. Extension of the production DB to integrate data from characterization / new product introduction (NPI) / pilot build stages of development and field usage would allow faster convergence to the goals.

What improvements from outside suppliers could accelerate adoption?

1. Combine design models by domain: Component, printed circuit board (PCB), thermal, signal integrity/power integrity into a single tool to allow co-optimization.

Provide interface for the owners to tweak and update the models with real product data to enable continuous learning.

2. Improve performance characterization in system environment: better sensors, better monitors insertion, better data process-

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REFERENCES [1] End to end supply chain: http://www. supplychainshaman.com/new-technolo gies/navigating-the-end-to-end-journey/ [2] “System testing in the era of AI and 5G”,

Harry H. Chen, Semicon Taiwan, 2019 [3] Complexity references by Santa Fe Institute: https://rightreason.typepad.com/ right_reason/2014/01/what-is-complexity. html [4] “Beyond open system models of organi zation”, Louis Pondy, Emergent Publica tions, 2005 [5] “Degradation monitoring --from a vision

to reality”, Evelyn Landman et. al., IRPS 2019

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ers/supply chain partners, to preserve autonomy, to maximize collaboration, to align roadmaps. We suggested to increase the leverage of data driven storytelling to connect ETE supply chain domains (e.g. materials, equipment, component, PCB, cooling, system, software, etc.) and build a more inclusive human organization that leverages and co-optimizes available technologies, with faster learning cycles, and better performance/cost/Q&R. ◆

SO

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PalaMax

ing and integration into the design model (item 1).

3. Use the capability in items 1 and 2 along with available infrastructure to create a degradation model that is more relevant to customer applications [5]. Consider degradation model sharing across foundry customers to improve utilization of the margin.

In conclusion, we introduced an “Extended KGD Philosophy”. It addresses system level complexity by mapping customer application specs across ETE value chain to “known good” specs for the System, Module, Package, Die, Process, Incoming materials.

• “Extended KGD test” feasibility relies on more accurate system model (performance, yield, reliability).

• Accurate system model is a result of thorough characterization, and model re-training through monitoring of cross domain interactions in the system during development and production.

We applied ETE value chain-based approach to extend design space (codesign/co-optimization) to stakehold-

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PACKAGING

Die Crack Prevention and Detection in Advanced Packaging Woo Young Han Onto Innovation

THE NEED FOR LOW COST, SMALLER packages with high density interconnects for smartphones and wearable devices has been leading the development of advanced packaging. All of these advanced packaging techniques involve stacking multiple chips in vertical directions. In DRAM memory packaging, there are as many as eight dies integrated vertically and the manufacturers are trying to keep the thickness of the die as minimal as possible to keep an overall thin package profile.

Backside thinning of fully processed wafers has become a widely used technique in the industry. Typical final wafer thickness in the early 1990s was around 450Âľm but current wafers are usually thinner than 50Âľm. As the final wafer thickness becomes thinner, they are more fragile and susceptible to cracks and chips. Chipping and cracks can cause near-term yield and long-term reliability problems. If a chip or crack is discovered during the final processes of advanced packaging, the overall final yield will be lower. If it is not discovered, the end device may not be reliable in the real world and fail for the consumer, a more costly consequence.

As wafers became thinner, the industry started seeing sidewall cracks, inner cracks and micro cracks starting from the kerf or street area initiated from wafer sawing. These types of cracks can cause air bubbles around the cracks during the molding process in fan-out packaging and eventually lead to mold cracking which can result in lower yields. It would be very beneficial if these types of cracks are detected early and the affected die removed. However, these types of cracks are happening underneath the die surface and are difficult to see with traditional bright field and dark field illuminations because they are underneath the top surface. meptec.org

Hairline Crack

Sidewall Crack

Inner Crack

Backside Crack

Figure 1. Die cracks are generally associated with the dicing process and categorized as hairline, sidewall, inner or backside cracks. Each crack type has distinct causes and requires a different approach to optimize detection.

Vertically integrated chips are a necessity for advanced packaging. The thinning technique to reduce overall package thickness results in more fragile die that are susceptible to cracks or chipping. It is necessary to prevent and detect these cracks or chips before they reduce the final package yield or cause long term reliability issues in the consumer device.

Results Die cracks come in several types (Figure 1), each requiring a different approach to optimize detection. Hairline cracks occur at the surface. They are small and shallow and show low contrast in inspection images.

Sidewall cracks penetrate the die from the sidewall (the die edge), roughly in the plane of the die, and seem to be directly associated with the dicing process. Inner cracks are similar to sidewall cracks but may occur anywhere in the die and are likely caused by stresses introduced at other stages in the process. Backside cracks originate in the wafer substrate and often continue across multiple die.

As with any defect control, the best approach is prevention. In the case of die cracks, the best prevention is tighter control of the dicing process. Traditionally, manufacturers have relied on manual microscope inspection for sawing process control. Like other manual inspection, it is labor intensive, slow, and inconsistent.

The solution for these issues is automated kerf metrology and inspection.

The sawing process and chipping or crack counts are directly related. The number of cracks increase as the sawing process becomes unstable. The primary consideration for kerf metrology after sawing is the position of the sawing lines relative to the die seal rings. Each die is separated by streets and has seal rings that provide protection to the active die area from the outer environment. Manufacturers are concerned that if a die seal ring is broken by a chip or crack it can cause reliability issues in the real-world devices.

Optimizing the sawing process involves the ability to automatically measure the dicing lines relative to the die seal rings. Accurate and repeatable kerf metrology helps with the overall sawing process improvements and reducing WINTER 2020 MEPTEC REPORT | 15

PACKAGING

Seal Ring Kerf Margin (b) Kerf Separation (d) Kerf Margin (c)

Seal Ring

Figure 2. There are commonly used terms in the industry to characterize kerf metrology.

defects such as chipping and cracks. More manufacturers are adopting automated kerf metrology and inspection.

Kerf metrology/inspection assesses the quality of the cuts made during the wafer saw process and there are four commonly used terms in the industry to characterize kerf metrology quality (see Figure 2).

Kerf Margin measures how much material is left outside the die after singulation.

Kerf Width measures how much material was removed by singulation. It requires an accurate determination of the whole wafer street width before singulation.

Kerf Position measures the distance between the actual cut and the street center. Ideally, the cut should occur in the center of the street.

Kerf Separation is the distance between the cut edges of two neighboring die. It indicates how far apart the two die moved during expansion.

The overall sawing quality on a wafer can be viewed by various graphs (Figure 3). The graph in Figure 3 shows the kerf margin distribution on the wafer by the cut lines. The yellow points represent the upper margin and the blue points represent the lower margin on horizontal cuts.

Likewise, the red points represent the left margin and the purple points represent the right margin on horizontal cuts.

A two blade sawing method is commonly used in the industry for faster throughput. On both horizontal and vertical cuts, the signature of two blades can be seen on the graph.

Ideally, the margins on both sides of kerf should be the same, indicating the cut was made at the center of the street but the graph in Figure 3 shows that the vertical cuts made on the left half of the wafer were better centered than the vertical cuts made on the right half of the wafer. The margins between the two sides are closer to each other on the left half of the wafer compared to the margins on the right half of the wafer. Also, the graph in Figure 3 shows that more materials were removed from the left half of the wafer compared to the right half of the wafer during the sawing. The sum of the margins on both sides should be the amount of material left on the kerfs and the margins on right half of the wafer are clearly larger than the margins on the left half of the wafer.

The same symptom can be seen for

Figure 3. Graph showing kerf margin distribution by cut lines on wafer. Clear signature of two blades (vertical cuts) between the left and the right side of the wafer can be seen here. The blade on the left side of the wafer was better centered in the middle of kerf compared to the blade on the right side of the wafer. The margins between the left and right side are closer to each other on the left side compared to the margins on the right side of the wafer. Also, it can be seen that more raw materials were removed on the left half of the wafer compared to the right half of the wafer.

16 | MEPTEC REPORT

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the horizontal cuts between the lower and upper half of the wafer.

Hairline Crack With wafers thinning beyond 100Âľm, the wafer manufacturers have been suffering with very thin partial cracks also known as hairline cracks. The primary challenge with hairline cracks is their small size and low contrast from the background.

Figure 4 shows images of a hairline crack before and after the application of image processing algorithms designed to enhance the visibility of hairline cracks.

Spatial filtering improves the signal to noise ratio, resulting in a doubling of the apparent width of the crack and four to five times increase in contrast.

The algorithm is also designed to improve uniformity near the edge of the die where cracks are most likely. The overall result is an improvement in detectability and reduction in nuisance defects.

Figure 5 shows the same hairline crack in three different images. The image on the left is a traditional bright field color image and the image in the middle was captured with the new topography-based image sensor. While the hairline crack can be clearly seen with high contrast in the new topography-based image, the crack is barely visible on the traditional bright field image. The IR image on the right confirmed the presence of the crack.

Sidewall Cracks Sidewall cracks, also known as inner cracks, are another type of crack initiated by sawing and difficult to detect. Sidewall cracks typically penetrate between layers near the die edge and it can be difficult to distinguish them from chipping.

In many cases, the inner cracks can be seen better at lower magnification compared to higher magnifications (Figure 6).

The lower numerical aperture of the lower magnification optical system enhances its sensitivity to topographic displacements that often occur over the cracks. In many cases, IR images can see through some layers and are useful in confirming their presence.

Backside Cracks Backside cracks are relatively large and easy to see from the wafer backside.

Backside cracks often cross more than meptec.org

5X BF Image

Hairline Crack

Hairline Crack

(The hairline crack is 2 pixels wide and has less than 10 GSV contrast)

(The hairline crack is 4 pixels wide and has around 40 to 50 GSV contrast)

Original Defect Image

Post-Crack Detection Defect Image

Figure 4. Image processing can improve the apparent size and contrast of a hairline crack.

The image on the left is a raw bright field image of a hairline crack. The crack is only two pixels wide with 10 GSV contrast from the background. The image on the right is the same crack but it has 4 pixel width with 40-50 GSV contrast. The processing algorithm uses spatial filtering to eliminate noise and enhance the contrast of the crack.

Hairline Crack

Bright Field Color Image

Hairline Crack

Hairline Crack

Height Topography Image

IR Image

Figure 5. Topography-based image can improve the apparent size and the contrast of the hairline cracks. The image on the left is raw bright field color image of the hairline crack.

The crack has less than 3 GSV contrast from the background. The image in the middle is the same crack captured with the new height topography sensor and it has over 70 GSV contrast.

The image on the right is an IR image of the same crack and it confirmed that the crack is real.

1X-BF

20X-BF

10X-IR

Figure 6. Sidewall or inner cracks can be challenging to detect because they mostly occur below the die surface. In these images, their appearance changes with magnification, seeming to be more extensive at 1X and smaller at 20X. IR images look through the pattern on top of die and can provide crucial confirmation of their existence and extent.

one die and are associated with the dicing process while the dies are still on the film frames that support them. The challenge lies in inspecting the backside without damaging the active die area on the fronmeptec.org

tside. Flipping film frames requires a film frame inverter. Once inverted, inspection without contacting the front surface requires a specially designed chuck in which the central portion, corresponding

Figure 7. Wafer backside cracks are obvious when viewed from the back. Inspecting the backside without contacting the active area on the frontside requires special handling capabilities.

to the active area, can be retracted below the chuck surface to avoid contact.

Without any support in the active area of the wafer, there can be large sagging on the wafer and the primary challenge in performing automated inspection is to keep the images focused.

Another major challenge in backside inspection through film is background noise. Figure 7 shows typical backside cracks through film and the grinding marks on the wafer can be seen. In many cases, the grinding marks on the wafer look similar to cracks and it can be challenging to distinguish real cracks from the noise such as grinding marks and scratches on the film.

Conclusions Die cracks such as hairline cracks, sidewall cracks, and backside cracks may not show up during electrical tests, but such cracks can cause field failures and adversely impact real world reliability of a product. Detecting die cracks is essential in high reliability applications like automotive where there are significant safety and liability concerns.

Proven solutions exist for in-line crack detection in high volume manufacturing. The solutions described in this paper such as kerf metrology/inspection, hairline crack, inner crack, backside crack inspection, IR image sensor, topography based image sensor combine software and hardware to improve wafer sawing process control and increase the sensitivity to detect such cracks with minimal nuisance defects. â—† WINTER 2020 MEPTEC REPORT | 17

ANALYSIS

Challenges of Advanced Packaging Failure Analysis Bernice Zee and Chin Jiann Min, Device Analysis Laboratory Advanced Micro Devices (Singapore) Pte Ltd.

THE SEMICONDUCTOR INDUSTRY is no longer purely performance driven.

Requirements such as economic viability, increased functionality, miniaturization, low latency, and high bandwidth are becoming more important. Furthermore, Moore’s law scaling is becoming more challenging and costly, thus, innovations in packaging technologies through heterogenous integration are needed to meet the increasing demands of this new digital age.

When surveying the emerging next generation packaging technologies developments of integrated device manufacturers (IDMs) and foundries, two trends can be observed: one is die-stacking and the other is dis-integration. Die stacking allows for increased functionality without compromising the two-dimensional (2D) footprint, but this comes with its challenges. Firstly, through-silicon-via (TSV) reliability becomes very crucial and secondly, the ability to identify defects in these high aspect ratio interconnects will become important. Dis-integration brings the advantage of reduced die size which benefits yield and allows for IP reuse.

Conversely, there can be disadvantages in terms of routing and latency.

Regardless of whether dies are stacked or dis-integrated, it is critical that only known good die (KGD) are assembled to form the final product. However, KGD can turn into a bad die due to design, process, and assembly issues. Consequently, robust and efficient failure analysis (FA) is essential for achieving the highest possible quality to make any advanced packaging approach work. Failure mechanisms that may occur in advanced packages are like those of conventional flip chip packages as shown in Figure 1. However, finding and diagnosing the cause of failure is becoming increasing challenging due to package design complexities.

Furthermore, ease of FA is a criterion seldom considered when new packaging 18 | MEPTEC REPORT

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Âľ-Bump - Delamination - Cracks - Misalignment - Shorts - Damage in underlying MEOL - Warpage Chip 1 CPU GPU

C4 Bump - Delamination - Cracks - Misalignment - Shorts

MCM Organic Package - Copper trace damage - Cracks Chip 2 IO

CPU

GPU

Interposer/TSV - Delamination - Pin holes/breakdown in liner - Voids - Cracks - Electro migration

Organic Package

Figure 1: Possible failure mechanisms in next generation packaging technologies.

Defect validation

Nondestructive testing (NDT)

PFA

Conclusion

Figure 2: Typical Package FA workflow.

technologies are developed. As a result, innovations in FA techniques need to occur in tandem with packaging technology advances so that meaningful FA can continue to be pursued.

The objective of this article is to highlight the requirements for next generation package FA as well as touch on the challenges and current state of the art. Case studies will be discussed at the end to demonstrate how the various techniques are used together in the package FA flow to root cause device failure.

Requirements for Next Generation Package FA The standard semiconductor industry package FA flow is illustrated in Figure 2.

The device under test (DUT) undergoes a series of non-destructive testing (NDT), which includes electrical fault isolation (EFI), to isolate the defect before physical failure analysis (PFA) is carried out to reveal the defect.

While the FA workflow may be broad-

ly applied for analyzing next generation advanced packages, architectural complexities such as die stacking or embedded components introduce a third dimension (i.e., depth) which complicates defect localization and visualization. Accordingly, next generation package FA requirements need to evolve to provide: (1) high spatial and axial resolution, (2) improved signal sensitivity, (3) faster image acquisition speed, and (4) higher precision and throughput. A more in-depth discussion of the challenges and advancements of various NDT techniques will be covered in the latter sections.

Electrical Fault Isolation (EFI) Techniques EFI is a required step to validate the electrical failing signature of a DUT (i.e., failing dead short, dead open, leakage or resistive open) and to localize a region on the device to focus subsequent failure analysis. Curve trace is employed at the start to electrically characterize the meptec.org

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ANALYSIS

Lock-in Frequency (Hz)

Figure 3: Defect Z-depth determination using LIT for 2.5D devices

DUT. Once this is completed, other EFI techniques such as Lock-in thermography (LIT), electro optical terahertz pulse reflectometry (EOTPR) and magnetic field imaging (MFI) are used to localize a region of interest (ROI).

Lock-in thermography (LIT) is an established technique for non-destructively localizing thermally activated on-die and embedded semiconductor package short/leakage defects in the x, y, and z dimension [1][2]. In LIT, phase shift (φ), which represents the time delay between an electrical stimulation and a thermal response of a device, is used for 3D defect localization (i.e. the deeper the defect, the longer the time delay). This is achieved by comparing experimental phase shift data obtained from the DUT with a theoretical plot of phase shift versus applied lock-in

frequency as shown in Figure 3 [1-7]. However, the feasibility of generating phase shift data plots for 3D defect localization remains challenging not only because of complex experimental set-ups but also because of the consistency and accuracy of the data points collected. Furthermore, time to results is another facet to consider.

This is especially relevant to defects that are deep-seated in the device.

To alleviate some of the challenges, a new algorithm for phase data acquisition was developed [8]. The new algorithm applies real-time parabolic curve fitting to automatically find the best point on the thermal emission site to report phase data from (i.e., selecting the point in the curve with the lowest phase value as shown in Figure 4). The other benefit of the new algorithm is that it significantly reduces the time required for phase date acquisition as the lock-in measurements can be stopped automatically when a pre-defined

(a) Figure 4: Non-linear phase variation across thermal emission site.

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goodness of fit is reached.

For open/short defects of signal pins in semiconductor packages, electro optical terahertz pulse reflectometry (EOTPR) technique, which uses terahertz pulses, has been utilized to diagnose and localize faults in a wide variety of complex IC packages with different device architectures [10]. During operation, electrical pulses are launched into the (DUT) via a high frequency circuit probe (Figure 5a). Reflections from device structures and faults are recorded as a voltage-time waveform by a fast-photoconductive switch.

Measurement set-up typically requires a good unit, and suitable references to compare with the failed unit and the fault location is determined by measuring the time of flight to a suspect peak in the waveform. However, as semiconductor packages become more complex, finding or fabricating suitable references for comparison becomes a serious challenge.

To address this, a software was developed to utilize one-dimensional lump circuit model to simulate a measured EOTPR waveform from a known good device [11].

Subsequently, the waveform of the failed device is measured, and the software runs a simulation to fit and optimize the KGD model to that of the failed device waveform to extract the fault location of the failed device.

Finally, magnetic field imaging (MFI), the mapping of current in devices by detecting the magnetic field they generate,

(b)

Figure 5: (a) Schematic diagram of an EOTPR system. (b) Typical raw EOTPR waveform from the open end of a high frequency circuit probe.

meptec.org

Figure 6: Current density image of short defect in DUT using MFI.

can be used for detecting shorts, leakages, high resistance, and open circuit failures [12].

It is a suitable technique for 3D fault isolation because magnetic field can pass unobstructed and unaffected through most, if not all, materials currently used in packaging. The signal (DC or few kHz AC for shorts and leakages detection or RF up to few 100 MHz for open failure detection) injected in the DUT generates a magnetic field and the magnetic field is detected by a sensor raster scanning above the device. This magnetic field data is typically processed using a standard inversion technique to obtain a current density map of the device and this allows defects to be localized in X-Y dimension as shown in Figure 6.

For defect localization in the z-dimension, a 3D solver software starts with an initial current path extracted from the current density image. The solver positions the current path in an XY plane at an arbitrary distance (Z) from the sensor. It then adjusts the current path z distance in a way that matches the observed magnetic field in the acquired scans and from these adjustments a true 3D current path can be constructed and in doing so, vertical information about the path is obtained. The challenge for ubiquitous adoption of this meptec.org

EFI technique lies in the time to results, the ease of data interpretation for general FA practitioners as well as the occasional need for sample preparation to minimize the distance between the sensor and die surface to improve signal resolution and sensitivity.

Non-Destructive Testing (NDT) Defect Imaging Techniques After a ROI is localized on the DUT, non-destructive defect imaging techniques such as acoustic microscopy and X-ray imaging are employed to inspect for any anomalies.

C-mode scanning acoustic microscopy (C-SAM) is a mature non-destructive imaging technique used for inspecting semiconductor package interfacial integrity. However, new advanced semiconductor packages feature smaller interconnect dimensions, multiple die stacks, thinner form factor and embedded silicon bridges, thus posing significant challenges in terms of signal penetration and resolution. Currently, high resolution acoustic imaging can be achieved by considering the following: (1) high speed data processing to improve signal-to-noise ratio and enable capturing of small data gates, (2) SAM transducer frequency and focal

length based on semiconductor package construct, (3) transducer and sample water path reduction to minimize attenuation of high frequency signals, and (4) active z-axis positioning of transducer during scanning to overcome warpage induced artefacts in acoustic images [13]. However, the challenge of imaging through a 3D die stack or embedded silicon bridges remains as FA practitioners need to compromise depth penetration with transducer frequency which is correlated to lateral resolution. Furthermore, the ability to resolve and image each die interface in a complex 3D die stack individually is still elusive because of acoustic waveform convolution. Some areas being worked on to overcome the challenges include advanced acoustic signal processing and advanced transducer design development.

3D X-ray Microscopy (XRM) is another frequently used non-destructive imaging technique. It enables high resolution imaging of internal structures and defects in complex next generation packages without having to destroy the device.

This give FA practitioners an opportunity to revisit EFI testing when the need arises as well as increase PFA confidence. Figure 7 shows a typical setup of a 3D XRM. In addition, 3D XRM has demonstrated success in replacing physical cross-sections in FA labs [14][15].

Scintillator Device

Lens system

X-ray source Detector

Figure 7: Schematic diagram showing the setup for a 3D-X-Ray microscope.

A sample placed between the X-Ray source and detector is rotated axially. 2D X-ray images taken at different angles are initially enlarged through geometric magnification. Further magnification of these images is achieved when a scintillator converts X-rays into photons, thus enabling optical magnification. In a post-measurement process, the collected images are used to reconstruct a 3D volume model of the sample. However, the WINTER 2020 MEPTEC REPORT | 21

ANALYSIS

challenge of faster time to results remains and this could be addressed by system automation and higher power source.

In the next section, case studies will be discussed to demonstrate how the various techniques are used together in the package FA flow to root cause device failure.

(a)

(a)

(b)

(b)

(c)

(c)

(d)

(d) Figure 8: Case Study 1- (a) Thermal Emission Site in XY detected using full camera frame; (b) Phase shift measurements for Z depth localization; (c)TIVA Emission site observed; (d) M3 Die Metal Damage observed during die-level de-processing.

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Figure 9: Case Study 2 - (a) Thermal Emission Site in XY detected using full camera frame; (b) Phase shift measurements for Z depth localization; (c) 3D X-ray microscopy slice image at LIT emission site; (d) FIB cross section and EDX at LIT emission site.

Case Studies In a first case study, a 2.5D IC device failed power supply testing at automated test equipment (ATE) during routine screening. Leakage was verified when biasing the failure power supply pin with respect to ground pin by curve trace. The device was analyzed with LIT to determine the defect location in the X, Y and Z space. Compared to a good unit, an additional thermal emission site was detected at the die edge as shown in Figure 8(a).

Thereafter, phase shift data was acquired and plotted against the empirical phase shift plot to determine the defect depth in Z space. The phase shift measurement results obtained fell very close to the region defined as “Die” by the empirical reference plot as shown in Figure 8(b), indicating the defect was possibly located in the die metal and/or active circuitry.

Observable TIVA emission site substantiated this conjecture as seen in Figure 8(c) and die-level de-processing was done at the identified location. M3 die metal defect was subsequently observed as seen in Figure 8(d).

In a second case study, a different 2.5D device failed power supply short at the automated test equipment (ATE) when undergoing routine screening as well. The power supply short was verified when biasing the failure signal pin with respect to the ground pin by curve trace.

The device was also analyzed by LIT to determine the defect location in the X, Y and Z space. A thermal emission site was detected at the die edge as shown in Figure 9(a) and the phase shift measurement results obtained fell very close to the boundary of the “Substrate” and “Interposer” regions defined by the empirical reference plot as shown in Figure 9(b).

This indicated that the defect was possibly located at the C4 bump interface. 3D-Xray meptec.org

(a)

(b)

(c) Figure 10: (a) Zoom in CSAM imaging at signal pin C4 bump; (b) EOTPR waveform from the failed unit (red line) shows an open fault occurred mid-way between the substrate (black curve) and interposer (blue curve) terminations; (c) SEM image of a cross section through the failed unit TSV showing a thin layer of passivation between the TSV and RDL Cu.

microscopy was done at the LIT identified location and suspected solder-like material was observed to be shorting the failure meptec.org

signal pin to ground pin as seen in Figure 9(c). Focus Ion Beam (FIB) and Energy Dispersive X-ray (EDX) conducted at the failed location verified short failure was likely caused by solder flow into passivation/UF delamination as shown in Figure 9(d).

In the final case study, an open failure was observed in a 2.5D device when biasing a specific signal pin with respect to the ground pin by curve trace. Scanning Acoustic Microscopy (SAM) did not reveal any anomalies at the associated failure pin interconnects as shown in Figure 10(a). EOTPR was employed to obtain a more accurate defect localization.

Comparing the waveforms obtained in Figure 10(b), the defect was found to be mid-way between the substrate termination and interposer termination, putting it near the bottom of the TSV. Subsequent PFA revealed a thin layer of passivation material between the TSV and RDL to be the cause of the open as seen in Figure 10(c).

Conclusion To keep pace with the increasing computational demands of the new digital era, packaging technologies have evolved progressively through the application of heterogenous integration as Moore’s law scaling continues to slow down and becomes more expensive to adopt. The introduction of packaging concepts such as die stacking and chip “dis-integration” have added new dimensions to package FA (failure analysis), thus making it very challenging to diagnose and root cause failure when devices malfunction during operational use. Consequently, innovations in FA techniques and tools need to occur in tandem with packaging technology advances as robust and efficient FA is essential to drive toward the highest possible die quality to make any KGD / advanced packaging approach work. ◆ © [2020] Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

REFERENCES [1]

[2]

Schmidt, C., et al., IPFA 2010, “Nondestructive defect depth determination at fully packaged and stacked die devices using Lock-in Thermography”.

Schlangen, R., et al., ISTFA 2011, “Use of Lock-In Thermography for nondestruc- tive 3D Defect Localization on System in Package and Stacked-Die Technology”.

[3] Schmidt, C., et al., ISTFA 2011, “Quan titative Phase Shift Analysis for 3D

Defect Localization Using Lock-In Ther mography”.

[4] Schmidt, C., et al., ISTFA 2012,

“Enhanced Comparison of Lock-in Ther mography and Magnetic Microscopy for

3D defect localization of System in Pack ages”.

[5]

Schmidt, C., et al., Materials Science and Engineering B, 2012, “Application of Lock-in Thermography for Failure Analysis in Integrated Circuits using Quantitative Phase Shift Analysis”.

[6] Cao, L., et al., ISTFA 2012, “Lock-in

Thermography for Flip-chip Package

Failure Analysis”.

[7] Altmann, F., et al., ISTFA 2015, “Failure

Analysis Strategies for Multi-stacked

Memory Devices with TSV intercon nects”.

[9] Zee, B., et al., ISTFA 2018, “Improved

Phase Data Acquisition for Thermal

Emissions Analysis of 2.5D IC”.

[10] J. Alton, et al., EDFA 2018, “Advanced

Packaging fault isolation case studies and

advancement of EOTPR”.

[11] J. Alton, et al., ISTFA 2019, “Non Destructive Short Fault Localization in

Advanced IC Packages Using Electro

Optical Terahertz Pulse Reflectometry”.

[12] A. Orozco, et al., ISTFA 2016, “3D Fault

Isolation in 2.5D Device comprising High

Bandwidth Memory (HBM) Stacks and

Processor Unit Using 3D Magnetic Field Imaging”.

[13] Oh, Z.Y. et al., IPFA 2018, “Optimiza tion and Application of Acoustic Imaging

for Defect Detection in Stack Die Pack ages”.

[14] Md Zulkifli, S., et al., IPFA 2017, “High Res 3D X-ray Microscopy for Non Destructive Failure Analysis of Chip-to Chip Micro-bump Interconnects in

Stacked Die Packages”.

[15] C. Schmidt et al., ISTFA 2016,

“Advanced Package FA flow for next gen packaging technology using EOTPR,

3DXRAY & Plasma FIB”.

WINTER 2020 MEPTEC REPORT | 23

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INTERVIEW

Catching Up with Jeff Demmin Semiconductor and Defense Project Manager Keysight Technologies

With a very diverse and accomplished set of MEPTEC members, there are many great informative, instructional, and entertaining stories to be told.

“Catching Up with…” will share these stories from time to time.

Jeff Demmin (https://www.linkedin. com/in/jeff-demmin-b880992/) is a longstanding MEPTEC Advisory Board member. This interview was conducted via email and edited for clarity.

What was working at a hardware startup like in the early 90’s?

My career started in the Packaging group at National Semiconductor. Many veterans in the industry can claim that as well, since National hired college recruits actively and had one of the biggest packaging organizations back in the 1980s. I worked on a lot of different projects but ended up running the package simulation group. It was awfully primitive in the 1980s – typing node coordinates into a file to run in ANSYS on a computer in a different building – but I learned a lot. A good chunk of my LinkedIn connections go back to the National days, and I still have a National Semiconductor branded digital watch in my hardware archives.

After about four years I jumped to nCHIP. That was a great experience too. At that point I didn’t really understand how much of a longshot a hardware start-up is, but I lasted five years there and learned a lot of new things. I started in package design and thermal analysis for multi-chip modules, but at some point they discovered that I was willing and able to write, so I veered more towards technical marketing and ultimately government-funded proposals and reports. The company was struggling a bit on cash flow, so an infusion meptec.org

of government money was a big help.

I coordinated and wrote a proposal for DARPA’s ASEM program (applicationspecific electronic modules), and the resulting 6 or 7 million dollars was huge deal for nCHIP. Back in those days, such proposals were often hand-delivered, so I flew to DC and we presented it to DARPA. That early experience with government programs turned out to be helpful later in my career. My colleagues at DARPA were amused that I still had a paper copy of it ~25 years later.

The company was fun with some great people, and we even had a decent softball team – the Multi-Chip Maulers.

We once had a group from the government visit us on Halloween one year, and there was CEO Bruce McWilliams giving the nCHIP pitch in a Viking costume.

The highlight of nCHIP, though, was meeting my wife Vikki! She worked in program management there, and the company Christmas party was one of our first dates.

What happened to nCHIP? nCHIP was bought by Flex – then called Flextronics – which was one of the pioneering contract manufacturers. They were looking for some more advanced technology to broaden their scope. I recall the VP of Sales at Flextronics saying that he could see how they could get to $400M annual revenue soon. Now they are at about $25B, so it was probably about 100x growth over 25 years. It might have been interesting (and profitable) to stick around, but it felt like time for a change. I think Flextronics didn’t quite know what to do with the technology, but one output was a spinoff called Intarsia, which was jointly owned by Dow and Flextronics. They

tried to run with the integrated passive technology that arose from nCHIP, but that never took off. It’s hard to compete with ultra-low cost incumbent technologies, even when a new technology has many benefits.

How far advanced was nCHIP’s technology? How does it compare to what is being done in packaging today?

In some ways, nCHIP’s technology was ahead of its time. The key piece was the “Silicon Circuit Board” (SiCB) with interconnect layers embedded in a silicon substrate. In some ways this was a precursor to the silicon interposers that are becoming a mainstay in the industry.

Some pretty impressive modules were built, but nothing really took off in volume. It’s interesting to see those old modules – arrays of wire bonded chips on a silicon substrate in a pin grid array package.

What did assembly/packaging/test look like at the start of your career in the early 80’s? Are any of these devices still being manufactured (by anyone)? Is there still a demand for them? Are the systems they go in still operational/fielded?

Almost 40 years on I am confident that my TO3/TO5 cans, 14/16 lead ceramic dips and side braze components continue to provide excellent service.

The ceramic leadless chip carriers – not so much.

Any stories to tell about Microminature Technology?

My wife and I were interested in getting out of the Silicon Valley rat race, so I looked at some jobs in other parts of the country, but then an interesting opportunity popped up in the North Bay. Microminiature Technology was WINTER 2020 MEPTEC REPORT | 25

INTERVIEW a small company that made assembly tooling, and they needed someone with some experience and contacts in semiconductor assembly. I ended up taking the job and we moved to Sonoma. We moved away a couple of times for various reasons but have ended up back in Sonoma each time. It was probably a bit crazy to make the jump to Microminiature since it was a niche company even in the small world of bonding tools. It was basically a very high-end machine shop, and its specialty was wedge wire bonding tools using an osmium alloy tip. Osmium is known as the most dense element, so that was one of the marketing angles. One interesting twist is that Hewlett-Packard (HP) in Sonoma County was one of the customers, and now – 25 years later – I am with Keysight, the Sonoma County spinoff of HP via Agilent.

What was it like working on extreme high-volume applications (1M/day) at Seagate? Especially with the cost pressures of low margin hard drives (or at least now) and before the days of smartphones (no other applications at that time in this type of volume)?

Seagate was really my first exposure to high-volume manufacturing. National Semiconductor was a large manufacturer of course, but I wasn’t really involved in that side of it. Learning about disk drives was interesting too – I was surprised even 20+ years ago how manual it was. There were tens of thousands of assembly line workers overseas handwiring the connections to disk drive heads with tweezers under microscopes, and anything we could do in the process to save motion would save money.

I ended up working in a development group on optical data storage, which involved micro-lenses and a MEMS-like focusing apparatus.

How/why did you make the jump from Product Engineering to Technical Publications/Editing? And then back again...

I was feeling somewhat plateaued out in engineering roles, not having found an upward path from there. I had always followed the trade press, like EETimes and Solid State Technology, 26 | MEPTEC REPORT

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Jeff tells his personal 9/11-related story at the MEPTEC luncheon last September.

so when a Senior Technical Editor spot came up at the latter, I was intrigued.

They were based in New Hampshire, but were seeking someone around Silicon Valley, which was also a good match for me at the time with a finite set of opportunities in the North Bay. So, I made that jump and really enjoyed that job. That was during the heyday, when SEMICON West was huge and the June and July issues of these magazines were hundreds of pages. Those days are long gone of course! It was a great opportunity to learn more about semiconductor processing and how the industry works.

Everyone wants to talk to you when you have a job that can get them publicity.

Learnings from running a publication? Future of technology magazines?

When I was with SST, a sister publication at PennWell was Advanced Packaging, and the editor-in-chief role opened up there. It was a natural move, since that was more aligned with my technical background. I also took on more responsibility, managing the budget, writing editorials, approving layouts, and other such things. That’s in the running for my favorite job.

One career-related story that I told at the MEPTEC luncheon last year related to 9/11: We were living in New Hampshire at the time, having moved there for the editor-in-chief job. On September 11,

2001 I was flying from Boston to San Francisco to attend a MEPTEC event among other things in Silicon Valley.

I was in the air when the attacks happened, and the pilot made an abrupt landing in Des Moines. They didn’t say anything about the hijackings until we were on the ground. All planes in the air at that time were forced to land where they could. Fortunately I was able to rent a car in Iowa and make it home the next day, but it was a scary time, especially for my wife at home who didn’t know if I was on one of those planes until I was able to land and call her. The Logan to SFO flight that was hijacked was the same airline as mine but left shortly after my flight. We were lucky, but it’s hard not to think of those who weren’t.

Being at Tessera for 10 years you must have seen a lot of change in the company and how IP “developers” are viewed. Thoughts on the role of IP developers vs. “patent trolls”?

Importance of IP and the process of developing it?

I spent almost 11 years at Tessera and saw some changes there, and it has morphed even more since then. I went there basically for the money – the publishing business plateaued out financially – but it was good to be back with some of the nCHIP crew there.

When I joined, it was a one-trick pony with the microBGA, but that was a very good trick. The technology was broadly licensed in a very high margin business model. They branched out over the years, with upgrades to the technology that would require companies to renew licenses, as well as new technologies to license. Some of the latter was by acquisition, and some was by internal development. For a while they also pursued government funding, and I contributed to many of those programs.

Ultimately it was a difficult match to try to create a licensing business with government funded work, so Tessera eventually stopped pursuing that. After that, I moved into corporate development. Tessera had a significant pile of cash and had to figure out how to spend it. We explored all kinds of acquisition opportunities, and it was great fun to dig into new technologies and companies meptec.org

to see if we could find a good deal that helped Tessera’s business. For a while I was almost an expert in display technology and emerging memory devices. The other part of that was patent acquisition.

I took the patent examiner’s course and worked on a bunch of patent search, valuation, and acquisition projects. We eventually bought enough patents to create some new revenue streams. Since Tessera did develop a fair amount of the technology it licensed, it’s more in the IP Developer category than Patent Troll.

We bought some patents from companies more in the latter category. Now, Tessera is Xperi with a much broader range of technology in audio, imaging, and all kinds of consumer technologies.

A few of the same people are there, and they are still developing packaging technology. Hybrid bonding is one area where they are doing some very interesting work.

I left there when the company needed an overhaul at all levels, and I landed at STATS ChipPAC shortly after. Quite a change!

STATS ChipPAC - did you do a lot of traveling to Taiwan? Thoughts on the relationships between OSATs and their customers?

Actually, I never traveled overseas for STATS ChipPAC. I had plenty of late-night calls with the factories, but as the Director of OEM Marketing, I was dealing more directly with people in the US at Apple, Amazon, Microsoft, Google, etc. Still, I did learn a lot about how the factories function, as well as international business. It was stressful at times with the extreme pressure in the low-margin business. The relationships with customers varied – some were great, realizing the value of the partnership, while others were more demanding, and not always reasonably so. I didn’t mind leaving the OSAT world, but it was definitely good experience.

What/why is Booz Allen Hamilton running programs for DARPA? One would think organizations like Draper would be more suited for it... Challenges of being a technologist/program manager within a company of management consultants?

The government makes use of all meptec.org

kinds of resources. Places like Draper Labs provide some good technology inputs, but you also need an army of people from companies like Booz Allen to run things. For example, DARPA is only about 100 or so people directly employed by the government, but there are hundreds employed by contractors such as Booz Allen to keep everything running. That covers IT, administration, facilities, contracting, etc., as well as the technologists. We were basically of two

Once I was on the other side of the table working for Booz Allen at DARPA, it was really interesting to see how things work. The security clearance process, for example, was illuminating. types – fresh PhDs with leading-edge knowledge or industry veterans with a breadth of knowledge. That’s actually why I took the Booz Allen job – it was a place and role that valued a broad background. We were in the minority, though, and there wasn’t a great path upward if technology was your expertise. Still, they treated people well, and it was great to be at a place like DARPA and see a little bit behind the curtain of how the government works.

Your role at Keysight? I’m assuming Keysight’s interest is due to the having a compound semiconductor fab line.

I joined Keysight in November of last year, and I have been working on government-funded programs and various fab projects. It’s definitely an interesting place – very vertically integrated,

with a wafer fab for GaAs and InP devices that go into its test equipment.

Plus the ability to do packaging, boardlevel assembly, and full system design and manufacturing. Keysight also has industry-leading IC and board design tools, and extensive software capabilities. Keysight makes test equipment for very high-performance electronics, so the technology inside has to be even more advanced. In case you don’t know the history, Keysight was spun out of Agilent in 2014, after Agilent spun out of HP about 20 years ago. Keysight ended up with the original HP business of test equipment. The historical display at the facility in Santa Rosa has a functioning version of the original HP200B audio oscillator that was used to test the equipment in the theaters that were equipped with special equipment to show the movie “Fantasia” in 1940.

What is working with/for/selling to the US government like? When did you get your first taste of this? Was it nCHIP? As I mentioned above, nCHIP was my introduction to government work.

Once I was on the other side of the table working for Booz Allen at DARPA, it was really interesting to see how things work. The security clearance process, for example, was illuminating. Mine was surprisingly fast, apparently because of a lack of anything sketchy in my past.

It was also interesting to work in the highest-security rooms (“SCIFs”) when needed, where nothing goes in or out.

There were also tiny cellphone-size lockers where you had to put your personal cellphones before going through security at the DARPA building.

Also, the process by which program solicitations are created and proposals are judged was actually an encouraging view of how the government can work.

As one DARPA program manager put it, the system is built for fairness and transparency, not speed. They take conflicts of interest and independent, data-driven judgment very seriously. People are also very well-behaved (for lack of a better word), since there are clear policies and practices on ethics and government contracting. I am glad to have had experience that environment during my career.

(DARPA is always looking for program WINTER 2020 MEPTEC REPORT | 27

INTERVIEW managers since they rotate through in about four years, so give it a look if you are interested.)

Hobbies/interest other than work?

I follow sports somewhat, especially baseball. I still have the old Bill James Baseball Abstracts from even before my semiconductor packaging days. I used to run (before orthopedic issues presented some constraints), and a highlight was a late-career half-marathon.

It’s unconfirmed, but I believe I set the world record for a 47-year-old first-time half marathon by a father of five with three dogs and a horse. These days (especially during the pandemic) I read a fair amount, and usually have a jigsaw puzzle going. My biggest lifelong hobby though has been trivia. I was on high school and college quiz teams, and even made some money writing questions for several years for College Bowl, “The Varsity Sport of the Mind.” I also made an appearance on “Jeopardy!”

We actually have family trivia nights occasionally with a buzzer system and everything. There are worse ways to shelter-in-place.

Places you’ve traveled for work or fun? Where have you enjoyed most?

My wife loves traveling, and we have been fortunate enough to do several trips to Europe, even when it meant hauling around babies and toddlers years ago.

More recently it has been useful to have the offspring help plan and navigate.

That has been a tremendous bonding experience for all of us. Favorite places have been Cornwall, Normandy, Lisbon, and Venice. (Pretty lucky for a guy from Buffalo!) I even popped in on a few European semiconductor companies on those trips during my Advanced Packaging days, including ESEC in Switzerland, DEK and Dage in the UK, and Atlantic Semiconductor, that OSAT in Wales years ago.

Workwise, I travelled pretty regularly in the early days, often to JEDEC meetings which rotated around the country. (That was so long ago I remember reading newspapers in the back of the big meetings, before scrolling through your phone was an option.)

That was a good way to see some cities that I might not have seen otherwise.

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Jeff’s lifelong hobby of triva led to writing questions for TV’s College Bowl quiz show and an appearance on “Jeopardy!”.

More recently I traveled a fair amount around the country for various DARPA meetings. In spite of being in semiconductors, I have only traveled overseas for work a few times – Japan for a few conferences and company visits, and Finland to visit Nokia, for example.

COVID-19 changes that you think will become permanent?

People say that working remotely will continue for a lot of people, but I’m not so sure. There will definitely be a trend that way, but I think it works now because colleagues already know each other. As new people get added, that pre-pandemic cohesion will be awfully hard to recreate with new employees. I imagine some hybrid scenario will be common. It’s nice to have the flexibility of working at home, but I think it would also help to have some fraction of your work time be in person. There’s still a lot to figure out, beyond the workplace as well.

I think that virtual conferences, or at least virtual access to conferences, will continue. Registration at most events is higher since you don’t need to invest in travel and be absent from an office. It was handy to pick and choose what to see at ECTC whenever you wanted, and still have the proceedings. SEMICON West was a little trickier, since I am more accustomed to just making the rounds and seeing who I see, and that’s hard to re-create. Again, people will figure it out. It’s amazing what those organizers did with such short notice.

Notable industry “luminaries” that you’ve worked with? Stories / experiences to share?

I met many luminaries when I was a member of the press. One thing I haven’t forgotten is Scott Kulicke (head of K&S at the time) saying that anyone who found a new customer at SEMICON should be punished (he phrased it a bit more colorfully), since you should have done all of your homework before then.

At Seagate, Al Shugart was the legendary CEO. He was a smoker, so it was supposedly a good career move to take up smoking to hang out with him in the outdoor smoking area. This was in Bloomington, MN, so you had to be hardy to do that year-round.

When I was with Booz Allen at DARPA, I met Secretary of Defense Ash Carter at a big DARPA event. He was known for actually being an expert on an impressive array of technology.

One last name to drop is Elon Musk.

I met him at a conference on small satellites in 2004 in the early days of SpaceX. He was not nearly as prominent then, but he was still a good draw for a technical event like that. He gave a good keynote and noted that he made a lot of money with PayPal, but he was churning through it at a fast pace by investing in space travel.

And, I don’t know if the Internet counts as a luminary, but I was present for a demonstration of the internet at a DARPA meeting in the early 1990s when I was with nCHIP. I don’t recall being overly impressed at the time …

What was MEPTEC like in the early days? How long have you been a member / on the board?

I do remember attending a MEPPE event or two (before it became MEPTEC), and I have been on the Advisory Board since about 2000. I remember having dinner in San Jose with Bette Cooper and Gary Brown, and I was happy to jump on board which was particularly useful for me since I was still with Advanced Packaging then.

MEPTEC has been remarkably consistent over the years. The one-day focused workshop format has always worked well, especially with Bette running everything so smoothly and making it easier for the board members to contribute without having to worry about the details. And I’m happy to be continuing on with Ira Feldman at the helm. ◆ meptec.org

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