P12-02

Nano‐contacts and Nano‐interconnects: Will they extend Moore’s Law? Dr. Greg Monty, UL LLC, Corp. Research Chairperson, IEC TC113, Nanotechnology Standardization for Electrical and Electronic Products and Systems Page 1

ABSTRACT • CNTs and graphene have superior characteristics (current, resistance) • Need high‐quality electrical contacts • Graphene hoped to be an extension for copper in ICs • Major barriers to success remain – Requirements, Fabrication, Characterization, Performance, Reliability Page 2

CONCLUSIONS • The results from nanoscale contacts and interconnects are falling far short of the requirements and expectations.

• There appear to be difficulties that may be impossible to overcome • Without significant breakthroughs, nanoscale contacts and interconnects may not enable devices, components, products, and systems as many in the research and product development community wish.

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Products and Nano‐contacts • • • • • • • • • •

Semiconductor devices Integrated Circuits Photovoltaic Panels Batteries Flexible electronics Displays Solid‐state lighting Organic LEDs (OLEDs) Printable electronics ALL NEED excellent nano‐structure to bulk‐conductor contacts for low‐resistance current flow Page 4

Nanotubes and Nanofibers, Pros and Cons • Mean free path (MFP) SWCNTs: 1000nm • Mean free path Cu: 40nm • SWCNT current density: 1012 A/cm2 BUT • CANNOT deterministically make 100% metallic bundles • MWCNTs have much shorter MFP – unusable for semiconductors • Oxide formation on nanowires forms barriers to ohmic contacts • Surface effects are significant and degrade contacts Page 5

Nanotubes and Nanofibers Cons, cont’d • Strings of thousands/millions of contacts not demonstrated yet • Process variations still very large – no control • Annealing or thermal processes needed to break down dielectric barriers to form ohmic interface • Correlations of resistance and capacitance to diameter and length do not exist • Connecting to all inner shells of MWCNTs not possible Page 6

Via Interconnects Pros and Cons • Copper limited as technology nodes shrink • SWCNTs current density 1000> than for Cu (theoretically) • SWCNT array resistance 10‐100x lower than for Cu at 30‐nm diameter (theoretically) BUT • 100% metallic arrays are not possible • Experiments do not match theoretical values Page 7

Via Interconnects Issues, cont’d • MWCNTs experiments: 100x less current density; 100x higher resistance than Cu wires same size • Thermal annealing still needed to make good ohmic contacts • Contacting all shells of MWCNT not demonstrated yet • Fabricating millions of vias not possible or demonstrated yet • NO SOLUTION FOR VIAS WITH CNTs HAS BEEN DEMONSTRATED TO DATE. Page 8

Surface (Lateral) Interconnects Issues with CNTs • No research has demonstrated millions of transistors integrated on an IC (mass production) • Perpendicular current flow not demonstrated with low resistance and reliability – Ohmic contacts between all CNTs?

• No alignment of CNTs in orthogonal directions • Only‐metallic nanotubes not feasible for SWCNTs • No demonstration of integration of fabrication with CMOS • Driving CMOS circuits with CNT interconnect performs poorly when normal size drivers were used Page 9

Graphene Interconnects Features Mean Free Path 1 µm Optically transparent High electron mobility 105 cm2/V‐sec Graphene nano ribbons (GNRs) 1010 A/cm2 10x conductivity and more transparent than ITO for displays and touch screens • Fabrication of graphene sheets 1‐m wide • Inexpensive to fabricate • Relatively easy to make ohmic contacts to graphene (Ti/Au, Al/Au, Ni/Au, Cu/Au, Pd/Au, Pt/Au)

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Graphene Interconnects Issues • Difficult to integrate into ICs • Patterning of graphene into GNRs requires atomic‐level control • Preventing surface effects (or establishing control) on graphene is not demonstrated yet • Alignment of graphene orthogonally on IC not demonstrated • Layer morphology, background doping, film stress, defectivity levels all are issues today • Isolated GNRs have better performance compared to GNRs on dielectric layers, and change depending on the type of dielectric layers Page 11

GNR Issues • Edge roughness matters, and can be either zigzag or armchair (and will be different in orthogonal directions) • Atomic width will determine metallic or semiconducting character – Need atomic GNR width control – nearly impossible

• Experiments have not lived up to theoretical predictions (15x‐40x more resistive than Cu at same dimensions) • Bonding and stability of GNRs to under‐layers is not controlled yet Page 12

GNR Issues, continued • Single‐layer graphene will not conduct enough current • Multi‐layer graphene may help this, but – How does one control the number of layers?

– How does one control the GNR width on multiple layers?

– How does one control the interactions between graphene layers – Edge shape and smoothness is still required, and nearly impossible to achieve Page 13

CONCLUSIONS • The results from nanoscale contacts and interconnects are falling far short of the requirements and expectations.

• SWCNTs, MWCNTs, CNFs, and graphene have not been demonstrated to be useful in ICs • Without significant breakthroughs, nanoscale contacts and interconnects may not enable devices, components, products, and systems as many in the research and product development community wish.

• The Grand Challenge remains….the extension of Moore’s Law with new conductors and contacts Page 14