The Definitive Guide to Outsourcing Semiconductor Design Projects: What You Need to Know Now!
Contents
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Executive Summary
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Project Challenges
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Are Traditional Project Approaches Working?
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Risks of Not Succeeding
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Damage Tolerant Design Process
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Alternatives for a Successful Design
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Considering Design Outsourcing
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The Next Step
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References
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About Cyient
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The primary focus for setting regulatory requirements is to limit structural damage and to enhance flight safety during the service life of the aircraft.
Executive Summary
IP Migration
Designing and verifying a System-on-Chip (SoC) , Application Specific Standard Part (ASSP), Application Specific Integrated Circuit (ASIC) using Customer Owned Tooling (COT) or FPGA technology for your next electronic product can be a daunting task, especially when trying to meet time to market goals while being confined to a fixed budget using available engineering talent. Some of the typical barriers to success can be:
Semiconductor Intellectual Property blocks are often re-used between projects, yet when you move from one process node to another, each hard IP block will have to be migrated, requiring design, verification, and physical implementation. Ideally, you would be able to purchase quickly all of the necessary IP for each new process node. However, in reality there are likely many custom IP cells and blocks that require migration because they are simply not yet available on the market2.
• There’s not enough engineering staff to complete the project on time • Existing engineers may not have the right skills • Hiring new employees takes too much time
Project Challenges Planar to FinFET Perhaps you’ve done designs at 28 nm in planar CMOS processes, and want to now move into FinFET design at the 16 nm, 14 nm or even 10 nm nodes in order to meet stringent requirements of large gate count, fastest performance or lowest power. The design and layout of FinFET (aka Tri-Gate by Intel) devices are quite different from planar devices, plus there’s an explosion of DFM (Design For Manufacturing) rules and guidelines that require new EDA tools and flows1.
IP Selection and Use A modern SoC can include hundreds of IP blocks from a multitude of intellectual property providers, so selecting, integrating and verifying the right IP is a critical success factor3. Should your team build the IP or buy IP off the shelf? Are you a domain expert for every IP block and protocol required? The most popular processor cores around are from leading companies like ARM, Imagination Technologies, Synopsys, and Cadence. Unless you have a processor design team with hundreds of engineers like Apple, Intel or Samsung you likely will choose a processor core from an IP provider.
Traditional Planar
Drain
Gate Drain
High-k Dielectric Source Oxide Silicon Substrate
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3D FinFET
Traditional 2-D planar tansistor form a conducting channel in the silicon region under the gate electrode when in the “on” state.
Gate
Source Oxide Silicon Substrate
3-D Tri-Gate transistor form conducting channels on three sides of a verticals fin structure, providing “fully depleted” operation
Over the years, major airplane accidents have highlighted problems due to aging airplane structures including airframe structural fatigue, and issues related to maintenance, inspection, and repairs.
Fig. 1 | Custom 8 bit pipelined ADC with 200MSPS, TSMC 65 nm
Design and Verification Languages RTL design and verification are based on standard languages like VHDL4 and SystemVerilog5, plus you could even be required to mix these languages together on a project based on the IP source. Even though VHDL started out in the 1980’s the latest revision is IEEE 1076-2008. SystemVerilog was introduced in 2002, and the most recent release is IEEE 1800-2012. For analog and AMS6 blocks, the two most popular languages are VHDL-AMS and Verilog-AMS7. Both your design and verification engineers should be up to date on the latest versions of these HDL languages to work most efficiently with each other and with the widest range of IP providers. Design teams must segregate into separate design and verification functions to minimize the time to debug the chip and produce the 02
highest quality of results. The more complex the chip, the greater the ratio of verification engineers to design engineers8. Verification engineers will find more bugs in a design block than the original design engineer because they don’t have the same preconceived notions of how the block was created. Having excellent communication between design and verification engineers is essential to creating new IP blocks that meet the specifications. Verification engineers have been rapidly adopting the Universal Verification Methodology (UVM)9 as a way to improve interoperability and reduce the costs of buying and writing Verification IP (VIP) for every new project or EDA tool. Using UVM also makes it easier for your team to reuse verification components. Limiting your verification approach to ad-hoc methods will only slow down the project.
When a damage is identified in an aircraft during inspection, it is either repaired according to procedures and guidelines provided in manufacturers’ standard repair. Documents such as SRM, SB, RAG, or a new repair is approved
Test Env I2C Agent Sequencer
Cfg
Register Model
I2C Monitor
Ramp Monitor
VCO_SEL Monitor
I2C Driver
Load Select Monitor
SDA
SCL
CLK
Interface DUT Fig. 1 | AMS UVM Verification Environment
Design Process Having experience in the front-end flow requires many skills: • RTL entry • Functional simulation • Verification • Logic synthesis • DFT and ATPG The back-end flow also has a different set of steps and skills required: • Partitioning • Floor planning • Placement • Custom IC layout • Clock tree synthesis • Signal routing • Timing Closure • DFM • Physical verification with DRC and LVS 03
Product Definition & Design
RTL Design
Functional Verification
Planning / Partitioning
Synthesis
DFT
Physical Design with Timing Closure Physical Verification and Tape out Productization & Implementation
A structure is said to be damage tolerant if it resists fracture from the already existing cracks for a given period of time. Damage tolerant structures can be divided into two major groups.
Each of these steps requires access to EDA tools, a proficient level of training, iterations to meet the specification, and plenty of CPUs and cores to run the software in a reasonable amount of time. When moving from a 28 nm process node to a 16 nm or 14 nm node the amount of CPU time required goes up by about a factor of 3X.10 ASIC versus FPGA Design High volume and high-performance SoC designs tend to be implemented as an ASIC while lower volume and lower performance designs can meet your specifications as an FPGA implementation. The IP available and design methodologies are similar, yet the EDA tool flows will be quite different between these alternatives, and there’s always a learning curve for any new or unfamiliar device. Back in 201011 it was estimated that there were 2,500 ASIC design starts versus 90,000 FPGA design starts, so the popularity of FPGA design continues to increase today. Many ASIC projects will do an FPGA prototype as a way to better verify functionality and performance, or even run software more quickly before the chip is ready12. There are many commercial products for FPGA prototyping, or an alternative is to create your own if the team has this skill set and time.
Are Traditional Project Approaches Working? In the preceding section, we listed all of the specialized steps, skills, and EDA tools required to design a modern chip. Building up your engineering staff to cover the breadth and depth of skills can be a time consuming and an expensive proposition to many departments and companies. Two immediate options are to hire new talent or consultants to fill the gaps in your team. With those options, your challenge is to get the right people with the right experience on a budget that you can afford. 04
Multi-national companies could have their design centers in places like India, Taiwan or Europe. Having access to these engineering resources in the required timeframe and skill sets can be problematic. The management overhead to coordinate a multi-site project and keep the communication flowing can be a real headache and source of missed deadlines and failed market windows.
Risks of Not Succeeding If your present team and approach aren’t sufficient then the likely outcomes are: • Late project – causing lost product revenue or declining market share • Multiple silicon spins – increasing NRE costs, delaying time to market and time to revenue • Broken team morale – key talent is likely to get frustrated and walk out the door to join a more successful team that does get to market in time
Alternatives for a Successful Design If you need to meet an aggressive semiconductor product development schedule, then one ideal approach is to hire your own team with existing experience, and hit the ground running using a budget that can support sufficient EDA tools, IP and CPUs. Mid-stream into a project you may find that using your set budget and approach that you cannot possibly fulfill all marketing features, so by removing features or lowering performance metrics you may still be able to get to market with a somewhat lesser product and position. As time runs out on your schedule, another approach is to decrease the amount of verification or software integration testing, hoping for the best that silicon samples will plugin and just work.
With each of these three alternatives, there are risks involved. Staffing your own team takes precious time to find engineers, interview them, make an offer, hire them, get through relocation, add training, and see if they gel with their co-workers and can be productive. Hiring new college graduates is always less expensive than hiring experienced engineers; however, the learning curve and time to proficiency could slow down your entire project to the point that it starts to fail. Getting to market with fewer features or lower specifications may be the tipping point, causing the market to reject your product in favor of the competition who does have all the characteristics and with better specifications. A rushed product is more likely to have undetected bugs that turn out to frustrate early users of your design, and ultimately cause them to look for another vendor. Another alternative worthy to look at is a flexible workforce, one that can expand as needed to complement your existing engineering team, and then engage your services partner to satisfy your peak product development and verification demands. This strategy of augmenting your team with just in time talent from a design services company will enable you to scale in a controlled and very flexible manner.
Considering Design Outsourcing A recommended approach is to consider complementing your existing design team with specialists from an outsourcing services company. This kind of approach can provide you with: • The exact talent that you need, when you need it • Domain experience in particular IP building blocks (SERDES, ARM cores, WiFi, etc.) • A local, certified project manager to keep the project and people in synch 05
• Affordable design resources where EDA tool licenses and people can follow the sun and get three shifts in per 24 hours • Experienced talent on demand, no waiting or training required With outsourcing, your team would face lower risks because of the skilled engineers working on the project, provided at a lower cost than hiring and training your engineers. You could do more work and higher quality design and verification work with your fixed budget by adding outsourced engineers. Adding some design outsourcing may sound too good to be true, so it’s natural to be skeptical. Finding the right design outsourcing company is possible, especially if you have criteria and ask them to prove their capabilities with questions like: • Years in business • Type of design projects completed, and size of client companies • Size and experience of engineering staff • Project management approach • Span of engineering experiences available • Experience with semiconductor IP • Digital experience • Analog experience • AMS experience • Foundry partners • Support of all the major EDA tools and flow, even inter-mixed tool flows • First-pass silicon success rate
The Next Step
References
It is possible to ensure greater success for your next SoC or ASIC design project by adding design outsourcing to your design and verification project. This approach has been demonstrated countless times before at tier-one fabless and Integrated Device Manufacturing (IDM) companies.
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If you are considering exploring companies with broad semiconductor domain experience, please download the whitepaper titled “15 Reasons Cyient Outshines Other Semiconductor Design Service Providers” and learn how 15 years of first-pass silicon success across more than 250 semiconductor designs/tape-outs while working with bluechip semiconductor companies with the latest technology node can do for you.
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FinFET History, Fundamentals, and Future. 2012 Symposium on VLSI Technology Short Course 2 Migrating Hard IP from one node to another, SemiWiki, June 2015 3 Using 3rd Party IP in ASIC/SoC Design, Design & Reuse 4 VHDL, Wikipedia 5 SystemVerilog, Wikipedia 6 VHDL-AMS, Wikipedia 7 Verilog-AMS, Wikipedia 8 The 2012 Wilson Research Group Functional Verification Study 9 Standard Universal Verification Methodology 10 Crossing the Great Divide: How to Safely Navigate the Move from 28nm to 16FF+, DAC 2015 11 What’s the number of ASIC versus FPGA design starts? EE Times 12 FPGA Prototyping. Tech Design Forum
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