Alex K. Jones, PhD

Professor

Professor, Computer Science (courtesy)

1128 Benedum Hall | 3700 O’Hara Street | Pittsburgh, PA 15261 P: 412-624-9666 C: 412-447-1150

akjones@pitt.edu www.pitt.edu/~akjones

The parallelism and heterogeneity of new computing systems have led to a myriad of new opportunities in the design of computer architectures and systems. My research focuses on methods to allow compilers, operating systems, and computer architectures to work together in enabling higher levels of performance, improving energy efficiency, and increasing reliability and robustness of next-generation computer systems. This form of cross-layer research enables optimizations that can achieve orders of magnitude of improvement over techniques that address each layer individually. I am also active in computing for sustainability. As a member of the Pitt’s Mascaro Center for Sustainable Innovation (MCSI), my work has investigated lightweight grid computing, computing/sensing hubs to support life-cycle assessment of larger systems such as buildings, emerging non-volatile memory research to support ultra-low energy computing, and balancing environmental impacts from the manufacturing and use-phases of integrated circuits. Further, I am active in interdisciplinary electrical, computer, and biological research related to development of medical instruments. My research is funded both by the National Science Foundation (NSF) and industry partners. Moreover, I collaboratively developed and direct a new NSF I/UCRC center called Nexys, which brings together industry, government, and multi-university collaborations to form multidisciplinary teams to address collectively identified key research challenges in computing.

Cross-layer Computer System Design

A key limiting factor of modern computer systems is data access latency, motivating the employment of every increasing cache size. My research shows that data access locality can often be discovered through software-layer or compiler analysis and communicated to the architecture through the operating system in a cross-layer fashion. This information can be used to improve the efficiency of architectural components such as caches and on-chip networks between processors in multi-core environments. Further, improved methods to access memory in a comprehensive fashion are possible compared with examining each system level or component in isolation. As such, crosslayer optimization often leads to dramatic improvements in performance and energy. My research is based on the premise that system layers should be designed cooperatively to improve data access latency. Thus, application information extracted from higher system levels such as from the compiler can be used throughout the system layers to optimize the whole system. An example contribution of my work would be classification of data for parallel applications, which can be used to keep data local to the core that uses it in a chip multiprocessor (CMP). Further, the shared memory concept and nonuniform cache architectures (NUCA) that ease the programmer’s burden for leveraging parallelism in CMPs can also obscure the implied data partitioning and communication of the underlying parallel algorithm. My research also detects and recovers this information at various levels and uses it to guide data placement in distributed caches and optimize the interconnect to reduce communication delays. Further, my research leverages application data access characteristics to enable integration of new and traditional non-volatile memory technologies (e.g., flash, STT-RAM) by mitigating their asymmetric access properties.

Interdisciplinary Computing Research

I work closely with other disciplines to employ optimized computing in Operating and innovative ways. One example is the Runtime System development of a lightweight grid and sensor hub called Ocelot and Lynx, respectively (Figure), which supports dynamic life-cycle assessment research crossing the borders of civil Memory and mechanical engineering. I am also Organization involved in developing lightweight, massively parallel sensor hubs for lowcost patient testing and monitoring. Through my research and service I am a leader of community-wide efforts to improve the scientific method of computer science research and develop a new vision for next generation design technology and automation of computing in light of new technologies and levels of scale.

Compiler Interconnection Network

Ad-hoc node Dedicated WSN node Dashboard and server complex