Ijcot v5p309

International Journal of Computer & Organization Trends – Volume 5 – February 2014

Implementation of Encoder and Adaptive Viterbi Decoder 1

Manashree Nayak, 2 Praveen Kumar Y.G, 3Dr. M Z Kurian 1 th

4 SEM, M.Tech (Digital Electronics), SSIT, Tumkur 2

M.Tech, Lecturer, Dept. of E&C, SSIT, Tumkur

3

HOD, Dept. of E&C, SSIT, Tumkur, Karnataka

Abstract-----Adaptive viterbi decoder is used for decoding codes of long constraint length, where as viterbi decoder is used for decoding short constraint lengths. In order to minimize power consumption and BER, Radix2 ACS Adaptive Viterbi decoder has been proposed. The area consumption is less in viterbi compared to Adaptive Viterbi decoder. But the power consumption is much less in radix 2 ACS Adaptive Viterbi decoder when compared to other decoders.

Keywords: -Bit error rate (BER), Adaptive Viterbi Decoder (AVD), Convolutional Encoder, Radix2 Add Compare Select (ACS).

1. INTRODUCTION Convolutional coding is type of error correcting code in which each m bit information symbol is transformed into n bit symbol where m/n is code rate. Convolutional codes are frequently used to correct errors in noisy channels. They error correcting capability and perform well even on very bad channels. Convolutional coding has been used in communication systems including deep space Communications and wireless communications.

Convolutional codes offer an alternative to block codes for transmission over a noisy channel.

Convolutional coding can be applied to a Continuous input stream (which cannot be done with block codes), as well as blocks of data.

A Convolutional encoder is a Mealy machine, where the output is a function of the current State and the current input. It consists of one or more shift registers and multiple XOR gates. The Stream of information bits flows in to the shift register from one end and is shifted out at the other end. XOR gates are connected to some stages of the shift registers as well as to the current Input to generate the output. There is no theoretical basis for the optimal location of the shift Register stages to be connected to XOR gates. It is based on an empirical approach. The encoder produces three bits of encoded information for each bit of input Information, so it is called a rate 1/3

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encoder. A Convolutional encoder is generally characterized in (n, k, and m) format.

Viterbi decoding is an optimal algorithm for decoding convolution code in maximal likelihood sense. A Viterbi decoder is an important target for power reduction in many low-power communication devices. It can account for more than one-third of power consumption during baseband processing in current generation cellular telephones. As integrated circuits continue to become smaller and faster, the appeal of higher complexity Viterbi decoders for higher memory order convolution codes increases. Its main drawback is that the decoding complexity grows exponentially with the code length. So, it can be utilized only for relatively short codes. To overcome this problem, the adaptive Viterbi Decoder (AVD) has been proposed.

Adaptive viterbi decoder is used for decoding codes of long constraint length. In order to minimize power consumption and BER, Radix2 ACS adaptive viterbi decoder has been proposed. The goal of adaptive Viterbi is to reduce the average computation and path storage required by the Viterbi algorithm.

Instead of computing and retaining all possible paths, only those paths which satisfy cost conditions (1.path is less than min cost of all surviving path 2.total number of survivor path is limited to fixed no Nmax) are retained for each received symbol at each state node. Power reduction in AVDs has been achieved by either reducing the number of states (reduced-state sequence decoder), the size of survivor memory, or the number of trellis paths (limited-search trellis) at the expense of increased BER and reduced throughput.

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International Journal of Computer & Organization Trends – Volume 5 – February 2014 2.

SYSTEM DESIGN

A high level view of adaptive Viterbi decoder architecture is shown in Figure 2.1. The decoder contains a data path and an associated control path.

The data path is split into four parts: the Branch Metric Generators (BMG), Add Compare Select (ACS) units, the survivor memory unit, and path metric storage and control. The BMG unit determines distance between received and expected symbols.

The ACS unit determines path costs and identifies the lowest cost path. The survivor memory stores lowest cost bit sequence path on decisions made by the ACS units. The flow of data in the data path and the storage of results are determined by the control path.

Figure 2.1 Adaptive viterbi decoder The first unit in AVD is branch metric unit (BMU). It is the simplest block in the Viterbi decoder design.BMU calculates the distance (metric) between the received noisy symbol and the output symbol of the state transition (branch).The received data symbols are compared to the ideal outputs of the encoder from the transmitter and branch metric is calculated. Hamming distance or the Euclidean distance is used for branch metric computation.

The ACS unit determines the path costs and identifies lowest-cost path. The ACS unit recursively accumulates the branch metrics to path metrics for all the incoming paths of each state and selects the path with minimum path metric as the survivor path.

When more than one path arrives to a state, ACS unit selects the path with the lowest metric value, which is the survivor path. The PMU accumulates the distances of the single state. Corresponding branch metrics are added to the previously stored path metrics which are initialized with zero values. The

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resulting values are compared with each other and the smaller value is selected and stored as the new path metric for each state.

The survivor memory stores lowest cost bitsequence paths based on decisions made by the ACS units. The survivor memory unit receives decisions from the PMU and produces the decoded sequence.

There are two major techniques to implement the SMU: Register exchange (RE) and Trace-back (TB).

RE uses a set of multiplexers and registers to store and update the survivor sequence of each state for trace back depth (TBD) trellis stages. It is highly regular, area efficient and has low latency. But, due to frequent switching of states in the registers (bits are physically shifting from one stage to the next), it consumes a lot of power especially for larger values of TBD. The TB stores the decisions in an SRAM and reads them in reverse order during the trace-back cycle. As the update rate of the memory is much less than the update rate of the registers in the RE technique, the power consumption is significantly reduced. TB is split in three major operations, write, merge, and decode. In each cycle, 1 column of decisions is written into memory and other columns are read for trace-back and decode. Pointers are used to keep track of the column read. In the TB method, the storage can be implemented as RAM and is called the path memory. Survivor path storage stores the survivor path metric for further computation and decision regarding whether it is lesser than threshold or not. Output decoding block produces decoded bits.

The flow of data in the data path and the storage of results is determined by the control path. It provides the synchronization and initiates the control signals to all blocks. Path metric array holds per-state path metrics.BM selects expected symbol value (BMselect) is used to select the appropriate branch metric from the BMG.The branch metric value is combined with the path metric of its parent present state to form a new path metric. The output of the ACS units includes path valid signals which indicate which of the paths have survived pruning.

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International Journal of Computer & Organization Trends – Volume 5 – February 2014 3. RESULT ANALYSIS The Simulation result of Encoder is shown in Figure3.1.

Figure 3.1. Result of Encoder

The Simulation result of ACS2 is shown in Figure3.2

Figure3.2. Result of ACS2

The Simulation result of FIFO is shown in Figure 3.3

Device utilization summary: Logic utilization

used

available

Utilization

No of slices

3701

5472

67%

No of flip flop No of 4 input LUTS

2556

10944

23%

6811

10944

62%

No of bonded IOBS No of GCLKS

7

320

2%

2

32

6%

4.

CONCLUSION

VHDL program has been developed for Encoder and Decoder and results for different inputs are observed. Viterbi Encoder and Decoder is implemented on virtex4 FPGA. The decoder uses Trace Back approach for decoding .the design is implemented on an FPGA operating at 50 MHz .A total of Slices (67%) is used for the implementation.

Implementing Adaptive Radix2 ACS has reduced the computational resources, memory, noise tolerance, and power consumption in AVD. The power consumption for Adaptive Radix2 ACS has been analyzed. Adaptive Radix2 ACS is best for decoding and to achieve minimum power consumption.

REFERENCES [1] Error Resilient Low power Viterbi decoder Architectures.IEEE Transactions on signal processing, volume 57, no.I2, Dec 2009.

[2] Low power Adaptive Viterbi decoder with FACSU. EJSR European Journals volume 60 issue no.4

Figure 3.3 Result of FIFO

The Simulation result of Decoder is shown in Figure 3.4

[3] Design Exploration of hard decision viterbi decoding: Algorithm and VLSI implementation.

[4] F. Chan and D. Haccoun, "Adaptive Viterbi decoding of convolution Codes over memory less channels," IEEE Transaction on Communications, vol. 45, no. 11, pp. 13891400, Nov. 1997.

Figure 3.4 Result of Decoder

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