International Journal of Engineering Trends and Technology (IJETT) – Volume 7 Number 1- Jan 2014
Design of Low Power Basic 2x1Multiplexer Using Various Gates S. Ahmed Basha#1, K.Prasad Babu*2,H.Devanna #3, B.Venkatesh*4 #
E.C.E. Department, Assistant Professor Assistant Professor Associate Professor, Assistant Professor, JNTU Anantapur. University India St.John’s College of Engineering & Technology, Yemmiganur, 518360, Kurnool, Andhra Pradesh,India.
Abstract—Power dissipation is one of the important factor in VLSI design. All the systems with high performance have constraints regarding power consumption per chip. Low power consumption is generally done by careful design. In this paper we are designing the basic 2x1 multiplexer using various gates. We represent the low power dissipated multiplexer among them.
Table 2.When S=1
Inputs
Output
x1
x2
t
0
0
0
0
1
1
Keywords—MUX ;Complex Gates;PASS Transistor;
1
0
0
Transmission Gates;Power;
1
1
1
I. INTRODUCTION Multiplexer: It is the device that has 2n inputs and number of select lines by which the input line is send to the output line. Multiplexers in short are called as MUX. Mux’s are used for incrementing the information that has to be sent over the channel/network within the duration of time, with allotted bandwidth. Data selector is the other name of Mux. It is used for multiple inputs with one output at atime. The basic operation of 2x1 Mux is mentioned below table Basic Operation of 2x1 MUX: Table 1.When S=0
Inputs
Output
x1
x2
t
0
0
0
0
1
0
1
0
1
1
1
1
ISSN: 2231-5381
Basic operation of Transmission gates: Transmission gate is the one that momentarily allow or stop a voltage level from input side to output side. Transmission gate is composed of both pMOS and nMOS transistors. The operation of control gate is in such a way that complementary output is observed, i.e. When Logic 1 is applied at node A Logic 0 is seen at node active low A. Thus both transistors conduct and pass the voltage level at IN to OUT. And when Logic 0 on node active-low A is applied the complementary Logic 1 is applied to node A, thus both transistors are off and which gives us a highimpedance state at both the IN and OUT nodes. Thus we have 3 states high, low and high-impedance.
The Schematic, Circuit, Layout symbols are shown below
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