Chapter 8 Counter
Asynchronous (Ripple) Counter Synchronous Counter
Objectives
• At the end of this chapter, students should be able to:• Differentiate between asynchronous counter and synchronous counter. . • Design an asynchronous counter. • Design a synchronous counter. • Analyse a synchronous counter.
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Counters
• Flip-flops are wired together to form binary counters. • They are used to measure the frequency of a signal and are used in digital clock. • Counters characteristics: – Modulus of counter - the maximum number of counts to complete the counting cycles. – Can count either up or down. – Can operate asynchronously (ripple) or synchronously. – Free running or self stopping.
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Asynchronous (Ripple) Counter • Also known as ripple counter. • Example: Modulo-4 or mod-4 counter. • A counter that counts from 00 to 11 (0 to 3) is called modulo-4 or mod4 counter. • The modulus of a counter is the number of counts the counter goes through. • Note that each flip-flop is in its toggle mode. • Each flip-flop output drives the CLK input of the next flip-flop. 1 J
Clock pulse
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SET
Q
A
1 K Q CLR
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1 J SET Q
A
B
B
1 K CLR Q
4
Asynchronous (Ripple) Counter • The clock pulse is applied to the clock of flip-flop A. • The output of flip-flop A is connected to the clock of flip-flop B. • Flip-flop A will toggle (change to its opposite state) each time a clock pulse make a transition. • The output of flip-flop A will acts as the clock for flip-flop B, and so the output B will toggle each time A goes from transition. • The counting sequence is 00, 01, 10, 11. CLK
0
1
2
3
4
5
6
7
8
9
B A AB
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00
01
10
11
00
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01
10
11
00
01
5
Synchronous Counter • •
Synchronous counters can be designed to produce special purpose count sequences of nonconsecutive numbers (0, 2, 4,6). Excitation table Present Next J State (PS) State (NS)
K
Mode
0
0
0
x
Hold (00) or Reset (01)
0
1
1
x
Toggle(11) or Set (10)
1
0
x
1
Toggle (11) or Reset (01)
1
1
x
0
Hold (00) or Set (10)
0X
X0 1X 0
1 X1
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Design a Synchronous Counter Example:
Design a synchronous counter t0 count the following sequence: 0, 1, 2,3,0…. Draw the state transition diagram 0 1 2 3 Steps: 1
2
Derive the excitation table
Present State
Next State
JK
PS
A
B
NS
A’
B’
JA
KA
JB
KB
0
0
0
1
0
1
O
x
1
x
1
0
1
2
1
0
1
x
x
1
2
1
0
3
1
1
x
0
1
x
3
1
1
0
0
0
x
1
x
1
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0X
X0 1X 0
1 X1
7
Synchronous Counter 3
Simplify the JK expressions using Karnaugh map
A
A
B
B
1
A
x
B
x
x
B
x
JA = B
1
KA= B
A
A
B
1
1
B
x
x
JB = 1 10/9/2012
A
A
A
B
x
x
B
1
1
KB = 1 RA/Sept2012-Jan2013
8
Synchronous Counter 4
Draw the synchronous counter circuit A
B 1
J
SET
Q
J
SET
Q
K
CLR
Q
K
CLR
Q
JA = B KA = B
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JB = 1 KB = 1
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Synchronous Counter Analysis Analyse the following synchronous counter circuit. A
B
C 1
1
SET
Q
J
SET
Q
J
SET
Q
K
CLR
Q
K
CLR
Q
K
CLR
Q
Identify the J and K expressions
JA = ? KA = ? 10/9/2012
J
JB = ? KB = ?
JC = ? KC = ?
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Synchronous Counter Analysis 2
Derive the excitation table.
JA = BC KA =BC
JB = C KB = C
JC = 1 KC = 1
Present State
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PS
A
B
C
0
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
Next State NS A’ B’ C’
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JK JA
KA
JB
KB
JC
KC
11
Synchronous Counter Analysis 2
Derive the excitation table.
JA = BC KA =BC
JB = C KB = C
JC = 1 KC = 1
Present State
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PS
A
B
C
0
0
0
1
0
2
Next State NS A’ B’ C’
JK JA
KA
JB
KB
JC
KC
0
0
0
0
0
1
1
0
1
0
0
1
1
1
1
0
1
0
0
0
0
0
1
1
3
0
1
1
1
1
1
1
1
1
4
1
0
0
0
0
0
0
1
1
5
1
0
1
0
0
1
1
1
1
6
1
1
0
0
0
0
0
1
1
7
1
1
1
1
1
1
1
1
1
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Synchronous Counter Analysis Input
2
Derive the excitation table.
JA = BC KA =BC
JB = C KB = C
JC = 1 KC = 1
Present State
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CLOCK
PS
A
B
C
0
0
0
0
1
0
0
2
0
3
Output
J
K
Q
Mode
0
0
Q
Hold
0
1
0
Reset
1
0
1
Set
1
1
Q
Toggle
Next State
JK
NS A’ B’ C’
JA
KA
JB
KB
JC
KC
0
0
0
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
4
1
0
0
0
0
0
0
1
1
5
1
0
1
0
0
1
1
1
1
6
1
1
0
0
0
0
0
1
1
7
1
1
1
1
1
1
1
1
1
1
0
0
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1
13
Synchronous Counter Analysis Input
2
Derive the excitation table.
JA = BC KA =BC
JB = C KB = C
JC = 1 KC = 1
Present State
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CLOCK
J
K
Q
Mode
0
0
Q
Hold
0
1
0
Reset
1
0
1
Set
1
1
Q
Toggle
Next State
PS
A
B
C
0
0
0
0
1
0
0
1
0
0
1
2
0
1
2
0
1
3
0
4
Output
JK
NS A’ B’ C’
JA
KA
JB
KB
JC
KC
1
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
5
1
0
1
0
0
1
1
1
1
6
1
1
0
0
0
0
0
1
1
7
1
1
1
1
1
1
1
1
1
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Synchronous Counter Analysis Input
2
Derive the excitation table.
JA = BC KA =BC
JB = C KB = C
JC = 1 KC = 1
Present State
10/9/2012
CLOCK
J
K
Q
Mode
0
0
Q
Hold
0
1
0
Reset
1
0
1
Set
1
1
Q
Toggle
Next State
PS
A
B
C
0
0
0
0
1
0
0
1
0
0
1
2
0
2
0
1
0
3
0
3
0
1
4
1
5
Output
JK
NS A’ B’ C’
JA
KA
JB
KB
JC
KC
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
1
0
0
1
1
1
1
6
1
1
0
0
0
0
0
1
1
7
1
1
1
1
1
1
1
1
1
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Synchronous Counter Analysis Input
2
Derive the excitation table.
JA = BC KA =BC
JB = C KB = C
JC = 1 KC = 1
Present State
10/9/2012
CLOCK
J
K
Q
Mode
0
0
Q
Hold
0
1
0
Reset
1
0
1
Set
1
1
Q
Toggle
Next State
PS
A
B
C
0
0
0
0
1
0
0
1
0
0
1
2
0
2
0
1
0
3
3
0
1
1
4
4
1
0
5
1
6 7
Output
JK
NS A’ B’ C’
JA
KA
JB
KB
JC
KC
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
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Synchronous Counter Analysis Input
2
Derive the excitation table.
JA = BC KA =BC
JB = C KB = C
JC = 1 KC = 1
Present State
10/9/2012
CLOCK
J
K
Q
Mode
0
0
Q
Hold
0
1
0
Reset
1
0
1
Set
1
1
Q
Toggle
Next State
PS
A
B
C
0
0
0
0
1
0
0
1
0
0
1
2
0
2
0
1
0
3
3
0
1
1
4
1
0
0
5
1
0
6
1
7
1
Output
JK
NS A’ B’ C’
JA
KA
JB
KB
JC
KC
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
0
0
1
1
4
1
0
0
1
1
1
1
1
1
5
1
0
1
0
0
0
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
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Synchronous Counter Analysis Input
2
Derive the excitation table.
JA = BC KA =BC
JB = C KB = C
JC = 1 KC = 1
Present State
10/9/2012
CLOCK
J
K
Q
Mode
0
0
Q
Hold
0
1
0
Reset
1
0
1
Set
1
1
Q
Toggle
Next State
PS
A
B
C
0
0
0
0
1
0
0
1
0
0
1
2
0
2
0
1
0
3
3
0
1
1
4
1
0
5
1
6 7
Output
JK
NS A’ B’ C’
JA
KA
JB
KB
JC
KC
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
0
0
1
1
4
1
0
0
1
1
1
1
1
1
0
5
1
0
1
0
0
0
0
1
1
0
1
6
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
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Synchronous Counter Analysis Input
2
Derive the excitation table.
JA = BC KA =BC
JB = C KB = C
JC = 1 KC = 1
Present State
10/9/2012
CLOCK
J
K
Q
Mode
0
0
Q
Hold
0
1
0
Reset
1
0
1
Set
1
1
Q
Toggle
Next State
PS
A
B
C
0
0
0
0
1
0
0
1
0
0
1
2
0
2
0
1
0
3
3
0
1
1
4
1
0
5
1
6 7
Output
JK
NS A’ B’ C’
JA
KA
JB
KB
JC
KC
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
0
0
1
1
4
1
0
0
1
1
1
1
1
1
0
5
1
0
1
0
0
0
0
1
1
0
1
6
1
1
0
0
0
1
1
1
1
1
1
0
7
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
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Synchronous Counter Analysis Input
2
Derive the excitation table.
JA = BC KA =BC
JB = C KB = C
JC = 1 KC = 1
Present State
10/9/2012
CLOCK
J
K
Q
Mode
0
0
Q
Hold
0
1
0
Reset
1
0
1
Set
1
1
Q
Toggle
Next State
PS
A
B
C
0
0
0
0
1
0
0
1
0
0
1
2
0
2
0
1
0
3
3
0
1
1
4
1
0
5
1
6 7
Output
JK
NS A’ B’ C’
JA
KA
JB
KB
JC
KC
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
0
0
1
1
4
1
0
0
1
1
1
1
1
1
0
5
1
0
1
0
0
0
0
1
1
0
1
6
1
1
0
0
0
1
1
1
1
1
1
0
7
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
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Synchronous Counter Analysis
3
Draw the state transition diagram
0
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1
2
3
4
5 6
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21