8251 USART
R. Theagarajan, ME., MSc., PhD Rtd. Professor in Engineering email: rtheagarajan@yahoo.com rtrajan59@gmail.com
Basic communication
Parallel communication Centronics connector
Basic communication
Parallel communication
Serial communication
Centronics connector
RS-232 9-pin connector
Communication modes Simplex Data is transmitted in one direction only
Half duplex This method is used when two devices transfers the data alternatively, one at a time. Full duplex This method is used when two devices transfers the data simultaneously in both direction.
Serial communication connector
System communication
Transmission logic For Receiving device to interpret bit pattern correctly, it must able to determine the following • Bit Synchronization Start of each bit cell period • Character Synchronization Start and end of each character or byte • Frame Synchronization Start and end of each complete message block(frame) Types Synchronization Asynchronous Transmission Synchronous Transmission
Asynchronous Communications • Eliminates the need for a clock signal between two microprocessor based systems Transmit data
Receive data System 1
Common ground
System 2
Synchronous Communications Transmit data Receive data System 1
clk Common ground
System 2
Features of 8251 • 28 pin DIP package. • All inputs and Outputs are TTL compatible.
Features of 8251 • 28 pin DIP package. • All inputs and Outputs are TTL compatible. • Synchronous and Asynchronous operation.
Features of 8251 • 28 pin DIP package. • All inputs and Outputs are TTL compatible. • Synchronous and Asynchronous operation. • Synchronous 5-8 bit characters, Automatic sync insertion.
Features of 8251 • 28 pin DIP package. • All inputs and Outputs are TTL compatible. • Synchronous and Asynchronous operation. • Synchronous 5-8 bit characters, Automatic sync insertion. • Asynchronous 5-8 bit characters, Clock rate-1, 16 or 64 times baud rate, Break characters generation, Automatic break detection, Stop bits 1 or 1 ½ or 2
Features of 8251 • 28 pin DIP package. • All inputs and Outputs are TTL compatible. • Synchronous and Asynchronous operation. • Synchronous 5-8 bit characters, Automatic sync insertion. • Asynchronous 5-8 bit characters, Clock rate-1, 16 or 64 times baud rate, Break characters generation, Automatic break detection, Stop bits 1 or 1 ½ or 2 • Baud rate, Syn : dc to 64k, Asyn : dc to 20k
Features of 8251 • 28 pin DIP package. • All inputs and Outputs are TTL compatible. • Synchronous and Asynchronous operation. • Synchronous 5-8 bit characters, Automatic sync insertion. • Asynchronous 5-8 bit characters, Clock rate-1, 16 or 64 times baud rate, Break characters generation, Automatic break detection, Stop bits 1 or 1 ½ or 2 • Baud rate, Syn : dc to 64k, Asyn : dc to 20k • Full duplex, Double buffered Transmitter / Receiver.
PIN diagram of 8251 D2 D3
D4 D5 D6 D7
D1 D0
PIN diagram of 8251 D2 D3
D1 D0
D4 D5 D6 D7 TxC TxD TxEmpty
TxRdy
PIN diagram of 8251 D2 D3 RxD
D1 D0 RxC
D4 D5 D6 D7 TxC TxD TxEmpty
RxRdy
Sync/BD TxRdy
PIN diagram of 8251 D2 D3 RxD D4 D5 D6 D7 TxC
RxRdy
D1 D0 RxC DTR RTS DSR
TxD TxEmpty CTS Sync/BD TxRdy
PIN diagram of 8251 D2 D3 RxD D4 D5 D6 D7 TxC WR CS C/D RD RxRdy
D1 D0 RxC DTR RTS DSR Reset CLK TxD TxEmpty CTS Sync/BD TxRdy
PIN diagram of 8251 D2 D3 RxD Gnd D4 D5 D6 D7 TxC WR CS C/D RD RxRdy
D1 D0 Vcc RxC DTR RTS DSR Reset CLK TxD TxEmpty CTS Sync/BD TxRdy
Functional block diagram of 8251
Functional block diagram of 8251 Clk : This input is used to generate internal device timings. The frequency must be greater than 30 times the Receiver and Transmitter data bit rates.
Functional block diagram of 8251 Clk : This input is used to generate internal device timings. The frequency must be greater than 30 times the Receiver and Transmitter data bit rates. WR : A ‘low’ on this input informs the device that the CPU wants to write data / command word.
Functional block diagram of 8251 Clk : This input is used to generate internal device timings. The frequency must be greater than 30 times the Receiver and Transmitter data bit rates. WR : A ‘low’ on this input informs the device that the CPU wants to write data / command word. RD : A ‘low’ on this input informs the device that the CPU wants to read data / status word.
Functional block diagram of 8251 Clk : This input is used to generate internal device timings. The frequency must be greater than 30 times the Receiver and Transmitter data bit rates. WR : A ‘low’ on this input informs the device that the CPU wants to write data / command word. RD : A ‘low’ on this input informs the device that the CPU wants to read data / status word. C/D : This input with the WR and RD inputs, inform the device that the word on the data bus is either a data / control word / status information.
Functional block diagram of 8251 CS : A ‘low’ on this input selects the 8251. No reading / writing will occur unless the device is selected. A ‘high’ on this input the data bus is in tri-state / high impedance state.
Functional block diagram of 8251 CS : A ‘low’ on this input selects the 8251. No reading / writing will occur unless the device is selected. A ‘high’ on this input the data bus is in tri-state / high impedance state. DBB : This tri-state bi-directional, 8 bit buffer is used to interface 8251 to the system bus. Data is transferred / received upon execution of IN and OUT instruction.
Functional block diagram of 8251 CS : A ‘low’ on this input selects the 8251. No reading / writing will occur unless the device is selected. A ‘high’ on this input the data bus is in tri-state / high impedance state. DBB : This tri-state bi-directional, 8 bit buffer is used to interface 8251 to the system bus. Data is transferred / received upon execution of IN and OUT instruction. Reset : A ‘high’ on this input pin forces 8251 into an idle mode. This device will remain in idle mode until a new set of control words is written into the 8251.
Sections of 8251 • Data Bus buffer.
• Read / Write control logic. • Modem control. • Transmitter. • Receiver.
Data Bus buffer section of 8251 • It interfaces the internal bus of 8051 with data bus of the processor. • 8 bit data bus is used to read / Write the Command or Data or Status from or to the processor and 8251.
Read / Write control logic of 8251 WR : A ‘low’ on this input informs the device that the CPU wants to write data / command word.
RD : A ‘low’ on this input informs the device that the CPU wants to read data / status word.
Read / Write control logic of 8251 WR : A ‘low’ on this input informs the device that the CPU wants to write data / command word.
RD : A ‘low’ on this input informs the device that the CPU wants to read data / status word. C/D : Control / Data This input with the WR and RD inputs, inform the device that the word on the data bus is either a data / control word / status information. CS : A ‘low’ on this input selects the 8251. A ‘high’ on this input the data bus is in tri-state / high impedance state.
Read / Write control logic of 8251 WR : A ‘low’ on this input informs the device that the CPU wants to write data / command word.
RD : A ‘low’ on this input informs the device that the CPU wants to read data / status word. C/D : Control / Data This input with the WR and RD inputs, inform the device that the word on the data bus is either a data / control word / status information. CS : A ‘low’ on this input selects the 8251. A ‘high’ on this input the data bus is in tri-state / high impedance state. Reset : A ‘high’ on this input pin forces 8251 into an idle mode. Clock : This input is used to generate internal device timings.
Modem control logic of 8251 DSR : Data Set Ready This input signal is a general purpose. One bit inverting input ports. Its condition can be tested by the CPU using a status read operation. This input is used to test modem condition such as data set ready.
Modem control logic of 8251 DSR : Data Set Ready This input signal is a general purpose. One bit inverting input ports. Its condition can be tested by the CPU using a status read operation. This input is used to test modem condition such as data set ready. DTR : Data Terminal Ready This output signal is a general purpose. One bit inverting output ports. It can be set ‘low’ by programming appropriate bit in the command instruction. This output is used to test modem condition such as data terminal ready.
Modem control logic of 8251 DSR : Data Set Ready This input signal is a general purpose. One bit inverting input ports. Its condition can be tested by the CPU using a status read operation. This input is used to test modem condition such as data set ready. DTR : Data Terminal Ready This output signal is a general purpose. One bit inverting output ports. It can be set ‘low’ by programming appropriate bit in the command instruction. This output is used to test modem condition such as data terminal ready.
RTS : Request to Send This output signal is a general purpose. One bit inverting output ports. It can be set ‘low’ by programming appropriate bit in the command instruction. This output is used to test modem condition such as Request To Send.
Modem control logic of 8251 DSR : Data Set Ready This input signal is a general purpose. One bit inverting input ports. Its condition can be tested by the CPU using a status read operation. This input is used to test modem condition such as data set ready. DTR : Data Terminal Ready This output signal is a general purpose. One bit inverting output ports. It can be set ‘low’ by programming appropriate bit in the command instruction. This output is used to test modem condition such as data terminal ready.
RTS : Request to Send This output signal is a general purpose. One bit inverting output ports. It can be set ‘low’ by programming appropriate bit in the command instruction. This output is used to test modem condition such as Request To Send. CTS : Clear To Send A ‘low’ on this input enables the 8251 to transmit serial data if the TX enable bit in the command byte is set to one.
Transmitter control logic of 8251 Transmitter buffer : It accepts parallel data and converts to a serial bit stream, inserts the appropriate bits and outputs a composite serial stream of data on the TxD output pin on the falling edge of TxC.
Transmitter control logic of 8251 Transmitter buffer : It accepts parallel data and converts to a serial bit stream, inserts the appropriate bits and outputs a composite serial stream of data on the TxD output pin on the falling edge of TxC. TxRdy : Transmitter Ready This output signals the CPU that the transmitter is ready to accept a data. This output pin can be used as an interrupt to the system. This is automatically reset by the leading edge of WR, when data is loaded from the CPU.
Transmitter control logic of 8251 Transmitter buffer : It accepts parallel data and converts to a serial bit stream, inserts the appropriate bits and outputs a composite serial stream of data on the TxD output pin on the falling edge of TxC. TxRdy : Transmitter Ready This output signals the CPU that the transmitter is ready to accept a data. This output pin can be used as an interrupt to the system. This is automatically reset by the leading edge of WR, when data is loaded from the CPU. TxE : Transmitter is Empty When the 8251 has no data to send, this output will go ‘high’. It can be used to indicate the end of transmission mode.
Transmitter control logic of 8251 Transmitter buffer : It accepts parallel data and converts to a serial bit stream, inserts the appropriate bits and outputs a composite serial stream of data on the TxD output pin on the falling edge of TxC. TxRdy : Transmitter Ready This output signals the CPU that the transmitter is ready to accept a data. This output pin can be used as an interrupt to the system. This is automatically reset by the leading edge of WR, when data is loaded from the CPU. TxE : Transmitter is Empty When the 8251 has no data to send, this output will go ‘high’. It can be used to indicate the end of transmission mode. TxC : Transmitter Clock It controls the rate at which the data is to be transmitted. In synchronous mode, baud rate is equal to the TxC frequency. In Asynchronous mode, the baud rate is a fraction of the actual TxC frequency.
Receiver control logic of 8251 Receiver buffer : It accepts serial data and converts this input to a parallel format. Checks for bits that are unique for the communication and sends an assembled character to the CPU. Serial data is input to RxD pin and is clocked in the rising edge of RxC.
Receiver control logic of 8251 Receiver buffer : It accepts serial data and converts this input to a parallel format. Checks for bits that are unique for the communication and sends an assembled character to the CPU. Serial data is input to RxD pin and is clocked in the rising edge of RxC. RxRdy : Receiver Ready This output indicates that 8251 contains a character that is ready to be input to the CPU. This pin can be connected to the interrupt structure of the CPU, or for polled operation. The CPU can check the condition using a status read operation.
Receiver control logic of 8251 Receiver buffer : It accepts serial data and converts this input to a parallel format. Checks for bits that are unique for the communication and sends an assembled character to the CPU. Serial data is input to RxD pin and is clocked in the rising edge of RxC. RxRdy : Receiver Ready This output indicates that 8251 contains a character that is ready to be input to the CPU. This pin can be connected to the interrupt structure of the CPU, or for polled operation. The CPU can check the condition using a status read operation. RxC : Receiver Clock It controls the rate at which the data is to be received. In synchronous mode, baud rate is equal to the TxC frequency. In Asynchronous mode, the baud rate is a fraction of the actual TxC frequency.
Registers available in 8251 Mode Instruction Register (MIR) It supports both synchronous and asynchronous operation. Bit 0 & 1 of this register are the baud rate factors and determines the factor between the data rate and the clock. B0 & B1 : 0 0 for synchronous operation, otherwise it is asynchronous operation Command Instruction Register (CIR) The command instruction register controls the Transmitter / Receiver operation. D0 - Transmitter enable D1 - Data terminal ready D2 - Receiver enable D3 - Send break character D4 - Error reset D5 - Request to send D6 - Internal reset D7 - Enter hunt
Registers available in 8251 Status Register It allows the microprocessor / controller to examine the condition of the 8251 device D0 - Transmitter ready D1 - Receiver ready D2 - Transmitter empty D3 - Parity error D4 - Overrun error D5 - Framing error D6 - Sync / break detect D7 - Data set ready Sync Character one Register This register holds the first sync character. The information is used by the receiver for sync comparison and by the transmitter for sync character transmission.
Registers available in 8251 Sync Character two Register This register holds the second sync character. The information is used by the receiver for sync comparison and by the transmitter for sync character transmission. Transmitter Buffer Register It holds the transmitter data which 8251 formats, serializes and transmits on the TxD output. Once the existing data bits in the shift register are completely transmitted, the TBR transfers new data into shift register. Receive Buffer Register This register holds the data received from the shift register. After the shift register receives a new data, it is ready to transfer the new data to the RBR. If the existing data has already been read by the processor, then the transfer takes place. If the existing data has not been read, the overrun error bit is set.
Status word of 8251
Mode word of 8251
7
6
Number of Stop bits 00: 01: 10: 11:
invalid 1 bit 1.5 bits 2 bits
5
4
3
2
0
Mode register
Baud Rate
Parity enable 0: disable 1: enable Character length
Parity 0: odd 1: even
1
00: 01: 10: 11:
5 bits 6 bits 7 bits 8 bits
00: 01: 10: 11:
Syn. Mode x1 clock x16 clock x64 clock
Command word of 8251
EH
IR
RTS
ER
SBRK
RxE
TxE: transmit enable DTR: data terminal ready RxE: receiver enable SBPRK: send break character ER: error reset RTS: request to send IR: internal reset EH: enter hunt mode
DTR
TxE
8251 Interface with 8085
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