8253 Programmable Interval Timer
R. Theagarajan, ME., MSc., PhD Rtd. Professor in Engineering email: rtheagarajan@yahoo.com rtrajan59@gmail.com
Purpose of 8253
Description of 8253 • The Intel 8253 is a programmable Timer / Counter chip designed for use with Intel microprocessor as peripheral device.
Description of 8253 • The Intel 8253 is a programmable Timer / Counter chip designed for use with Intel microprocessor as peripheral device. • It is packaged in a 24-pin Plastic encapsulation, Dual In-Line Package.
Description of 8253 • The Intel 8253 is a programmable Timer / Counter chip designed for use with Intel microprocessor as peripheral device. • It is packaged in a 24-pin Plastic encapsulation, Dual In-Line Package. • It has 3 independent counters : 0, 1, 2 • Counters are 16 bit.
Description of 8253 • The Intel 8253 is a programmable Timer / Counter chip designed for use with Intel microprocessor as peripheral device. • It is packaged in a 24-pin Plastic encapsulation, Dual In-Line Package. • It has 3 independent counters : 0, 1, 2 • Counters are 16 bit. • Six programmable timer modes allow the 8253 to be used as an event counter, elapsed time indicator, programmable one-shot, and in many applications.
Description of 8253 • The Intel 8253 is a programmable Timer / Counter chip designed for use with Intel microprocessor as peripheral device. • It is packaged in a 24-pin Plastic encapsulation, Dual In-Line Package. • It has 3 independent counters : 0, 1, 2 • Counters are 16 bit. • Six programmable timer modes allow the 8253 to be used as an event counter, elapsed time indicator, programmable one-shot, and in many applications. • It can work from DC to 2.6 MHz.
PIN diagram of 8253
PIN diagram of 8253 RD WR CS A0, A1
: read signal (active Low) : write signal (active Low) : chip select signal (active Low) : address lines
PIN diagram of 8253 RD WR CS A0, A1
: read signal (active Low) : write signal (active Low) : chip select signal (active Low) : address lines
Data Bus buffer contains the logic to buffer the data between the microprocessor and the internal registers. It has 8 input pins, usually labelled as D7‌..D0, where D7 is the MSB.
PIN diagram of 8253 RD WR CS A0, A1
: read signal (active Low) : write signal (active Low) : chip select signal (active Low) : address lines
Data Bus buffer contains the logic to buffer the data between the microprocessor and the internal registers. It has 8 input pins, usually labelled as D7‌..D0, where D7 is the MSB. CLK Gate OUT
: Clock Input : Gate input control : Counter / Timer output
Functional block diagram of 8253
Functional block diagram of 8253 Each counter has two input pins – "CLK" (clock input) and "GATE" – and one output pin, for data output. The three counters are 16-bit down counters independent of each other
Functional block diagram of 8253 Each counter has two input pins – "CLK" (clock input) and "GATE" – and one output pin, for data output. The three counters are 16-bit down counters independent of each other
The control word register contains the programmed information which will be sent by the microprocessor to the device. It defines how each channel of the PIT logically works. Each access to these ports takes about 1 µs.
Writing the control word into CWR
To initialize the counters, the microprocessor must write a control word, in CWR register.
Writing the control word into CWR
To initialize the counters, the microprocessor must write a control word, in CWR register. This can be done by setting proper values for the pins of the Read/Write Logic block and then by sending the control word to the Data Bus Buffer block.
Writing the control word into CWR
To initialize the counters, the microprocessor must write a control word, in CWR register. This can be done by setting proper values for the pins of the Read/Write Logic block and then by sending the control word to the Data Bus Buffer block. The CWR can only be written into, No read operation is permitted.
Control word format
The control word register contains 8 bits, labeled D7‌.D0 (D7 is the MSB). Most values set the parameters for one of the three counters: The most significant two bits select the counter register the command applies to. The next two bits select the format that will be used for subsequent read/write access to the counter register. This is commonly set to a mode where accesses alternate between the least-significant and most-significant bytes. The next three bits select the mode that the counter will operate in. The least significant bit selects whether the counter will operate in binary or BCD.
Control word format
Control word format
Control word format
Control word format
Modes of operation
• There are 6 modes of operation of 8253
Modes of operation
• There are 6 modes of operation of 8253 • Differences in modes are : “OUT” signal in different shapes like low-high or high-low, periodic or nonperiodic – How to trigger/start the counter
Modes of operation
• There are 6 modes of operation of 8253 • Differences in modes are : “OUT” signal in different shapes like low-high or high-low, periodic or nonperiodic – How to trigger/start the counter
• Mode 0 and 1 are same in shape (non-periodic)
Modes of operation
• There are 6 modes of operation of 8253 • Differences in modes are : “OUT” signal in different shapes like low-high or high-low, periodic or nonperiodic – How to trigger/start the counter
• Mode 0 and 1 are same in shape (non-periodic) • Mode 4 and 5 are same in shape (non-periodic)
Modes of operation
• There are 6 modes of operation of 8253 • Differences in modes are : “OUT” signal in different shapes like low-high or high-low, periodic or nonperiodic – How to trigger/start the counter
• Mode 0 and 1 are same in shape (non-periodic) • Mode 4 and 5 are same in shape (non-periodic) • Mode 2 and 3 are almost same in shape (periodic)
Mode of operation
Mode of operation
Mode of operation
Mode of operation
Mode of operation
Read counter - operation
Simple Read
Reading while counting
Mode Register for latching the count
Control Logic
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