8051 Micro-controller
R. Theagarajan. ME., MSc., PhD Rtd. Professor in Engineering email: rtheagarajan@yahoo.com rtrajan59@gmail.com
Microcontroller Intel 8051 family 8031 – External ROM 8051 – Built-in ROM 8751 – EPROM 4k Programmable Memory 8951 – Flash ROM 128 location Data Memory Instruction cycle : 1 micro-sec with 12MHz crystal
8051 family
HMOS technology Single Power supply –5v Data memory – 128 bytes Programmable memory – 4096 bytes Software Flag – 128 user Addressable – 64 K byte Bi-directional I/O lines – 32 High speed Serial I / O
8051 family
Timer / Counter – Two Level prioritized Interrupt – Two Bit addressable locations Upward compatible ASCII code for data Unique 7 bit binary number 128 characters MSB is often zero for all characters Sometime D7 bit used for parity
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8 0
5 1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P0.0 (AD0) P0.0 P0.1 (AD1) P0.1 P0.2 P0.2 (AD2) P0.3 P0.3 (AD3) P0.4 (AD4) P0.4 P0.5 P0.5 (AD5) P0.6 P0.6 (AD6) P0.7 P0.7 (AD7)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8 0
5 1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P0.0 (AD0) P0.0 P0.1 (AD1) P0.1 P0.2 P0.2 (AD2) P0.3 P0.3 (AD3) P0.4 (AD4) P0.4 P0.5 P0.5 (AD5) P0.6 P0.6 (AD6) P0.7 P0.7 (AD7)
P2.7 (A15) P2.7 P2.6 (A14) P2.6 P2.5 P2.5 (A13) P2.4 P2.4 (A12) P2.3 (A11) P2.3 P2.2 P2.2 (A10) P2.1 P2.1 (A9) P2.0 P2.0 (A8)
(RxD) P3.0 (TxD) P3.1 P3.1 (INT0) P3.2 P3.2 (INT1) P3.3 P3.3 (T0) P3.4 P3.4 (T1) P3.5 P3.5 (WR) P3.6 P3.6 P3.7 (RD) P3.7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8 0
5 1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P0.0 (AD0) P0.0 P0.1 (AD1) P0.1 P0.2 P0.2 (AD2) P0.3 P0.3 (AD3) P0.4 (AD4) P0.4 P0.5 P0.5 (AD5) P0.6 P0.6 (AD6) P0.7 P0.7 (AD7)
P2.7 (A15) P2.7 P2.6 (A14) P2.6 P2.5 P2.5 (A13) P2.4 P2.4 (A12) P2.3 (A11) P2.3 P2.2 P2.2 (A10) P2.1 P2.1 (A9) P2.0 P2.0 (A8)
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 (RxD) P3.0 (TxD) P3.1 P3.1 (INT0) P3.2 P3.2 (INT1) P3.3 P3.3 (T0) P3.4 P3.4 (T1) P3.5 P3.5 (WR) P3.6 P3.6 P3.7 (RD) P3.7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8 0
5 1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P0.0 (AD0) P0.0 P0.1 (AD1) P0.1 P0.2 P0.2 (AD2) P0.3 P0.3 (AD3) P0.4 (AD4) P0.4 P0.5 P0.5 (AD5) P0.6 P0.6 (AD6) P0.7 P0.7 (AD7)
P2.7 (A15) P2.7 P2.6 (A14) P2.6 P2.5 P2.5 (A13) P2.4 P2.4 (A12) P2.3 (A11) P2.3 P2.2 P2.2 (A10) P2.1 P2.1 (A9) P2.0 P2.0 (A8)
P1.0 P1.0 P1.1 P1.1 P1.2 P1.2 P1.3 P1.3 P1.4 P1.4 P1.5 P1.5 P1.6 P1.6 P1.7 P1.7 (RxD) P3.0 (TxD) P3.1 P3.1 (INT0) P3.2 P3.2 (INT1) P3.3 P3.3 (T0) P3.4 P3.4 (T1) P3.5 P3.5 (WR) P3.6 P3.6 P3.7 (RD) P3.7
GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8 0
5 1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Vcc
P0.0 (AD0) P0.0 P0.1 (AD1) P0.1 P0.2 P0.2 (AD2) P0.3 P0.3 (AD3) P0.4 (AD4) P0.4 P0.5 P0.5 (AD5) P0.6 P0.6 (AD6) P0.7 P0.7 (AD7)
P2.7 (A15) P2.7 P2.6 (A14) P2.6 P2.5 P2.5 (A13) P2.4 P2.4 (A12) P2.3 (A11) P2.3 P2.2 P2.2 (A10) P2.1 P2.1 (A9) P2.0 P2.0 (A8)
P1.0 P1.0 P1.1 P1.1 P1.2 P1.2 P1.3 P1.3 P1.4 P1.4 P1.5 P1.5 P1.6 P1.6 P1.7 P1.7 (RxD) P3.0 (TxD) P3.1 P3.1 (INT0) P3.2 P3.2 (INT1) P3.3 P3.3 (T0) P3.4 P3.4 (T1) P3.5 P3.5 (WR) P3.6 P3.6 P3.7 (RD) P3.7 XTAL2 XTAL1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8 0
5 1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Vcc
P0.0 (AD0) P0.0 P0.1 (AD1) P0.1 P0.2 P0.2 (AD2) P0.3 P0.3 (AD3) P0.4 (AD4) P0.4 P0.5 P0.5 (AD5) P0.6 P0.6 (AD6) P0.7 P0.7 (AD7)
P2.7 (A15) P2.7 P2.6 (A14) P2.6 P2.5 P2.5 (A13) P2.4 P2.4 (A12) P2.3 (A11) P2.3 P2.2 P2.2 (A10) P2.1 P2.1 (A9) P2.0 P2.0 (A8)
P1.0 P1.0 P1.1 P1.1 P1.2 P1.2 P1.3 P1.3 P1.4 P1.4 P1.5 P1.5 P1.6 P1.6 P1.7 P1.7 RST
(RxD) P3.0 (TxD) P3.1 P3.1 (INT0) P3.2 P3.2 (INT1) P3.3 P3.3 (T0) P3.4 P3.4 (T1) P3.5 P3.5 (WR) P3.6 P3.6 P3.7 (RD) P3.7 XTAL2 XTAL1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8 0
5 1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Vcc
P0.0 (AD0) P0.0 P0.1 (AD1) P0.1 P0.2 P0.2 (AD2) P0.3 P0.3 (AD3) P0.4 (AD4) P0.4 P0.5 P0.5 (AD5) P0.6 P0.6 (AD6) P0.7 P0.7 (AD7)
P2.7 (A15) P2.7 P2.6 (A14) P2.6 P2.5 P2.5 (A13) P2.4 P2.4 (A12) P2.3 (A11) P2.3 P2.2 P2.2 (A10) P2.1 P2.1 (A9) P2.0 P2.0 (A8)
P1.0 P1.0 P1.1 P1.1 P1.2 P1.2 P1.3 P1.3 P1.4 P1.4 P1.5 P1.5 P1.6 P1.6 P1.7 P1.7 RST
(RxD) P3.0 (TxD) P3.1 P3.1 (INT0) P3.2 P3.2 (INT1) P3.3 P3.3 (T0) P3.4 P3.4 (T1) P3.5 P3.5 (WR) P3.6 P3.6 P3.7 (RD) P3.7 XTAL2 XTAL1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8 0
5 1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Vcc
P0.0 (AD0) P0.0 P0.1 (AD1) P0.1 P0.2 P0.2 (AD2) P0.3 P0.3 (AD3) P0.4 (AD4) P0.4 P0.5 P0.5 (AD5) P0.6 P0.6 (AD6) P0.7 P0.7 (AD7) ALE
P2.7 (A15) P2.7 P2.6 (A14) P2.6 P2.5 P2.5 (A13) P2.4 P2.4 (A12) P2.3 (A11) P2.3 P2.2 P2.2 (A10) P2.1 P2.1 (A9) P2.0 P2.0 (A8)
P1.0 P1.0 P1.1 P1.1 P1.2 P1.2 P1.3 P1.3 P1.4 P1.4 P1.5 P1.5 P1.6 P1.6 P1.7 P1.7 RST
(RxD) P3.0 (TxD) P3.1 P3.1 (INT0) P3.2 P3.2 (INT1) P3.3 P3.3 (T0) P3.4 P3.4 (T1) P3.5 P3.5 (WR) P3.6 P3.6 P3.7 (RD) P3.7 XTAL2 XTAL1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8 0
5 1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Vcc
P0.0 (AD0) P0.0 P0.1 (AD1) P0.1 P0.2 P0.2 (AD2) P0.3 P0.3 (AD3) P0.4 (AD4) P0.4 P0.5 P0.5 (AD5) P0.6 P0.6 (AD6) P0.7 P0.7 (AD7) EA ALE
P2.7 (A15) P2.7 P2.6 (A14) P2.6 P2.5 P2.5 (A13) P2.4 P2.4 (A12) P2.3 (A11) P2.3 P2.2 P2.2 (A10) P2.1 P2.1 (A9) P2.0 P2.0 (A8)
P1.0 P1.0 P1.1 P1.1 P1.2 P1.2 P1.3 P1.3 P1.4 P1.4 P1.5 P1.5 P1.6 P1.6 P1.7 P1.7 RST
(RxD) P3.0 (TxD) P3.1 P3.1 (INT0) P3.2 P3.2 (INT1) P3.3 P3.3 (T0) P3.4 P3.4 (T1) P3.5 P3.5 (WR) P3.6 P3.6 P3.7 (RD) P3.7 XTAL2 XTAL1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
8 0
5 1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Vcc
P0.0 (AD0) P0.0 P0.1 (AD1) P0.1 P0.2 P0.2 (AD2) P0.3 P0.3 (AD3) P0.4 (AD4) P0.4 P0.5 P0.5 (AD5) P0.6 P0.6 (AD6) P0.7 P0.7 (AD7) EA ALE PSEN
P2.7 (A15) P2.7 P2.6 (A14) P2.6 P2.5 P2.5 (A13) P2.4 P2.4 (A12) P2.3 (A11) P2.3 P2.2 P2.2 (A10) P2.1 P2.1 (A9) P2.0 P2.0 (A8)
8051 Pin details
Crystal Crystal
18 19
RST RST
9
EA EA
31
PSEN
29
ALE Ground
39 - 32
Port 0 AD0 – AD7
30 20
21 - 28 1-8
10 - 17
Port 2 A8 – A15
Port 1 User Port 3 Control
MEMORY MAP Program Memory FFFF
Data Memory FFFF
FF SFR External
80 7F
Data RAM
External
00
1000 0FFF
0000
INT.
EXT.
EA = 1
EA = 0 0000
Internal Memory
Internal Memory
Internal Memory
Internal Memory
Functional block diagram
Special Function Registers F8 F0
FF B
F7
E8 E0
EF Acc
E7
D8 D0
DF PSW
D7
C8
CF
C0
C7
B8
IP
BF
B0
P3
B7
A8
IE
AF
A0
P2
A7
98
Scon
90
P1
88
Tcon
Tmod
80
P0
SP
Sbuf
9F TL0
TL1
DPL
DPM
TH0
TH1
97 8F Pcon
87
FLAG Register
D7
D6
D5
D4
D3
D2
D1
Carry
D0
Parity
Au. Carry
User Flag 0
User Flag1 0 0 1 1
0 1 0 1
Bank 0 Bank 1 Bank 2 Bank 3
Over Flow
Stack Pointer
SP is an 8 bit register May reside anywhere in on-chip RAM Normally initialized with 07H Actual location starts from 08H SP is incremented for Push, Call SP is decremented for Pop
Data Pointer
Data Pointer - DPTR Manipulated as one 16 bit register Manipulated as two 8 bit registers To hold 16 bit address Normally used to access data memory DPH, DPL
I / O Port
Port 0 – can sink 8 TTL inputs Port 3 – can drive 4 TTL inputs Port 0 – open drain output Port 1, 2, 3 – have internal pull-ups On Reset, ports are written with 1
Clock Crystal, connected between pins 18 & 19 Crystal generator provides internal clocking signal Internal clocking is half the OSC frequency Each machine cycle contain 6 states User cannot access internal clocks
Address Latch Enable
Address Latch Enable (ALE) Activated twice during each machine cycle Most instructions are executed in one cycle MUL & DIV - needs more than 2 cycles It is used to latch the valid address externally
PSEN signal Used for external fetches from Program Memory It takes 6 oscillator periods EA pin must be connected to ground PC contains value larger than 0FFF
Boolean Processor It is an integrated bit processor It has own Instruction set Accumulator Carry flag Bit addressable RAM I/O
Power Down Mode
By instruction Oscillator is stopped Content of RAM & SFR is held Exit only by Reset
Vcc can be reduced Vcc must be restored before Reset
CONTROL Register
These registers contain control / status information TMOD – Timer / counter mode register TCON - Timer / counter control register SCON – Serial control register IE – Interrupt enable register IP – Interrupt priority control register PCON – Power control register
TIMER Register
Two timers in 8051 family Three timers in 8052 family Sixteen bit Timer / Counter – T0, T1 Eight bit register – TH0, TL0, TH1, TL1 Used auto-reload TH0 TL0 TH1 TL1
Timer
Timer 0, Timer 1 Mode 0 8 bit counter Divide by 32 pre-scalar 13 bit register Mode 1 – sixteen bits timer Mode 2 – 8 bit counter with auto-reload Mode 3 – Timer 1 To hold the count value Two separate counter
Tmode Register Timer - 1 D7
D6
D5
Timer - 0 D4
D3
D2
D1
D0
Gate C/T
M1 D6 = 1 for Counter = 0 for Timer
M0
0
0 MCS-48
0
1 16 bit
1
0
1
1 Timer 0
8 bit, auto reload
Tcon Register Timer 0
Timer 1
D7
TF1
D6
D5
TR 1
TF 0
1 - ON
D4
D3
TR 0 IE1
D2
D1
D0
IT 1
IE 0
IT 0
by SW
0 - Off Overflow
- Set
by HW
Cleared – vectors to Int. routine
Set by HW when External Int. detected Level triggered Edge triggered
Serial Data Buffer
Referred as SBUF – 99h Contains two registers Transmit Buffer Receive Buffer
Serial Port 4 modes Mode 0 – Data enters and exists through RxD TxD outputs shift clock 8 bits, Baud rate 1/12 Frequency
Mode 1 – 10 bits (data+ start, stop bit) Data exists through TxD Data received through RxD Variable baud rate
Mode 2 – 11 bits (data+ start, stop bit, parity bit) Data exists through TxD Data received through RxD Baud rate is programmable
Mode 3 – Similar to mode 2, Baud variable
Scon Register
D7
SM0
D6
D5
SM 1 SM2
D4
D3
REN TB8
D2
RB8
D1
TI
D0
RI
Multi-processor Comm. features 0 0 - mode 0 - fosc / 12
Mode 2 / 3 9 bit
0 1 - mode 1 - 8 bit UART – variable baud 1 0 - mode 2 - 9 bit UART – fosc / 32 or fosc / 64 1 1 - mode 3 - 9 bit UART - variable
Receive Int. flag set – HW Cleared - SW
Interrupt Enable Register D7
D6
D5
D4
D3
D2
D1
D0
EA
X
ET2
ES
ET1
EX1
ET0
EX0
0 – disables all the interrupts 1 – enables
Serial Port Int. 0 – disables 1 – enables Timer 1 overflow Int. 0 – disables 1 – enables
Timer 2 0 – disables 1 – enables
External Interrupt 0 0 – disables 1 – enables
Interrupt Priority Register D7
D6
D5
D4
D3
D2
D1
D0
X
X
PT2
PS
PT1
PX1
PT0
PX0
Serial Port Int. 1 – Higher priority
Timer 1 1 – Higher priority
IE0
– highest
- 0003
TF0
–
- 000B
IE1
–
- 0013
TF1
-
- 001B
RI + TI
-
- 0023
TF2 + ExF2
- lowest
- 002B
Addressing Modes
5 modes Register – R0-R7, Acc, B, DPTR, Cy Direct – RAM, Special Function Reg. Register Indirect - @R0, @R1, SP Immediate Base register + Index register @DPTR + Acc @PC + Acc
Instruction Set 5 groups
Data Transfer group Arithmetic operation group Logical operation group Boolean variable manipulation Program & Machine control
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