ARM - LPC2148 Architecture
R. Theagarajan. ME., MSc., PhD Rtd. Professor in Engineering email: rtheagarajan@yahoo.com rtrajan59@gmail.com
• Advanced RISC Microcontroller. • Pipeline techniques, so that processing, memory and other blocks can operate continuously. While executing an instruction its successor is being decoded and a third instruction is being fetched. • It employs unique architecture known as THUMB, suitable for high volume application with memory restrictions. • Idea behind THUMB is, super reduced instruction set * Standard 32 bit ARM instruction * 16 bit THUMB instruction set.
ARM controller History
ARM family comparison
Pipeline depth
ARM7
ARM9
ARM10
ARM11
3 stage
5 stage
6 stage
8 stage
Typical MHz
80
150
260
335
mW / MHz
0.06
0.19
0.5
0.4
MIPS / MHz
0.97
1.1
1.3
1.2
Architecture
VonNeumann
Harvard
Harvard
Harvard
Multiplier
8 x 32
8 x 32
16 x 32
16 x 32
ARM family comparison Processor family
# of pipeline stages
Memory organization
Clock Rate
MIPS / MHz
ARM6
3
Von Neumann
25 MHz
ARM7
3
Von Neumann
66 MHz
0.9
ARM8
5
Von Neumann
72 MHz
1.2
ARM9
5
Harvard
200 MHz
1.1
ARM10
6
Harvard
400 MHz
1.25
StrongARM
5
Harvard
233 MHz
1.15
ARM11
8
Von Neumann/ Harvard
550 MHz
1.2
Nomenclature -
ARM x, y, z, T, D, M, I, E, J, F, S
X - Family. Y - Memory management / protection unit.
Z - Cache. T - Thumb 16 bit decoder. D - JTAG debug. M - Fast multiplier. I - Embedded ICE macrocell. E - Enhanced instructions. J - Jazelle. F - Vector floating-point unit
S - Synthesizible version.
ARM ARM processor has three instruction sets – ARM, Thumb and Jazelle. Register file contains 37 registers, but 17 or 18 are accessible at any point of time, rest are banked according to processor mode. Current processor mode is stored in the CPSR. It holds the current status of processor core, Interrupt masks, condition flags and state. State determines which instruction set is being executed. ARM processor consists Core + surrounding components which interface it with a bus. Cache - to improve overall system performance TCM - to improve real time response Memory management to protect system resource Coprocessors – to extend the instruction set.
Key Features of LPC2148 • 32-bit ARM7 microcontroller in a tiny LQFP64 package. • 32 kB of on-chip static RAM and 512 kB of on-chip flash memory. 128-bit wide interface / accelerator enables high-speed 60 MHz operation. • In-System Programming / In-Application Programming via on-chip boot loader software. • Full chip erase in 400 ms and programming of 256 bytes in 1 ms. • Embedded ICE and Embedded Trace interfaces offer real-time debugging with the on-chip RealMonitor software and high-speed tracing of instruction execution. • USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM. In addition, it provides 8 kB of on-chip RAM accessible to USB by DMA.
Key Features of LPC2148 • Two 10-bit ADCs provide a total of 14 analog inputs, with conversion times as low as 2.44 μs per channel. • Single 10-bit DAC provides variable analog output. • Two 32-bit Timers / external event Counters (with four capture and compare channels), PWM unit (six outputs) and watchdog. • Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input. • Multiple serial interfaces including two UARTs, Two Fast I2C-bus (400 kbit/s), Serial Peripheral Interface and Synchronous Serial Port with buffering and variable data length capabilities. • Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.
Key Features of LPC2148 • 5v tolerant fast general purpose I/O pins. • Up to 21 external Interrupt pins are available.
• 60 MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100 μs. • On-chip integrated oscillator operates with external crystal upto 25 MHz.
• Power saving modes include Idle and Power-down. • Individual enable / disable of peripheral functions as well as peripheral clock scaling for additional power optimization.
• Processor wake-up from Power-down mode via external interrupt or BOD. • Single power supply chip with POR and BOD circuits: CPU operating voltage range of 3.0v to 3.6v with 5v tolerant I/O pads.
Pin diagram of LPC2148 -
LPC2148
Basic block Diagram -
Functional block Diagram -
Block Diagram -
VLSI Peripheral Bus VP Bus
Block Diagram -
Advanced High Performance Bus AHP Bus
Block Diagram -
Bridge AHP to VP bus
Memory map of LPC2148 -
Memory map of LPC2148 -
0007 FFFF
512 KB Non-Volatile memory 0000 0000
Memory map of LPC2148 -
Reserved 4000 0000 Address space 0008 0000
Memory map of LPC2148 -
4000 8000 4000 0000
32 KB RAM
Memory map of LPC2148 -
Reserved 7FD0 0000 Address space 4000 8000
Memory map of LPC2148 -
7FD0 2000 7FD0 0000
8KB DMA RAM
Memory map of LPC2148 -
Reserved 7FFF D000 Address space 7FD0 2000
Memory map of LPC2148 8000 0000 7FFF D000
Boot Block
Memory map of LPC2148 Reserved E000 0000 Address space 8000 0000
Memory map of LPC2148 F000 0000 E000 0000
VPB addresses
Memory map of LPC2148 FFFF FFFF F000 0000
AHB addresses
Registers of ARM -
Current Program Status Register
Pin connect Block Pin connect block allows selected pins of the microcontroller to have more than one function.
Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Pin control module with its pin select registers defines the functionality of the microcontroller in a given hardware environment. After reset all the pins of port are configured as input. If debug is enabled, the JTAG pins will assume their JTAG functionality If trace is enabled, the trace pins will assume their Trace functionality
The pins associated with the I2C interface are open drain.
Fast General Purpose I/O Pins that are not connected to a specific peripheral function are controlled by the GPIO registers.
Pin may be dynamically configured as In or Out. All GPIO registers are byte addressable. Entire port value can be written in one instruction. Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. Directional control of individual bits. Separate control of output set and clear. All I/O lines are defined as input after Reset.
Timers / Counters External event Counter or Timer operation. It is 32 bit with a programmable 32 bit prescaler.
Four 32 bit capture channels can take a snapshot of the timer value when an input signal transitions. Capture event may also generate an interrupt. Four 32 bit match registers allow Continuous operation with interrupt on match Stop timer on match with interrupt generation Reset timer on match. Four external outputs per timer/counter with set Low on match set High on match Toggle on match do nothing on match.
ADC features It contains two analog to digital converters. ADC0 has six channels & ADC1 has eight channels. Measurement range of 0 to Vref. Each converter can perform more than 4,00,000 samples per second. Each analog input has a dedicated result register to reduce interrupt overhead. Burst conversion mode for single or multiple inputs. Optional conversion on transition of input pin or timer match signal. Global start command for both converters.
DAC features It enables to generate a variable analog output. Maximum DAC output voltage is the Vref. Buffered output. Ten bit DAC. Power down mode available. Selectable speed.
Pulse Width Modulator It is based on the standard timer block. Designed to count cycles of the peripheral clock (PCLK). Ability to control rising and falling edge allows the PWM to be used for more applications. Seven match registers, with single edge or double edge controlled PWM output. It allows Continuous operation with interrupt generation Stop timer on match with interrupt generation Reset timer on match with interrupt generation. Pulse period and width can be any number of timer counts. It allows flexibility between resolution and repetition rate. Programmable double edge controlled PWM output.
USB device controller It is a 4 wire serial bus, supports communication between a host and peripherals.
Controller allocates the bandwidth to devices through a token based protocol. It supports hot plugging, unplugging and dynamic configuration of the devices. Transactions are initiated by the host controller. Fully complaint with USB2.0 full speed specification. Supports 32 physical endpoints. It supports Bulk, Interrupt and Isochronous endpoints. Scalable realization of endpoints at run time.
USB device controller ‌.cd. Endpoint maximum packet size selection by software at run time. RAM buffer size based on endpoint realization and maximum packet size. It supports SoftConnect and Goodlink LED indicator. These two functions are sharing one pin.
It supports bus powered capability with low current. Supports DMA transfer on all non-control endpoints. One duplex DMA channel serves all endpoints. Allows dynamic switching between CPU controlled and DMA modes. Double buffer implementation for bulk and isochronous endpoints.
I2C bus serial controller It contains two I2C bus controllers. The bus is Bi-directional, using only two wires. Serial Clock Line (SCL) Serial Data Line (SDA) Each device is recognized by a unique address. Bus is a multi-master bus, it can be controlled by more than one bus master connect to it. Supports bits rates upto 400 Kbits. Easy to configure as master, slave or master/slave.
It can be used for test and diagnostic purposes.
SPI and SSP controller Serial Peripheral Interface controller : It is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Only a single master and single slave can talk at a time.
Synchronous Serial Port controller :
It contains one SSP It is capable of operation on Motorola’s SPI, TI’s 4-wire SSI, NS Microwire bus. It can interact with multiple masters and slaves on the bus. Supports full duplex transfers with data frames of 4 bits to 16 bits of data.
UART device controller It contains two UARTs. Apart from standard transmit and receive data lines, it provides a full modem control handshake interface. Provides a fractional baud rate generator with any crystal frequency above 2 MHz. Auto CTS / RTS flow control functions are fully implemented in hardware. Sixteen byte Receive and Transmit FIFO. Register locations confirm to industry standard.
Real Time Clock Designed to provide a set of counters to measure time when normal / idle mode of operation. It uses ultra low power, suitable for battery powered systems. To maintain a calendar and clock Provides Seconds, Minutes, Hours, Day, Month, Year, Day of week and Day of Year.
Uses dedicated 32KHz oscillator input or clock derived from the external crystal input. Dedicated power supply pin can be connected to a battery
Watchdog Timer It contains two I2C bus controllers. The bus is Bi-directional, using only two wires. Serial Clock Line (SCL) Serial Data Line (SDA) Each device is recognized by a unique address. Bus is a multi-master bus, it can be controlled by more than one bus master connect to it. Supports bits rates upto 400 Kbits. Easy to configure as master, slave or master/slave.
It can be used for test and diagnostic purposes.
System Control On-chip integrated oscillator operates with external crystal in range of 1 – 25 MHz. PLL accepts an input clock of 10 – 25 MHz. The input frequency is multiplied into the range with a Current Controlled Oscillator. Reset has two sources, the RESET pin and Watchdog reset. Reset pin is a Schmitt trigger input with an additional glitch filter. When the internal reset is removed, the controller begins executing at address 0000. The wake-up timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the controller is allowed to execute instructions
System Control ..cd. Two stage monitoring of the voltage on the Vdd pin. If this falls below 2.9v, the Brownout Detector generates an interrupt to the VIC.
Code-security allow an application to control whether it can be debugged or protected from observation. External Interrupt inputs include upto nine edge / level sensitive, selectable pin functions. It can be used to wake-up the controller from power down mode Supports Idle and Power down mode of operation. Reset / specific Interrupt is used to come out. VPB divider determines the relationship between the processor clock and the clock used by peripheral devices.
Interrupt Controller Vectored Interrupt Controller accepts all the interrupts. • Fast interrupt request • Vectored interrupt request • Non-vectored interrupt request.
Priorities of interrupts can be dynamically assigned and adjusted. Fast interrupt request has the highest priority.
Vectored interrupt request have the middle priority. Sixteen of the interrupt request can be assigned to this category. Any interrupt can be assigned to any of the 16 vectored IRQ slots. Slot 0 has the highest priority. Non-vectored interrupt requests have the lowest priority. VIC combines the requests from vectored & nonvectored IRQs to produce the IRQ signal to the ARM processor.
Emulation and Debugging It supports emulation and debugging via a JTAG serial port. Standard ARM embedded ICE logic provides on-chip debug support. Debug Communication Channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The data and control registers are mapped into addresses in the embedded ICE logic. Embedded Trace Macrocell provides real time trace capability for deeply embedded controller core.
Real monitor – It is a configurable software module, developed by ARM, which enables real time debug. It runs in the background.
ARM development board -
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