PIC - 16F877 Architecture
R. Theagarajan. ME., MSc., PhD Rtd. Professor in Engineering email: rtheagarajan@yahoo.com rtrajan59@gmail.com
Programmable Interface Controller
Peripheral Interface Controller
Pin details
Pin details
Pin details
Key Features – 16F877 MAX Operating Frequency
20MHz
FLASH Program Memory (14-bit words)
8K
Data Memory (bytes)
368
EEPROM Data Memory (bytes)
256
I/O Ports
RA 0-5 (6) RB 0-7 (8) RC 0-7 (8) RD 0-7 (8) RE 0-2 (3)
Timers
3
Capture Compare PWM
2
Serial Communications
MSSP, USART
Parallel Communications
PSP
10-bit Analog-to-Digital Module
8 Channels
Instruction Set
35 Instructions
Pins (DIP)
40 Pins
Features of 16F877 • High performance RISC CPU • Only 35 single word instructions • All single cycle instructions except for program branches which are two cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • Up to 8K x 14 words of Flash Program Memory, Up to 368 x 8 bit of Data Memory (RAM) Up to 256 x 8 bit of EEPROM Data Memory
Features of 16F877 • • • •
Pinout compatible to PIC16C74B, 76, 77 Eight level deep hardware stack Interrupt capability (up to 14 sources) Addressing modes Direct, Indirect and Relative addressing • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
Features of 16F877 • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • Programmable code protection
• Power saving SLEEP mode • Selectable oscillator options
• Low power, high speed CMOS Flash / EEPROM • Fully static design
Features of 16F877 • In-Circuit Serial Programming (ICSP) via 2 pins • Single 5V In-Circuit Serial Programming capability • In-Circuit Debugging via two pins • Processor read/write access to program memory • Wide operating voltage range 2.0v to 5.5v • High Sink / Source Current : 25 mA
Features of 16F877 • Commercial, Industrial and Extended Temperature ranges • Low-power consumption < 0.6 mA typical @ 3v, 4 MHz 20 μA typical @ 3v, 32 KHz < 1 μA typical standby current
Peripheral features of 16F877 • Timer0 8-bit timer/counter with 8-bit pre-scalar • Timer1 16-bit timer/counter with pre-scalar, can be incremented during SLEEP via external crystal clock • Timer2 8-bit timer/counter with 8-bit period register, pre-scalar and post-scalar
Peripheral features of 16F877 • Two Capture, Compare, PWM modules • Capture is 16-bit, max. resolution is 12.5 ns • Compare is 16-bit, max. resolution is 200 ns • PWM max. resolution is 10-bit • 10-bit multi-channel Analog-to-Digital converter
Peripheral features of 16F877 • Synchronous Serial Port (SSP) with SPI (Master mode) and I2C (Master/Slave) • Universal Synchronous Asynchronous Receiver Transmitter with 9-bit address detection • Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls (40/44 pins) • Brown-out detection circuitry for Brown-Out Reset (BOR)
33
I/O
Oscillator 16F877A
4 modes
8K 368 locations
P. Memory
RAM
33
256 bytes EEPROM
I/O
Oscillator 16F877A
4 modes
8K 368 locations
P. Memory
RAM
33
256 bytes EEPROM
I/O
Oscillator
4 modes
16F877A
Peripherals 8 Analog
An. Comp
2
8K 368 locations
P. Memory
RAM
33
256 bytes EEPROM
I/O
Oscillator
4 modes
16F877A
Timers
3
Peripherals 8 Analog
2
CCP
An. Comp
2
8K 368 locations
P. Memory
RAM
33
256 bytes EEPROM
I/O
Oscillator
4 modes
16F877A
USART
Timers
3
Peripherals 8 Analog
MSSP
2
CCP
An. Comp PSP
2
Architecture
Pin details • • • • •
RA0-5 RB0-7 RC0-7 RD0-7 RE0-2
: Input / Output port A : Input / Output port B : Input / Output port C : Input / Output port D : Input / Output port E
• AN0-7
: Analog input port
• • • •
: USART Asynchronous Receive : USART Asynchronous Transmit : Synchronous serial clock input : Output for both SPI and I2C modes
Rx Tx SCK SCL
Pin details • DT • CK
: Synchronous Data : Synchronous Clock
• SDO • SDI • SDA
: SPI Data Out ( SPI mode ) : SPI Data In ( SPI mode ) : Data I/O ( I2C mode )
• CCP1,2 : Capture / Compare / PWM • OSC1/CLKIN : Oscillator In / External Clock In • OSC2/CLKOUT : Oscillator Out / Clock Out
Pin details • MCLR
: Master Clear ( Active low Reset )
• Vpp • THV • Vref+/-
: Programming voltage input : High voltage test mode control : Reference voltage
• SS
: Slave select for the synch. serial port
• • • •
: Clock input to Timer0 : Timer1 oscillator output : Timer1 oscillator input : Clock input to Timer1
T0CKI T1OSO T1OSI T1CKI
Pin details • PGD • PGC • PGM
: Serial programming data : Serial programming clock : Low voltage programming input
• INT • RD • WR
: External interrupt : Read control for the parallel slave port : Write for the parallel slave port
• CS • PSP0-7
: Select control for the parallel slave : Parallel slave port
• Vdd • Vss
: Positive supply for logic and I/O pins : Ground reference for logic & I/O pins
Ports • Five ports are available Port A – 6 bits Port B – 8 bits Port C – 8 bits Port D – 8 bits Port E – 3 bits
Input / Output Ports â&#x20AC;˘ All Ports are Bi-Directional â&#x20AC;˘ Direction of the ports is controlled by the TRIS(x) registers.
X varies depending on the Port being used.
E.g. TRISA is used to set the direction for PORTA. TRISB is used to set the direction for PORTB and so on.
Input / Output Ports • Setting a TRIS(x) bit ‘1’ will set the corresponding PORT(x) bit as input. • Clearing a TRIS(x) bit ‘0’ will set the corresponding PORT(x) bit as output.
Input / Output Ports • Example: movlw B’00001111’ movwf TRISB Will set D3-D0 as input and D7-D4 as output in Port-B
movlw B’11110000’ movwf TRISC Will set D3-D0 as output and D7-D4 as input in Port-C
Status Register - 03h, 83h, 103h, 183h D7
D6
IRP
RP1
D5 RP0
D4
D3
D2
D1
D0
TO
PD
Z
DC
C
Carry Bit 0 = No Carry 1 = Carry
Register Bank Select Bit 0 = Bank 0, 1 1 = Bank 2, 3 Register Bank Select Bits 00 = Bank – 0 01 = Bank – 1 10 = Bank – 2 11 = Bank - 3
Zero Flag Bit 0 = No Zero 1 = Zero
Power Down Bit 0 = Nu execution of SLEEP 1 = After CLTWDT
Timer Out Bit 0 = WDT timer-out occurred 1 = After Power-up
Option_Reg Register - 81h, 181h D7
D6
D5
D4
D3
D2
D1
D0
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Bit value 000 001 010 011 100 101 110 111
Port-B pull-up 0 = Enable 1 = disable Interrupt Edge 0 = falling 1 = rising TMR0 source 0 = internal clock 1 = on RA4
Pre-scaler assignment 0 = Timer0 1 = WDT
TMR0 source edge 0 = low to high 1 = high to low
= = = = = = = =
TMR0 rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256
Program Memory • Thirteen bit Program Counter • Capable of addressing 8K • Device has 8K Flash program memory • Reset vector 0000 • Interrupt vector is at 0004h
Program Memory map
Data Memory Partitioned into four banks RP1 RP0 Bank 0 0 0 0 1 1 1 0 2 1
1
3
Bits of RP1 & RP0 of the STATUS register selects the bank access.
It contains the General Purpose Registers & SFR It has 368 byte of Data Memory It has 256 byte of EEPROM
Stack It has an 8 level deep, 13 bit wide stack Implemented as a circular buffer. The stack is neither readable nor writeable. The PC is pushed onto the stack when CALL occurs. PC is popped out of the stack if a return Ins. occurs
Special Function Registers
Special Function Registers
Special Function Registers
Special Function Registers
Special Function Registers
Special Function Registers
Special Function Registers
INTCON register - 0Bh, 8Bh, 10Bh, 18Bh D7
D6
D5
GIE
PEIE
TMR0IE
D4
D3
D2
D1
INTE
RBIE
TMR0IF
INTF
Global Int. Enable 1 = Enable 0 = Disable
D0 RBIF
Timer0 Int. Flag 1 = Overflow 0 = did not overflow
Peripheral Int. Enable 1 = Enables 0 = Disables
Port change Int. Flag RB7:RB4 pins 1 = pins changed 0 = no pins changed
TMR0 Int. Enable 1 = Enables 0 = Disables
RB port change interrupt enable bit 1 = Enables 0 = Disables
Ext. Interrupt 1 = Enables 0 = Disables
External Int. Flag 1 = Int. occurred 0 = did not occur
ADCON1 register - 9Fh D7
D6
ADFM
ADCS2
D5
Conversion clock select bit With ADCON0
ADC result format 0 = Left justified 1 = Right justified
D4
D3 PCFG3
D2 PCFG2
D1
D0
PCFG1
PCFG0
Port configuration bits 0 0 0 0 = all are analog channels 0 0 1 0 = AN0 to AN4 analog channels 1 0 0 1 = AN0 to AN5 analog channels
ADCON0 register - 1Fh D7 ADCS1
D6
D5
D4
D3
ADCS0
CHS2
CHS1
CHS0
Analog Channel Select bits
S2 0 0 0 0 1 1 1 1
S1 0 0 1 1 0 0 1 1
S0 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 =
Fosc / 2 Fosc / 8 Fosc / 32 Clock from internal Osc Fosc / 4 Fosc / 16 Fosc / 64 Clock from internal Osc
D2
D1
GO
D0 ADON
1 = AD module powered ON 0 = AD module is shut Off
Setting this bit starts convertion, automatically cleared by hardware when convertion is over
CCP1CON register - 17h, 1Dh D7
D6
D5
D4
D3
D2
D1
CCPxX
CCPxY
CCPxM3
CCPxM2
CCPxM1
D0 CCPxM0
Not used in CC mode. PWM LS bits Eight MS bits are found in CCPRxL register
Mode selection bits 0000 - CCP is disables 0100 - Capture mode, every falling edge 0101 - Capture mode, every rising edge 0110 - Capture mode, every 4th rising edge 0111 - Capture mode, every 16th rising edge 1000 - Compare, set output on match 1001 - Compare, clear output on match 1010 - Compare, generate Int. on match 1011 - Compare, trigger special events 11xx - PWM mode
RCSTA – Receive Status & Control Register - 18h D7 SPEN
D6
D5
D4
RX9
SREN
CREN
No of bit Receive 1 = Selects 9 bit 0 = Selects 8 bit
D3
D2
D1
D0
ADDEN
FERR
OERR
RX9D
Continuous Receive Enable bit. 1 = Enables 0 = Disables
Serial Port Enable bit. 1 = Enabled 0 = Disabled Synchronous mode – Master. 1 = Enables single receive 0 = Disables single receive Don’t care in Slave and Asynchronous mode
9th bit of received data Overrun Error bit 1 = Overrun error 0 = No overrun error
Framing error bit. 1 = Framing error 0 = No framing error
Address Detect Enable bit. 1 = Enables address detection 0 = Disables address detection
TXSTA â&#x20AC;&#x201C; Transmit Status & Control Register - 98h D7 CSRC
D6
D5
D4
TX9
TXEN
SYNC
D3
D2
D1
D0
BRGH
TRMT
TX9D
9th bit of Transmit data No of bit Transmit 1 = Selects 9 bit 0 = Selects 8 bit
USART mode select bit. 1 = Asynchronous mode 0 = Synchronous mode
Clock source select bit. 1 = Master mode 0 = Slave mode Transmit Enable bit. 1 = Enabled 0 = Disabled
Transmit shift register status bit 1 = TSR empty 0 = TSR full
High Baud Rate select bit. 1 = High speed 0 = Low speed In Asynchronous Unused in synchronous mode
EECON1 â&#x20AC;&#x201C; Control Register â&#x20AC;&#x201C; 18Ch D7
D6
D5
EEPGD
D4
D3
D2
D1
D0
WRERR
WREN
WR
RD
Read control bit 1 = Initiates read 0 = Does not initiate
Program / Data Memory select bit. 1 = Access Program memory 0 = Access Data memory
Write control bit 1 = Initiates write 0 = Write cycle is complete
Write Enable bit. 1 = Allows write cycles 0 = Inhibits write operation Error Flag bit. 1 = Write prematurely terminated 0 = Write operation completed
Avoid Plastics Plant a Tree Let us take care of our earth for future generation