PIC - 16F877 Timers
R. Theagarajan. ME., MSc., PhD Rtd. Professor in Engineering email: rtheagarajan@yahoo.com rtrajan59@gmail.com
Timers in 16F877
• Timer 0 • Timer 1 • Timer 2
Timer-0 in 16F877 • Timer 0 8-bit Timer / Counter 8-bit pre-scalar
Registers used with Timer-0 • Registers associated with Timer0 INTCON PIR1
PIE1 TMR2 T2CON PR2
Timer-1 in 16F877 • Timer 1 16-bit Timer / Counter Pre-scalar Incremented during SLEEP (via external crystal clock)
Registers used with Timer-1 • Registers associated with Timer1 INTCON PIR1
PIE1 TMR2 T2CON PR2
Timer-2 in 16F877 • Timer 2 8-bit Timer / Counter Period register Pre-scalar and Post-scalar
Registers used with Timer-2 • Registers associated with Timer2 INTCON PIR1
PIE1 TMR2 T2CON PR2
Timer mode Timer mode is selected by clearing TOCS in Option_Reg.
In timer mode, Timer0 will increment every instruction cycle without prescaler. Counter mode is selected by setting the bit TOCS. In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4 / TOCK1.
Incrementing edge is determined by the Timer0 source edge select bit TOSE in Option_Reg. Clearing bit TOSE selects the rising edge.
Option_Reg register - 81h, 181h D7
D6
D5
D4
D3
D2
D1
D0
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Bit value 000 001 010 011 100 101 110 111
Port-B pull-up 0 = Enable 1 = Disable
Interrupt Edge 0 = Falling 1 = Rising TMR0 source 0 = internal clock 1 = on RA4
Pre-scaler assignment 0 = Timer0 1 = WDT
TMR0 source edge 0 = Low to high 1 = High to low
= = = = = = = =
TMR0 rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256
Timer-0 Interrupt Timer-0 Interrupt is generated when TMR0 overflows from FFh to 00h. This overflow sets bit TOIF in INTCON register. Interrupt can be masked by clearing bit TOIE in INTCON. Bit TOIF must be cleared in software by the Timer-0 module interrupt service routine before re-enabling the interrupt.
TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut off during sleep. Prescaler is shared between Timer-0 and the WDT. The PSA and PS2, PS1 & PS0 bit in Option-Reg determines the prescaler assignment and the ratio. For T0, all instructions writing to the TMR0 will clear the prescaler. If assigned to WDT, a CLRWDT will clear the prescaler along with WDT.
INTCON register - 0Bh, 8Bh, 10Bh, 18Bh D7
D6
D5
GIE
PEIE
TMR0IE
D4
D3
D2
D1
INTE
RBIE
TMR0IF
INTF
Global Int. Enable 1 = Enable 0 = Disable
D0 RBIF
Timer0 Int. Flag 1 = Overflow 0 = did not overflow
Peripheral Int. Enable 1 = Enables 0 = Disables
Port change Int. Flag RB7:RB4 pins 1 = pins changed 0 = no pins changed
TMR0 Int. Enable 1 = Enables 0 = Disables
RB port change interrupt enable bit 1 = Enables 0 = Disables
Ext. Interrupt 1 = Enables 0 = Disables
External Int. Flag 1 = Int. occurred 0 = did not occur
Timer-1 Timer-1 contains two (TMR1H & TMR1L) 8-bit registers, which are readable and writable. TMR1 register pair increments from 0000 to FFFFh and overflows to 0000. Interrupt is generated on overflow, Latched to Int. flag bit TMR1IF in PIR1 register. This interrupt can be enabled / disabled by setting / clearing TMR1 interrupt enable bit TMR1IE in PIE1 register. Timer-1 can operate as a Timer or as a Counter.
The operating mode is selected by the clock select bit, TMR1CS in T1CON. Timer-1 can be enabled / disabled by setting / clearing control bit TMR1ON in T1CON register.
Peripheral Interrupts Enable register - 8Ch D7
D6
D5
D4
D3
RSPIE
ADIE
RCIE
TXIE
SSPIE
D2
D1
CCP1IE
TMR2IE
D0 TMR1IE
TMR2 to PR2 match Int. Enable 1 = Enable 0 = Disable
PSP Int. Enable 1 = Enable 0 = Disable
CCP1 Int. Enable 1 = Enables 0 = Disables
ADC Int. Enable 1 = Enables 0 = Disables USART Receive Int. Enable 1 = Enables 0 = Disables
Serial Port Int. Enable 1 = Enables 0 = Disables
USART Transmit Int. Enable 1 = Enables 0 = Disables
TMR1 overflow Int. Enable 1 = Enables 0 = Disables
PIR1 register – Flag bits - 0Ch D7
D6
D5
D4
PSPIF
ADIF
RCIF
TXIF
D3
D2
D1
D0
SSPIF
CCP1IF
TMR2IF
TMR1IF
TMR2 to PR2 match Int. Flag 1 = Occurred 0 = No match
PSP Int. Flag 1 = R/W occurred 0 = No operation
CCP1 Int. Flag 1 = CC occurred 0 = No CC occurred
ADC Int. Flag 1 = Conversion over 0 = not completed USART Receive Int. Flag bit 1 = Buffer full 0 = Buffer empty
Serial Port Int. Flag 1 = Tx / Rx has occurred 0 = No operation
USART Transmit Int. Flag 1 = Buffer empty 0 = Buffer is full
TMR1 overflow Int. Flag 1 = Overflowed 0 = no overflow
T1CON register - 10h D7
D6
D5
D4
D3
D2
D1
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS
D0 TMR1ON
T1 source select bit 1 = External clock 0 = Internal clock
Input clock pre-scale 11 = 1:8 pre-scale 10 = 1:4 01 = 1:2 00 = 1:1
Clock Input Sync. 1 = Do not sync 0 = Sync. When TMR1CS = 1
Oscillator Enable bit 1 = Enabled 0 = Disabled
Timer1 on bit 1 = Enables 0 = Stops
Timer-1 operation in Timer mode Timer mode is selected by clearing the TMR1CS in T1CON. The input clock to the timer is Fosc / 4. The synchronize control bit T1SYNC in T1CON has no effect since the internal clock is always in sync.
Timer-1 operation in Counter mode Timer 1 may operate in asynchronous or synchronous mode depending on the setting of the TMR1CS bit. When Timer1 is being incremented via an external source, increments occur on a rising edge. After Timer1 is enabled in counter mode, the module must first have a falling edge before the counter begins to increment.
Timer-1 operation in Sync. Counter mode
Counter mode is selected by setting of the TMR1CS bit.
The Timer is incremented on every rising edge of clock input on pin RC1 / T1OSI, when bit T1OSCEN is set OR on pin RC0 / T1OSO / T1CKI, when bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple counter. During SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off. However the prescaler will continue to increment.
Timer-1 operation in Sync. Counter mode
Timer-1 operation in Async. Counter mode
If T1SYNC in T1CON is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP mode and can generate an interrupt on overflow, which will wake-up the processor. Special precautions in software are needed to read/write the timer. In async counter mode, Timer1 can not be used as a time base for capture
or compare operations.
Timer-2 module Timer2 is an 8 bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for the PWM mode of the CCP modules. The Timer2 register is readable and writable and is cleared on any device reset. The input clock has a prescale option of 1:1, 1:4 or 1:16 selected by control bits T2CKPS1 and T2CKPS0 in T2CON. Timer2 increments from 00 until it matches to PR2 and then resets to 00 on the next increment cycle. PR2 is a readable and writable register. This PR2 is initialized to FFh upon reset. The match output of TMR2 goes through a 4 bit postscaler to generate a TMR2 interrupt. Timer2 can be shut off by clearing control bit TMR2ON in T2CON to minimize power consumption.
Timer-2 block diagram
T2CON register - 12h D7
D6
D5
D4
D3
D2
D1
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
D0 T2CKPS0
Timer2 clock prescale 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Timer2 post scale select bits 0000 = 1:1 post scale 0001 = 1:2 0010 = 1:3 .. .. .. .. 1111 = 1:16
Timer2 ON bit 1 = Timer is ON 0 = Timer is Off
Capture / Compare / PWM module This module contains a 16 bit register which can operate as a 16 bit Capture register 16 bit Compare register PWM master / slave duty cycle register Capture and Compare modes use Timer-1 PWM mode uses Timer-2
CCP1 module Capture / Compare / PWM Register-1 (CCPR1) is comprised of two 8 bit registers CCPR1L and CCPR1H
CCP1CON register controls the operation of CCP1. Special event trigger by a compare match and will reset Timer-1 and start an A/D conversion, if the A/D module is enabled.
Capture mode In Capture mode, CCPR1H and CCPR1L captures the 16 bit value of the TMR1 register when an event occurs on pin RC2 / CCP1.
Event is defined as Every falling edge Every rising edge
Every 4th rising edge Every 16th rising edge
Event is selected by control bits in CCP1CON. When capture is made the interrupt request flag bit CCP1IF in PIR1 is set. This interrupt flag must be cleared by software. In capture mode RC2 / CCP1 pin should be configured as an input by setting the TRISC.2 bit.
Capture mode block diagram
Compare mode In Compare mode, the 16 bit CCPR1 register value is constantly
compared against the TMR1 register pair value. When a match occurs, the RC2 / CCP1 pin is Driven high
Driven low Remain unchanged
The action on the pin is based on the value of control bits CCP1M in CCP1CON register. At the same time, interrupt flag bit CCP1IF in PIR1 is set. This interrupt flag must be cleared by software. In compare mode, user must configure the RC2 / CCP1 pin as an output by clearing the TRISC.2 bit.
Compare mode – block diagram
Registers associated with Capture, Compare and TIMER INTCON
T1CON
PIR1
CCPR1L
PIR2
CCPR1H
PIE1
CCP1CON
PIE2
CCPR2L
TRISC
CCPR2H
TMR1
CCP2CON
PWM mode In PWM mode, the CCPR1 produces upto a 10 bit resolution output. Since CCP1 pin is multiplexed with the Port-C data latch, the TRISC.2 bit must be cleared to make CCP1 pin an output. A PWM output has a time base and a time that the output stays high. The frequency of the PWM is the inverse of the period. The PWM period is specified by writing to the PR2 register. PWM period = Fosc / (4*Fpwm*TMR2 prescale value) – 1 When TMR2 is equal to PR2, the following events occur on next cycle, TMR2 is cleared CCP1 pin is set PWM duty cycle Is latched from CCPR1L into CCPR1H.
PWM mode – block diagram
Set-up for PWM operation
The following steps should be taken when configuring the CCP module for PWM operation Set the PWM period by writing to the PR2 register
Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON bits Make the CCP1 pin an output by clearing the TRISC.2 bit Set the TMR2 prescale value and enable Timer2 by writing to T2CON Configure the CCP1 module for PWM operation
Registers associated with PWM and TIMER2 INTCON
T2CON
PIR1
CCPR1L
PIR2
CCPR1H
PIE1
CCP1CON
PIE2
CCPR2L
TRISC
CCPR2H
TMR2
CCP2CON
PR2
Avoid Plastics Plant a Tree Let us take care of our earth for future generation