ChipTimer Timing & Area Optimizer by Library Technologies, Inc. Tools for Faster Cooler Smaller Chips
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Background •
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Founded in 1994 to provide characterization tools. Focused on chip level timing and power tools. Self funded.
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LTI Products LibChar CellOpt YieldOpt PLI-Calc ICpower AgeTimer UnBlock ChipTimer
Cell/Memory/IO characterization Dynamic Circuit Optimizer Process Variation Analysis Gate level Delay Calculator Gate level Power Simulator MOS aging/degradation analysis Tool RcBack Custom Block Modeling Timing/area/power Optimization
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Where Are We? 1. Chinnery/Keutzer & Kong/Markov 2. P&R Tools ≈ 2X away from optimal wire length 3. ASIC Flow is way behind in Performance & Power 4. Chips are slower, bigger and consume more energy than necessary. 5. Technology mapping is quasi-optimal. 6. Path timing optimization is quasi-optimal.
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How to Reduce Area? 1. 2. 3. 4.
Better design optimization (-10% to 10%) Reduce Clock Uncertainty for bigger slack Eliminate positive timing slack (2% to 10%) Better cell topology and aspect ratio (0 to 30%)
We implemented items 1, 2, & 3. We report on item 4.
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How to Improve Timing? 1. 2. 3. 4. 5.
Better design architecture - beyond our interest Better design through reoptimization (0 - 20%) Reduce area (0 - 5%) Special Optimized Cells (0-30%) Reduce Clock Uncertainty (0-10%)
ChipTimer implements 2, 3 & 4.
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How to Reduce Power? 1. 2. 3. 4. 5. 6. 7.
Better design architecture - beyond our interest Reduce Area (0 - 10%) Reduce # of Instances for fewer nets (0 - 5%) Reduce Leakage by VT swapping (0 - 4X) Reoptimize Cell Library (0 - 10%) Reoptimize Clock Tree, low uncertainty (5-10%) Reoptimize IO Buffers (0 - 10%)
2,3,4 are implemented in ChipTimer. Smaller area means shorter wires, less power. 5,6 are implements by CellOpt reducing cell internal dynamic power and leakage by 20% through better sizing. Internal power ≈ Capacitive Power.
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ChipTimer Flow Cell Function
Verilog Design
Design Constraints
RC/ETS DC/PT
ChipTimer
New Cell NetLists
New Verilog Design
Cell Netlist
MakeLib LibChar CellOpt
Spice Servers
New Cell Library
Verilog In, Verilog Out
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ChipTimer Stages Stage -1 Stage 0 Stage 1 Stage 3
Checks the integrity of the setup & files. Restructures and Reoptimizes the design. Reoptimizes the design by creating new cells. Area and Leakage Optimization.
Each stage of reoptimization can be applied in any order.
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ASIC Flow RTL Synthesis
ChipTimer Stage 3 Leakage Reduction
Rough Initial P&R Wireloads
ChipTimer Stage 0 Timing Optimization
P&R
ChipTimer Stage 3 Area Reduction
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Centered Wire Load Modeling 1. Pre-layout, their load need to be estimated. 2. If the wire loads match the average post layout wireloads, it is a centered model. 3. Statistical averaging keeps path delay variation limited. 4. Average wire length may be design specific, but may not be dependent on perturbatrions of the design. 5. Varitation is less for long paths. 6. Short paths are not likely to be critical.
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ChipTimer Flow 1. 2. 3. 4. 5. 6.
Use ’Centered’ custom wire loads Identify untouchable instances Run Stage -1 to test SDC, netlist and libraries Run Stage 0 for reoptimization, fast library Run Stage 1 for new cell creation if necessary Run Stage 3 for same VT area and leakage optimization 7. Place & Route 8. Run Stage 3 for multi-VT leakage optimization
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ARM Processor 1. 2. 3. 4.
40nm, Glue Logic Around ARM Cores Post-layout netlist analyzed for leakage 330K placeable instances, LVT library Stage 3 area/leakage optimization 10% smaller area 25% less leakage 30ps better timing
Area was not optimized properly before P&R.
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MIPS Core - 28nm 1. 450K placeable instances, LVT library 2. Post-layout netlist analyzed for performance 3. Stage 0 Reoptimization Timing improvement 17.4% Area 2% Critical Path 1023ps -> 845ps Critical Path reduced to Memory + 1 gate 4. Stage 3 LVT->LVT Area Optimization Area reduced further by 0.04% 13% less leakage No change in critical path Performance is memory limited.
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Flash Controller - 20nm 1. 26K placeable instances, special single drive library 2. Pre-layout Cycle time: 11.1ns, Violation: 11ns 3. Stage 0 Optimization 4. Violation: 0.43ns 5. Area Reduction 1.5% 6. Stage 1 Optimization 7. 8 new cells, Violation: 0ns Stage 3 leakage/area optimization was not possible because of the small library.
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32b Open Risc - 65nm 1. 24K placeable LVT instances, Period 2.4ns 2. Stage 3 Area Optimization (LVT -> LVT) Violation: 2.18ns -> 2.20ns Stdcell Area Reduction: 9.7% Stdcell Leakage Reduction: 32% 3. Stage 0 Optimization Violation: 2.18ns -> 0.7664ns Stdcell Area Reduction: -6.5% 4. Stage 0+3 ReOptimization (LVT -> LVT) Stdcell Area Reduction: 2.3% Leakage Reduction: 20% Performance limited by memory.
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Image/Camera - 65nm 1. 90K placeable SVT instances, Period 2.8ns 2. Stage 3 Area Optimization (SVT -> SVT) Violation: 0.9039ns -> 0.9569ns Stdcell Area Reduction: 4.7% Stdcell Leakage Reduction: 23.1% 3. Stage 0 Optimization Violation: 0.9039ns -> 0.6219ns Stdcell Area Reduction: -7.1% 4. Stage 0+3 Area Optimization (SVT -> SVT) Stdcell Area Reduction: 1.1% Leakage Reduction: 17%
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Image/Camera - 65nm 1. Stage 0+1+3 Optimization (SVT -> SVT) 55 new cells added to the library Violation: 0.9039ns -> 0.3567ns Stdcell Area Reduction: -5.5% Stdcell Leakage Reduction: -21.4% Clock Frequencey: 270Mhz -> 317Mhz
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