Ago Analog and RF Design Optimization

Analog and RF Design Optimization AgO Synthesis Inc. Hillol Sarkar Hillol.Sarkar@ago-inc.com www.ago-inc.com Overview 1. Schematic Capture 2. Equation based Optimization 3. Spice Simulator 4. Synthesis and Optimization

Tools 1. Cadence 2. Synopsys 3. Mentor 4. Silvaco 5. Tanner – 2015

Format 1. Hspice compatible Net List 2. PDK from Fab 3. Optimized Width and Length of transistors

Human Resource = 5 Engineering Staff

Experience 20+ Years in Circuit Designs

Complex Circuit Design

Dr. Claude Gauthier — MoSys The accelerating need for ever higher data rates and serial I/O density sets demanding performance requirements for next generation SerDes transceivers which must meet tighter performance specifications to meet the challenges of the overall link design.

System performance requirements come not just from the core networking infrastructure required to support Internet growth, but also from business and government demands for increasingly complex computation- and data-intensive applications such as weather prediction, financial analysis, genomics research, and design simulation. An emerging and challenging standard is the OIF CEI standard for 25G class designs. The standard retains the basic topologies and bit-error-rates of the lower data-rate standards (i.e. OIF CEI 11-LR which has BER of 10-15), however the data rate is over 2.5 times higher.

Achieving these specifications implies strong core-competencies in the following areas:

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System modeling and DSP capabilities to architect the best solution in terms of performance, power, and area

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Signal integrity and power delivery expertise to be able to co-design and verify the package, board, and to drive decoupling requirements

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Technologists to quickly evaluate new technology nodes and help drive solutions to complex circuit/technology interactions

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Circuit design excellence (Analog and Digital) to meet extremely tight timing and jitter requirements across process, voltage, and temperature

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Extensive verification and compute resources to simulate the design thousands of different ways for very long run lengths

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Test silicon and detailed characterization reports

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Robust integration and documentation

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Execution and program-management to ensure everything essential to highquality design is done on time

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Production testing and DFT capabilities to enable rapid testing of 25G designs

As data-rates increase, more and more companies are relying on the expertise of 3rd party IP vendors, such as MoSys, who make SerDes their lifeblood and can leverage the cost of developing an IP across multiple customers. MoSys is an industry leader in multi-protocol IP designs with offerings spanning data-rates from 1-Gbps to 28-Gbps, including designs which push the limits of wire-bond packaging higher. This article focuses on SerDes architecture, modeling, and important aspects of implementing 25/28-Gbps standards.

SerDes Architecture A simplified block diagram of the MoSys SerDes architecture is shown in Figure 1. The system uses equalization at the transmitter, linear equalization and DFE at the receiver.

Using just a feed forward equalizer (FFE) on the TX driver, it is theoretically possible to cancel much of the pre-cursor and post-cursor ISI, but at the cost of significant power and crosstalk. Using an analog linear equalizer in the RX, all the noise and crosstalk within the equalizer boost range will be enhanced. The discontinuities in the channel at high frequencies which may have been insignificant at lower data-rates can contribute significant noise. Crosstalk also becomes increasingly significant with both higher transitions required of higher data-rates and the higher densities in systems. Noise and crosstalk enhancement are very compelling reasons to begin using decision feedback equalization (DFE) in conjunction with traditional linear equalizers. A properly designed DFE can provide high frequency boost with little noise enhancement. The post-cursor ISI can be very many unit intervals with high insertion loss. For our architecture, we have designed the TX FFE to reduce the pre-cursor ISI, the DFE to provide high frequency boost to remove post-cursor ISI close to the cursor, and the analog LE to provide lower frequency boost which removes the post-cursor ISI further away from the cursor. The clock data recovery (CDR) can have a very significant interaction with the DFE, as the clock can affect the samples used by the DFE which in turn will affect the phase data used by the CDR. Therefore, we have found that it is important to optimize the TX FFE in order to produce symmetrical eyes in order to obtain optimal data sampling.

Figure 1 Simplified High Reliability SerDes Overview The random-jitter (RJ) of the PLL is the most critical aspect of the transmit path because RJ cannot be tracked and the timing budgets need to account for upwards of 16-sigma for 10-15 BER. High-quality LC clocks are critical to achieving the specifications in realsystems. An ultra-low jitter wideband LC PLL is used to meet the exacting requirements.

The keys to low-jitter are the use of a supply regulator with better than 20dB of supply rejection, and the inherent spectral purity of the LC oscillator. A fractional-N divider is incorporated into the final design. An example oscilloscope plot showing a MoSys ultralow jitter wideband PLL is shown in Figure 2. The design realizes 355fs of random jitter when operating on a noisy FPGA substrate in a 40nm LP technology.

Figure 2 LC PLL’s offer superior performance Customer-Specific System Modeling Great circuits are very important, however the key to knowing for certain that the design will work on first silicon is to build a good model into which customer constraints can be introduced and their effects evaluated. For example, a test-chip characterization report may show fantastic performance, however customer packages, boards, and the noiseintegrity of the substrate itself play a big role in the ultimate robustness of the design. At MoSys we build very detailed models of customer systems, leveraging our competence in signal integrity and design.

The model (Figure 3) includes the following:

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Transmitter equalization coefficients,

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Transmitter swing, rise/fall times

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Transmitter pad capacitance and termination

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Package and channel models, including cross-talk coefficients

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Receiver pad capacitance and equalization

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Adaptive gain control and continuous time linear equalizer frequency characteristics

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DFE adaptation, taps and feedback coefficients

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Clock distribution characteristics

Figure 3 Detailed System Models Are Critically Important During the design phase system models can be used to derive the CTLE parameters (gain, zero-location, boost), as well as the number of DFE taps, and determine the jitter components of the various blocks. If an IP provider doesn’t have this kind of capability the actual performance won’t be known until the chip comes back with the integrated IP. Contour plots are computed by integrating the joint PDF of cross-talk noise and total jitter across the open eye. Contour plots are plotted at 10-17 BER and take into account the TX RJ and DJ, Cross-talk noise, RX RJ and DJ. The next section addresses more specifically the design of a 25(LR)-28(SR)Gbps system.

25-28Gbps Design and Challenges A typical specification for a 25/28Gbps design is shown in Table 1. The detailed system model can be used to drive the architecture and design of the system.

Table 1 25/28Gbps Specifications

Figure 4 illustrates a typical loss and crosstalk noise profile for an FCI 28Gbps SR channel including aggregate crosstalk. You can see that even though the max insertion loss is < 10dB, there is significant distortion. Thus adaptive equalization and techniques generally applicable to long-reach at lower data-rates become useful. The detailed system model is used to evaluate architectural trade-offs which are beyond the scope of this paper, but can be discussed under NDA.

Figure 4: 28Gbps FCI Channel Characteristics Figure 5 illustrates the model output when crosstalk is included. You can see that the solution is very robust even at 10-17 bit-error-rates.

Figure 5: 28Gbps Received Eye Diagram Indicates Good Margin Summary Designing SerDes IP is becoming an increasingly complex task requiring competencies in several areas. For that reason, more and more companies are opting to use 3rd party IP and effectively share development costs with other companies, while leveraging the expertise of those teams. For example, LC PLL design is mission-critical for 25Gbps design â&#x20AC;&#x201C; having extensive experience with those is a must for an IP provider.

MoSys offers silicon proven multiprotocol designs at several process nodes and foundries. Customers are supported by local applications teams and very rigorous system modeling capabilities which help ensure first silicon success.

MoSys has taken the lead with 25Gbps development and expects to be among the first providers to bring the technology to market.