AgO Circuit Synthesis

Circuit Synthesis

Hillol.Sarkar@ago-inc.com 1

ÂŠ Copyright AgO Inc 2011

ago-inc.com

100X Faster Simulation and Six Sigma Optimization

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ÂŠ Copyright AgO Inc 2011

Challenges in Analog & RF Design Maximising yield • Validating greater numbers of process, voltage and temperature corners • Efficiently centering design across all PVT corners using Monte Carlo Achieving design specification • Meeting or beating performance while minimising cost of implementation • Managing greater complexity in operating and power saving modes Respin avoidance • Analog circuits are responsible for ~ 50% of IC design re-spins • Re-spins can mean missing market windows and unbudgeted costs Design porting • Moving existing circuit designs to similar technologies • Re-centering design to meet constraints of new technology 3

Classic Analog Design Methodology • Design methodology has changed little over the years • Manual, iterative design with many SPICE runs Design specification & constraints

Define topology & resize devices

Spice

Physical layout & adjust Spice Extraction Layout verification 4

Optimization Strategy

Description • DC Operation • Increase Margin • Quick check • Best Design Space

Description • Single Corner • Meet performance • Monte Carlo • Ready for Center

Description • All Corners • Rapid Size • Ready for P&R

AgO Optimization Strategy 5

Description • Conflict • Change Priority • System Analysis

AnXplorer Goals • • • • • •

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Quickly size W/L a circuit in a given technology Explore suitability of different design options Robust design over PVT & Monte Carlo Support all types of devices Explore results using database Optimize production yield

AgO Design Methodology AnXplorer automates device sizing Design specification & constraints

Define topology

Feasibility Global

Physical layout & adjust

Extraction Layout verification

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ÂŠ Copyright AgO Inc 2011

Centering

Porting of Existing Circuits Common challenge • Port existing design in technology X (say 180 nm) to technology Y (in 180 nm) • Ensure that original design goals are met

AnXplorer approach • Start with original sized circuit • Define variable ranges for target circuit • “One click” command • Optimises and centers with new PVT corners

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Vendor X

Same Node Porting Vendor Y

Prioritized Design Objectives • Most tools support a weight-based prioritization for multiple objectives – Designer is often unsure of relative weights

• AnXplorer supports hierarchical design objectives – User defines relative priority of different objectives

• AnXplorer achieves important objectives before optimizing others

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Implicit Objectives Correct by Construction • Imposes implicit objectives on conditions of devices at DC operating point • Customizable objectives • Detects common sub-circuits and imposes constraints on their operating conditions • Ensures a robust DC operating point • Feature only available for MOS devices

Examples of subcircuits:

• transistors in • • • • • • •

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saturation transistors in linear region current mirrors level shifters differential pairs voltage reference current mirror banks etc

Core Optimization Technology Early Optimisation tools • Frequently relied on traditional convex/gradient methods • These are known to have difficulty with multiple local minima AnXplorer • Based on Evolutionary algorithm • Capable of finding global minimum in presence of many local minima • Successfully optimised tough tests e.g. Rastrigin’s function • Optional logarithmic partitioning of design space 11

Supports both simulation-based optimization & equation-based optimization

Multiple Local Minimum

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Trade-off Analysis • Finds multiple design points satisfying design objectives • Creates exploration database for postoptimization analysis – Database stores all explored design points – Query language or GUI

• Useful for trade-off analysis with conflicting objectives • Useful for “what-if” analysis 13

Industry Standard Formats Compatible with existing design flows Un-sized circuit Schematics

Definition of Design variables

Design objectives

AnXplorer

Sized and centered net list

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Exploration database for Trade off analysis

Design Environment • Spice Simulators Silvaco SmartSpice Cadence Spectre Synopsys Spice Simulators Mentor Eldo Multi-threading support

• Operating system Red Hat RHEL 5

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Silvaco • Accurate circuit simulation • 100% HSPICE and SPECTRE compatible Netlists • Single event effect reliability analysis • A leader in run-time simulation speed • Largest collection of Spice Models

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Competitive Differentiation • One product, four optimization steps • Robust Centering to maximize yield –Monte Carlo • Implicit objectives for stable DC operation • Hierarchical design objectives • User can perform trade-off analysis • Industry standard formats and simulators • Core based on Evolutionary Algorithm

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