A Comparative Analysis of Copper and Carbon NanoTubes Based Global Interconnects by Allied Journals

International Journal of Engineering, Management & Sciences (IJEMS) ISSN-2348 –3733, Volume-2, Issue-5, May 2015

A Comparative Analysis of Copper and Carbon NanoTubes Based Global Interconnects Arti Joshi, Gaurav Soni  Abstract-Due to continuous advances in technology scaling, modern integrated circuits consist of billions of transistors. Interconnects between the gates in these transistors were considered as ideal conductors that propagated signals instantaneously. While device sizes were shrinking with each technology generation, multilevel metal structures rose higher and higher above the surface of the silicon and soon began to dominate the landscape of the integrated circuit. In the sub 100nm scaling regime, interconnect behavior limits the performance and correctness of VLSI systems. The wiring in today’s integrated circuits forms a complex geometry that introduces capacitive, resistive, and inductive parasitics. They can cause an increase in propagation delay, impact on energy dissipation and the power distribution and introduce extra noise sources, which affects the reliability of the circuit. As the device size scales down the impact of interconnect in the VLSI circuits became even more significant. The performance of copper interconnects tend to get reduced in the sub 100nm range and hence we need to examine for other interconnect via options. Single Wall Carbon Nanotubes exhibit better performance in sub 100nm processing technology due to their very large current carrying capacity and large electron mean free paths. Initially we have analyzed the performances of a copper based CMOS inverter for 32nm technology node. SPICE simulations were carried out to validate the results and the results show improved performance of CNT interconnects in terms of power and delay time in comparison to traditional copper based interconnects. This work suggests using Single Wall Carbon Nanotubes (SWCNT) as interconnects for global interconnects in VLSI design as they consume less energy and gives more throughput and bandwidth when compared with traditional Copper wires. Index Terms: Copper, SWCNT, Global Interconnects

I. INTRODUCTION

the landscape of the integrated circuit. In the sub 100nm scaling regime, interconnect behavior limits the performance and correctness of VLSI systems. The wiring in today’s integrated circuits forms a complex geometry that introduces capacitive, resistive, and inductive parasitics. They can cause an increase in propagation delay, impact on energy dissipation and the power distribution and introduce extra noise sources, which affects the reliability of the circuit. As the device size scales down the impact of interconnect in the VLSI circuits became even more significant. It controls all of these important electrical characteristics on the chip [29]. Also as the width of wires is decreased, the resistance increases. This increase in wire resistance causes RC delay to increase. The spacing between wires has been decreasing to the point where the coupling between wires is significant. The resulting capacitive coupling introduces additional delay and noise effects. II. LIMITATIONS OF COPPER INTERCONNECTS In the past copper wire replaced aluminum wires due to the low resistance of copper wires when compared with aluminum wires and also the resistance to electromigration was much higher in copper when compared with aluminum, now copper wires are going through similar problems due to the increasing resistivity and as a result, wire delay is becoming serious concern especially when the processing technology approaching the sub nanometer regime. From the report of International Technology Roadmap for Semiconductors (ITRS) plotted below we find that copper resistivity for future technologies is increasing at a very fast rate [7].

Due to continuous advances in technology scaling, modern integrated circuits consist of billions of transistors. Interconnects between the gates in these transistors were considered as ideal conductors that propagated signals instantaneously. Interconnects are used to connect components on a VLSI chip, connect chips on a multichip module and connect multichip modules on a system board. While device sizes were shrinking with each technology generation, multilevel metal structures rose higher and higher above the surface of the silicon and soon began to dominate Manuscript received February 20, 2015. Arti Joshi, Department of Electronics & Communication, Poornima University, Jaipur, India, (e-mail: arti.joshi@poornima.edu.in ). Gaurav Soni, Department of Electronics & Communication, Poornima University, Jaipur, India, (e-mail: gaurav.soni@poornima.edu.in).

Figure 1 : Increase in Cu Resistivity with Technology Scaling [7]

We find that the increase in resistivity is not much when we

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A Comparative Analysis of Copper and Carbon NanoTubes Based Global Interconnects

move from 90nm to 32nm technology node, but as we reduce the feature size further from 32nm, we see a sharp resistivity increase due to scattering effects. Besides increasing resistivity, the wire width is also shrinking with newer technologies. That further increases the overall resistance, since resistance of a wire is inversely proportional to the wire width. Therefore, even though the wire length is getting smaller, but decreasing cross section area and increasing resistivity resulting in higher interconnect delay, which is not a good sign as we always look to obtain higher speed. Hence as we look deeper into the circuit level issues, we find that as we slowly move from deep sub-micron technology to nanotechnology, the traditional copper wires will not be able to keep up, and we will need to look beyond conventional materials for interconnect design. Consequently, alternative solutions such as metallic carbon nanotube (CNT) interconnects have been proposed in order to avoid the problems associated with global on-chip wires altogether. III. CARBON NANOTUBES Carbon Nanotubes popularly called by the acronym CNT was discovered by Sumio Lijima in 1991. Nanotubes are composed of sp2 bonds, similar to those observed in graphite and they naturally align themselves into ropes held together by Vander Waals forces. These are allotropes of carbon with a cylindrical nanostructure.

conceptualized by wrapping a one-atom-thick layer of graphite (or graphene) into a seamless cylinder. The way the graphene sheets wraps can be represented by a pair of indices (n,m) called the chiral vector. The relationship between n and m defines three categories of CNTs viz: arm chair, zigzag and chiral. MWCNTs consist of multiple layers of graphite rolled in on them to form a tube shape with an interlayer spacing of 3.4 Å. The outer diameter of MWCNTs may range from 1 to 50nm while the inner diameter is usually of several nanometers. B. . General Properties of Carbon Nanotubes The electronic transport in metallic SWCNTs and MWCNTs occur ballistically over long lengths owing to their nearly one dimensional electronic structure. This enables nanotubes to carry high currents with negligible heating. It is reported that the MWCNTs can carry high current densities up to 109 to 1010 A/cm2. CNT’s are the strongest and stiffest materials yet discovered in terms of tensile strength and elastic modulus respectively. This strength results from the covalent sp2 bonds formed between the individual carbon atoms. Standard single walled carbon nanotubes can withstand a pressure up to 24GPa without deformation. Depending on the direction in which the carbon sheet is rolled up i.e. chirality they exhibit metallic or semiconductor properties. Due to lack of chirality any bundle of CNT consists of both metallic and semiconducting nanotubes. For a given (n,m) nanotube, if n=m, the nanotube is metallic; if n-m is a multiple of 3, then the nanotube is semiconducting with a very small band gap, otherwise the nanotube is a moderate semiconductor. This work analyses the efficiency of using single-walled carbon nanotube bundle instead of copper as an interconnect material as they consume less energy and gives more throughput and bandwidth when compared with traditional Copper wires. IV. CIRCUIT PARAMETERS MODELLING To study the parasitic effects described above requires the introduction of electrical models that estimate and approximate the real behavior of the wire as a function of its parameters. A. Modeling Parameters for Copper:

Figure 2 : Carbon NanoTube [29]

Carbon Nanotubes (CNTs) are cylindrical carbon molecules with novel properties (outstanding mechanical, electrical, thermal and chemical properties: 100 times stronger than steel, best field emission emitters, can maintain current density of more than 1010 A/cm2) Figure 3: RLC interconnect model [19]

A. Types of Carbon Nanotubes

The resistance of a wire is:

CNTs are of two types namely, single walled carbon nanotubes (SWCNTs) and multi walled carbon nanotubes (MWCNTs). SWCNTs were discovered in 1993 and most of these have a diameter close to 1 nm, with a tube length that may be many thousands of times larger and up to order of centimeters. The structure of a SWCNT can be

Where, ρ is the resistivity of material (in Ω-m).

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International Journal of Engineering, Management & Sciences (IJEMS) ISSN-2348 –3733, Volume-2, Issue-5, May 2015 The wire capacitance is modeled as follows

This additional scattering resistance appears as distributed resistance per unit length in the equivalent circuit.

Where ε is the dielectric permittivity, s is the interwire spacing (assumed s = w), h is wire height and t is intermetal layer spacing. For global wires, we included inductance, as shown in the following equation:

It is important to note that the mean free path of a CNT is proportional to diameter [4]. The total capacitance of a CNT consists of two components: 1. Electrostatic capacitance (CE) 2. Quantum capacitance (CQ) Electrostatic capacitance is the intrinsic plate capacitance of an isolated CNT whereas the quantum capacitance accounts for the electrostatic energy stored in the nanotube when it carries current[10].

B. Modeling Parameters for CNT Bundles:

Figure 4 : Equivalent RLC circuit model for an isolated SWCNT [35]

The various parameters are: 1. 2. 3. 4.

Here ε is dielectric permittivity, d is CNT diameter, y is distance of CNT from ground plane and vF is fermi velocity 5 in graphite (8*10 m/s). The total inductance of a CNT consists of two components[10]:

RF is the fundamental (quantum) resistance, LCNT is the total inductance, CQ is quantum capacitance, CE is the electrostatic capacitance.

The fundamental resistance RF, is equally divided between the two contacts on either side of the nanotube. It can be expressed as[10]:

The mean free path of electrons in CNT is typically 1µm [4]. If CNT length is less than mean free path (λCNT), electron transport within nanotube is ballistic and the fundamental resistance is independent of its length and is given by (h/4e2 )=6.45kΩ. However, if the length is greater than the mean free path, an additional ohmic resistance results due to scattering which increases with length as[10]:

1. Magnetic inductance (LM) 2. Kinetic inductance (LK) In presence of a ground plane, the magnetic inductance per unit length is given by:

Apart from magnetic inductance, another inductive component appears due to the kinetic energy of the electrons. The kinetic inductance per unit length can be expressed as[10]:

V. CNT INTERCONNECT MODELS USED BY RESEARCHERS Here l is length of CNT.

[Navin Srivastava and Kaustav Banerjee, 2005] analyses the applicability of carbon nanotube (CNT) bundles

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A Comparative Analysis of Copper and Carbon NanoTubes Based Global Interconnects

as interconnects for VLSI circuits, while taking into account the practical limitations in this technology. A model is developed to calculate equivalent circuit parameters for a CNT-bundle interconnect based on interconnect geometry. Using this model, the performance of CNT-bundle interconnects (at local, intermediate and global levels) is compared to copper wires of the future. It is shown that CNT bundles can outperform copper for long intermediate and global interconnects, and can be engineered to compete with copper for local level interconnects. The technological requirements necessary to make CNT bundles viable as future interconnects are also laid out. At the local interconnect level; CNT-bundles with imperfect contacts do not give much performance improvement. In the case of long intermediate and global interconnects, densely packed CNT bundle interconnects show significant improvement in performance as compared to copper interconnects, in spite of imperfect metal-nanotube contacts [35]. [Hong Li, et-al, 2006] proposed an equivalent transmission line model for CNT interconnects & calculated the equivalent circuit parameters for CNT bundles. Also author has made performance comparisons between carbon nanotubes & copper interconnects at various interconnect levels using interconnects dimensions data envisioned by ITRS. Author examined several previous research works & desisted that conventional copper interconnect performance is degrading & is conflicting with the requirements of today’s high performance systems. The capacitance extraction of CNT bundle has been done using FEM method. After getting all the circuit parameters of CNT bundles and Cu wires, we can estimate the propagation delay of a CNT interconnect and compare it with Cu interconnect. Author showed that the delay of CNT bundle is smaller than Cu wire at either intermediate or global interconnect level. In particular at global level, the performance enhancement in delay reduction can be as large as 80% [14]. [Kyung-Hoae Koo, et-al, 2007] has presented a comprehensive analysis of the performances of Copper wire and MWCNT (Multi-walled Carbon Nano Tube) bundles across deep submicron technology nodes like 45nm, 32nm, 22nm and 16nm for the local, intermediate and global level of interconnects. The authors have studied about both copper wire and CNTs (which are classified in SWCNTs and MWCNTs), they have found that Carbon Nano Tubes(CNTs) have immense potential in dictating the future VLSI interconnect technology due to their great electrical, thermal properties, high mechanical stability, current carrying capacity and later's electromigration concerns at high temperature. They are the most promising one to replace the existing Copper interconnect technology. The authors have done simulations at 45, 32, 22 and 16 nm technology nodes using Specter simulator of Cadence .The analytical delay estimation was done in MATLAB which has computed on the basis of some analytical expressions. From some figures authors have achieved 85% performance advantage of MWCNT bundle over Copper wire. Finally authors have observed, in 16nm technology node, the performance advantage numbers are 50%, 90% and 85% for 20µm long local interconnect, 200µm long intermediate interconnect and 10000µm long global interconnect respectively. Then finally

they have concluded that MWCNT bundles show better performance over copper wire at all level of interconnects and technology nodes [15]. [Kyung-Hoae Koo, et-al, 2008] present promising options for replacing the existing Cu-based global/semiglobal and local wires. Authors quantify the performance of carbon nanotubes (CNTs) interconnects and compare it with Cu/low-κ wires for future high-performance integrated circuits. For a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, for a future technology node, authors compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density. The power density comparison is highly switching activity (SA) dependent. At lower bandwidth density and SA lower than 20%, an improvement in mean free path and packing density of CNT can render it most energy efficient. In general, the CNT bundle shows lower latency than Cu. For global wires, authors used proper R, L, C modeling to compare latency, power density/energy efficiency, and bandwidth density of Cu and CNTs. The first set of comparisons entailed latency and energy per bit as a function of technology scaling. Bandwidth density was varied using different implicit parameters: wire pitch for Cu and CNT. Finally concluded that CNT wires exhibit the lowest latency whereas the power density comparison depends on SA. High SA yielded the best results, whereas at lower SA of 20%, there is a critical bandwidth density below which CNTs have lower power density [16]. [Naushad Alam, et-al, 2009] has discussed the prospects of mixed bundle of Carbon Nanotubes (CNT) as low-power high-speed global interconnects for future VLSI applications. Author studied several previous research works which shows that as interconnect feature size shrinks, copper resistivity increases & the Cu wires becomes more vulnerable to electromigration. Author has examined the power dissipation and delay of CNT bundle interconnects & compared them with that of the Cu interconnects for power dissipation & delay at the 32-nm technology node. Mixed bundle of CNTs and Cu interconnects are modeled as an equivalent transmission line and the equivalent circuit parameters (R, L, C) were extracted, using Carbon Nanotube Interconnect Analyzer (CNIA) and BPTM tools. To extract the circuit parameters of mixed CNT bundle interconnect a realistic nanotube density of 5 x 1012 tubes/cm2 has been considered & the power dissipation of interconnects were calculated & analyzed using simulation runs with H-SPICE at a frequency of 500MHz with Vdd = 0.9V. The delay analysis is done at a frequency of 500MHz and voltage swing of 0.9V which shows that CNT bundle is faster than Cu interconnects because of the smaller resistances and capacitances. Finally concluded that power dissipation of local copper interconnect is smaller than the corresponding CNT bundle but at intermediate and global level, the CNT bundle consumes 1.5 to 4 folds smaller power than Cu. So mixed bundle of CNTs can replace Cu interconnects in future low-power high-speed VLSI systems [2].

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International Journal of Engineering, Management & Sciences (IJEMS) ISSN-2348 –3733, Volume-2, Issue-5, May 2015 [Sudeep Pasricha, et-al, 2010] presented a comparative analysis of Carbon Nanotube (CNT) interconnects as an alternative to the conventional copper (Cu)-based global interconnects. Since Cu based interconnects faced the problem of being susceptible to electromigration, rising crosstalk coupling noise, and parasitic resistivity, which reduces its reliability and performance. Author basically investigate the performance and energy impact of using CNT-based global interconnect alternatives in place of conventional Cu global interconnects at the system-level for several CMP applications. Discussed previous work done & concluded that a lot of work has been done in studying the properties of CNT’s but little work has done to analyze the impact of using CNT instead of Cu. First of all author presented an overview of RLC circuit models for 4 CNT global interconnect candidates i.e. SWCNT, SWCNT Bundle, MWCNT & Mixed SWCNT/MWCNT Bundles. Author compared the global wire delay of Cu and CNT interconnect alternatives across the 45–22 nm UDSM technology nodes & the results showed that other CNT alternatives have lower interconnect delays compared to Cu. Also the MWCNT wire in particular has a much lower delay due to its large concentric tubes. In order to analyze the overall performance and energy impact of CNT global interconnects author selected applications from the well known SPLASH-2 benchmark suite. Results showed that the applications now perform better with CNT global interconnects because of their lower signal propagation delays & Since CNTs have a marginally lower capacitance, a reduction in energy consumption (1%–11%) has been observed. Finally author concluded that SWCNTs are not as suitable for global interconnect buses due to their large ohmic resistance and very high delays but global MWCNT buses can provide performance speedups of up to 1.98× for CMP applications & a potential communication architecture energy saving of as much as 30% can be achieved with the advances in fabrication technology [32]. [Manoj Kumar Majumder, et-al, 2012] has presented an equivalent single conductor (ESC) model of SWCNT which potentially provides attractive solution in propagation delay and power dissipation & solve the problems associated with the Al & Cu interconnects i.e. electromigration due to higher current density. This model is accurate up to several tens of GHz and any distance from ground plane & follows two fold modeling approaches. Initially, a multi conductor transmission line (TL) model is presented & then it is reduced to the ESC one by assuming that all the shells of SWCNTs are connected in parallel at both ends. The author has compared the propagation delay and power dissipation using a DIL (Driver-Interconnect-Load) system for SWCNT structures with different number of shells. A CMOS driver with1V supply voltage is used for accurate estimation of delay and power dissipation. The ESC model of SWCNT structures replaces interconnect line in the bus architecture & the interconnect line ranging from length 400µm to 2000µm is terminated by a load capacitance CL of 10aF. Finally concluded that for increasing number of shells in SWCNTs,

the propagation delay reduces but power dissipation increases at global interconnect lengths. Thus SWCNTs with higher number of shells can be predicted as more appropriate candidate for future global VLSI interconnects [25]. VI. CIRCUIT MODELS, PARAMETERS USED AND RESULTS Table 1: Circuit Models and parameters used by Researchrs

Interconnect Model Used

RLC Circuit [5]

RLC Wire model [4]

Parameters

Result

TN=22nm dcnt=1nm Wire length=1/10mm, PMOS:NMOS=2:1 (W/L ratio) MFP= 1.6µm/2.8µm PD=1/3 /1 TN=22nm Wire length=10mm Cu ρ= 1.9µΩ.cm MFP= 1.6µm Vbias=4.7 V SA=20% TN=22nm Contact resistance=1.2KΩ

RLC Circuit [3]

MPF=2.8µm Scattering coefficient=0.5 Grain boundary coefficient =0.5 W/L ratio=2:1

Equivalent transmission line model [10]

For (MFP, PD) = (2.8µm,1), CNT has 5% delay advantage CNT interconnects consumes less power than Cu interconnects Increasing MFP results in decreasing Power density.

For MFP=2.8µm CNT’s are 1.2X energy efficient than Cu. For a metallic SWCNT density of one per 3 nm2, the bandwidth density can potentially increase by up to 40%

R= 0.198 kΩ L= 0.952 & 0.010 nH

While density of one per 6 nm2 offers less than10% improvement.

C=30.36 fF

RLC Equivalent Circuit model [6]

For (MFP, PD) = (1.6µm,1/3), CNT has 1.7% delay advantage

For MFP=0.9µm CNT’s has1.6X improvement in latency

Length =10µm Equivalent circuit metallic SWCNT’s [2]

Larger dcnt increases CNT resistance

TN=32nm Vdd=0.9 V at 700 MHz Length=200µm R=374.2 Ω L=317 Ph C=36.283fF TN=22/32 nm Length =10µm W=70n H=168nm Cu ρ= 2.963µΩ.cm

CNT bundle consumes 1.5 to 2 folds smaller power CNT bundle are 1.4 to 3 times faster than Cu interconnect CNT has an 80% performance enhancement in delay reduction.

VII. PERFORMANCE COMPARISON

Table 2: RLC Parametrs for Cu & CNT Interconnect

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A Comparative Analysis of Copper and Carbon NanoTubes Based Global Interconnects

Interconnect Length (μm)

Interconnect Cu CNT Cu CNT

200 1000

Interconnect Parameters L R (Ω) C (fF) (pH) 374.2 317 36.283 109.05 5270 28.3 1870.8 1907 181.42 546.44 26700 142.0

Note: All values have been taken from the IEEE Paper [1]

Experimentation is done using HSPICE and waveform is observed using CosmosScope. Power Simulation of a Cu based and CNT based interconnect is shown in Figure 5 and Figure 6 respectively. The input is taken in the form of a pulse and output power pulse is shown in figure above. The output waveform is simulated under the process of transient analysis.

used to compare SWCNT bundle interconnect with that of copper interconnects. The simulation results obtained strengthened the fact that CNT technology is a possible and viable replacement for the present copper based technology. ACKNOWLEDGMENTS I would like to express my deep gratitude and thanks to Dr. Mahesh Bundele (Coordinator, Research), Poornima University for giving me an opportunity to work under his guidance for review of research papers and his consistent motivation & direction in this regard. I would also express my sincere thanks to Mr. Gaurav Soni (Asst. Professor, ECE), Poornima University for their guidance and support. REFERENCES [1]

[2]

[3] Figure 5: Transient Response of Cu RLC Interconnect [4] [5] [6] [7]

[8]

Figure 6: Transient Response of CNT RLC Interconnect

VIII. RESULTS

[9]

The Cu and CNT global interconnects are modeled by RLC transmission line. Average and Maximum Power obtained is shown in below Table :

[10]

Interconnec

4455.5

15666

CNT

1208

2666.7

Average Power (μw)

Maximum Power

[11]

(μw)

[12]

IX. CONCLUSION This paper presents the limitations of existing copper based technology and recommends the carbon nanotube technology as the possible future alternative. To analyze Copper and CNT interconnect circuits and to study their parasitic effects requires the introduction of electrical models that estimate and approximate the real behavior of the wire as a function of its parameters. So, their equivalent RLC Circuit model is designed. SPICE simulations using PTM level 54 model is

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International Journal of Engineering, Management & Sciences (IJEMS) ISSN-2348 –3733, Volume-2, Issue-5, May 2015

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Arti Joshi, received the bachelor degree in Electronics and Communication Engineering from Laxmi devi Institute of Engineering & Technology, Alwarr. He is currently working as Research scholar at Poornima University. His area of interest is Interconnect Modeling in VLSI Circuits. Gaurav Soni, Presently working as Head of Department- Department of Electronics & Communication Engineering and Department of Electrical Engineering at Poornima University, Jaipur. He is having an experience of seven years. His areas of interest includes Electromagnetic field theory, Electronic devices and circuits, Network on Chip (NOC), Nanoelectronics and Bioelectronics. He has authored a book titled Radar & TV Engineering