Communications in Control Science and Engineering (CCSE) Volume 2, 2014
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The Design of FPGA-based Array CCD Sensor Drive System Chengtao Cai*1, Mingyan Wei2, Zhedong Qian3 1, 2
College of Automation, Harbin Engineering University, Harbin,China 150001
3
East China Sea Centre of Stan dard&Metrology,S.O.A. Shanghai,China 201306
*1
2
3
caichengtao@hrbeu.edu.cn; weimingyan@hrbeu.edu.cn; qzd2000@163.com
Abstract CCD Sensor is the crucial equipment for environment perception which is widely used in various fields such as surveillance,vision navigation and machine vision. The commercial CCD device has been encapsulated the sensor driver inside which is not opened for secondary development. Even this mode facilitates the usage but it really cannot content the customizable need. For solving this challenging but imperative issue, we designed a novel CCD sensor driver system which implements the efficient and effective image acquisition task in customizing approach. The working principle and driving timing sequence about ICX625AQA the interline CCD image sensor used in our system are discussed in detail.For handling with this data intensive task, a high performance Field Programmable GateArray (FPGA) controller is used for data allocation and translation, the peripheral circuits including AD9974 and CXD3400 drive interface which process the horizontal signal and vertical signal, respectively. The designed system proposed at the end of this paper. Keywords Interline Transfer; Field Programmable Gate Array(FPGA); Dual-channel Output; Charge Coupled Device(CCD)
Introduction Charge-coupled device(CCD) h as many excellent features, such as high sensitivity, large dynamic range, low noise, low power consumption and fast sampling speed. The CCD sensor is such a device for the movement of el ectrical [1] charge, usually from within the device to an area where the charge can be manipul ated .CCD image sensor convert s optical signal into charge signal by an optical -sensitive surface,and then according with certain rules to output imag e based on corresponding pulse timing driver.CCD image sensor has better performances in optical filling rate, the uniformity of the respon se of pi xels an d quantum efficiency than CMOS an d become a science of choice detector for [2] high frame rat e i maging acquisition system increasingly , The array CCD imag e sensors can be implemented in several different architect ures. The most commonarchitectures are full-frame, frame-transfer, and interline. Each of these architectures has its different approach to the problem of sh uttering. The interline transfer because of its [3] advantages and fast readout speed CCD camera has been used in high frequency . The mainly driving circuit of interline transfer CCD includes biased voltage circuit, the horizontal timing-driven circuit and vertical timing-driven circuit.In such circuits mentioned above, the first encountered i ssue i s how to generate theCCD drive timing. In generally, there are four different methods to deal with this challenging matter: direct digital circuits, [4] microcontroller-dri ven, EPROM-driven and programmable logic devices method . Programmabl e logic devices such as fiel d programmable g ate array (FPGA) includes many advantages such as the ability to re-program in the field to fix bugs, can be repeated or improved after completing the design and easy to update an d maintenance.Thus characteristics make the FPGA graduallydominates the application for CCD sensor driver an d. The driver circuits implemented based FPGA is higher integration, reliability an d performance, lower power consumption,ch eaper price [5] cost an d shorter development cycles period . In this paper, we focus on how to design a novel CCD sensor driver system which implements the efficient an d effective image acquisition task in customizing approach based on FPGA. Firstly, we discuss the parameters and work principlesaboutICX625AQA, one of the typical CCD sen sors. Secon dly, we describe the design of hardware driving circuit including horizontal drive,vertical drive an d voltage gen eration circuitas well as illustrate the circuit layout and man ufact ure board. Thirdly, we proposed the final board about the system. Finally,we concl ude our work an d prospectthe further tasks. ICX625AQA Structure and Characteristics ICX625AQA is an interline transfer area array color i mage sensor produced by S ONY Corporation, The total gross number of pixels upto2536 (H) Ă— 2068 (V), approxi mately 5.24Meg a, the valid number of pixels are 2456 (H) Ă— 2058
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(V), approxi mately 5.05Megaeffective pi xels.Each pixel unit cell size is 3.45μm (H) × 3.45μm (V), and the effective pixel imaging area is 86.39square millimeters. ICX625AQA fanouts the signal within dual output channels. There are three operating modes can be han dled when proper operating the sensor which are full pixel scan output model, 4/16 line output model and the center readout scan output mode. The i mage out put rate of the ICX625AQA can achieve to [6] 15 frames/sec in all-pixel scan mode also output using various addition and eli mination methods . This CCD imag e sensor is drived by one four- phase vertical transfer pulse (V1, V2, V3 and V4), one two-phase horizontal transfer pulse (H1 and H2), and one el ectronic sh utter pulse (SUB) and one reset pulse(RG) si multaneously.Those various pulses mentioned above combined with each other constitute CCD i mage sensor’s drive timing pulse. Driver Circuit Analysis and Design Stable power circuit is essential for ICX625AQA work properly; there are several extinguished powercircuits to provi de energy for the CCD sensor, such as the positive 15V bias voltage, the negative 8V bias voltage.The horizontal transfer pulse an d the vertical transfer pulsesareshown in Figure 1. Bias voltage circuits not only provides CCD sensorpower but al so content the power consume in FPGA main chip system, the horizontal drive circuit and vertical drive circuit provides horizontal driving clock signal and vertical dri ving clock signal for CCD sensor respectively. These circuits work harmoniousl y to en sure the CCD image sen sor can output the small analog signals which stan d for the environ ment light intensity. The small analog signals are prone to be influenced by the electronic noise, on e AD conversion circuit which holds high magnification times an d SNR is used for correct imageacqui sition. The relationships between those circuits mentioned above are shown in Fig.1. Bias voltage supply circuit Horizontal drive circuit
CCD
AD conversion
FPGA
vertical drive circuit FIG. 1 SYSTEM HARDWARE BLOCK DIAGRAM
The Horizontal Drive Circuit As discussed above, ICX625AQA adopts the dual-channel drivemodel to fanout the image signals which ask the AD conversion circuit must match this issue. In this section, we mainly focus on generating the CCD dri ve signal, in our work, we sel ectADI's AD9974 to provide horizontal pulses drive signal, The Circuit di agram of AD9974 is shown in Fig. 2. AD9974 integrates double- pass high-speed signal processing circuit, internalintegrated analog frontendprocessing circuit, including the black l evel clamping, CDS, programmabl e amplifier (VGA) and a 14- bit analog[7] to-digital converter circuit . AD9974 can be seamless connection with ICX625AQAan d can con veniently connect the clock signals to the ICX625AQA pins i.e.H1A, H1B, H2A, H2B, and RG1 , RG2 .AD9974 h as two three-wire serial communicationinterfaceswhich can be used to configure the internal registers for generating thehorizontal clock pulse an d forw ard analog control signal. The Vertical Drive Circuit In generally, The output voltage amplitude comes from FPGA cannot satisfy the requirement of CCD sensor vertical drive signal, To deal with this issue, we choose the exclusive drive chip produced by SONY named CXD3400 as CCD vertical driver chip. CXD3400 contains six ch annels an d can work at the high-speed readout mode. The CCD sensor ICX625AQA must be driven in ten channel vertical signals which are Vφ1, Vφ2 , Vφ3 an d Vφ4four-phase vertical drive signal while the signal Vφ2 an d Vφ3 further are divided into four signals. So, we have to use two CXD3400 chips to deal with the ten signals simultaneously. When the conversion inside the CCD sensor has been completed, the signals of Vφ2 and Vφ3 provide the VH, VM an d VL three-level signals synchronically to read out to the vertical conversion signal. The on e thing we have to emph asise is that the pins of CXD3400process circuit must be connected to FP GA pins directly in specific rule in order to ensure proper signal generation. Th e vertical drive circuit schematics based on two CXD3400 is shown in FIG. 3.
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FIG. 2 AD9974 SIGNAL CONNECTION SCHEMATICS
FIG. 3 CXD3400 SIGNAL CONNECTION SCHEMATICS
Circuit Layout And PCB Board Manufaction Base on the circuit schematics design mentioned above, we laid out the printed circuit board (PCB)in the DXP2004 the integrated development environment(IDE). Th e manufactionof the P CB board i s shown in FIG. 5, The No.1 stands for the combination of the CCD an d lens with a pins connector to facilitate change and protect the CCD sensor. Th e No.2 and No.3 stand for thecombinationof the horizontal drive chipAD9974and vertical drive chip CXD3400 respectively as w ell as the peripheral configuration circuit. The Horizontal and vertical drive chips are layouted aroun d the CCD sen sor adjacently for eliminating noise interference. The component labelled No.4 i s the power supply circuit. Th e No.5 st ates the output interfaces, including n etwork interface an d VGA interface. Th e No.6indicates core board interface. Through conducting whole experiment, this board is working properly an d generating the necessary timing signals for the CCD i mage sensor.
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FIG. 4 SOLDERING TEMPLATE
Conclusions In this paper, we di scussed how to design an d i mplement the novel CCD sensor dri ver system based onFPGA. Th e working principle and driving timing sequence about ICX625AQA the interline CCD i mage sensor used in our system are discussed in detail. We adopted the special vertical driver chip CXD3400 and horizontal driver chip AD9974 to enhance anti-jamming capability of thecircuits,, the peri pheral circuits includingAD9974 an d CXD3400 are illustratedOur work provides a practical approach to implement the efficient an d effective CCD sensor imag e acquisition task in customizing pattern. Acknowledgment The authors would like to thank to the review ers for their valuable comments which have improved this paper significantly. This work is supported by National Nat ural Sci ence Foun dation of China (No.61203255), Fun damental Research Fun ds for the Central Universities (HEUCFX41304), the Science Foundation for Youths of HRB (NO.2013RFQXJ106) an d the HeilongjiangProvince Postdoctoral S ustentation Fund(No. LBH-Q11135). References [1]
Leach R W. Design of a CCD controller optimized for mosaics[J]. Publications of the Astronomical Society of the Pacific, 1988: 1287-1295.
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Myers W A, Smith R D, Stuart J L, et al. NEMO satellite sensor imaging payload[C].SPIE's International Symp osium on Optical Science, Engineering, and Instrumentation. International Society for Optics and Photonics, 1998: 29-40.
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Rafael C. Gonzalez and Richard E. Woods. Digital Image Processing, Pearson Education, Inc, 2010:347-355.
[4]
Xianjun Wang. Circuit Design for High Integrated Photoelectric Encoder Base on SOC Singlechip[J]. Based Optics and Precision Engineering, 2011, 19 (5): 1082-1087.
[5]
Rui Tian, Chunyu Chen. Design of the Drive Circuit of the Large Array Frame Transfer CCD Based on FPGA [J]. 2010 Chinese instruments academic, industry conference (Proceedings 2), 2010.
[6]
Sony Corporation. Diagona l 11.016(Type 2/3) progressive Scan CCD image Sensor with Square Pixe for Color Cameras[Z].Japan: Sony Corporation,2007.
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Analog Devices corporation. Dual-Channel,14-Bit,CCD Signal Processor with Precision Timing Core. Analog Devices corporation,2009.
[8]
Wei Zhou, Jianying He, Jugen Nie. Implementation of the Programming and Configuring of CPLD and FPGA [J].Computer and Digital Engineering, 2006, 34 (1): 100-102. Chengtao Cai, received the B.S. degree in Control Theory and Control Engineering, M.S. and Ph.D. degrees in Control Science and Engineering in Harbin Engineering University in 2003, 2005 and 2008 respectively. From 2006 to 2007, he was a visiting scholar in National Research Councile of Canada. From 2008 to 2010, he was a Postgraduate Research at Institute of Ship and Ocean Engineering, Harbin, China.From 2011 to now, he is an associate professor in school of automation Harbin, China. He has been involvedin a variety of projects on environmental perception and image processing. Dr Cai got the Best Paper Awards atNational Doctor Research Forum in 2007 and got the Progress Prize in
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Science and Technology of Heilongjiang Province in 2013. Mingyan Wei is a master graduate student major in Control Science and Engineering in Harbin Engineering University, his research interest in embedded system design and image processing.
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