Signal Processing Design with Resource Guide 2016 by OpenSystems Media

@signal_proc

VOLUME 13 | NUMBER 1

FALL 2016

On the cover Continuing the heritage of DSP-FPGA.com, the 2016 Signal Processing Design Resource Guide features products such as the Annapolis Micro Systems – WILDSTAR UltraKVP for OpenVPX 6U & 3U.

DEPARTMENTS Using DSP and RF circuit co-design to reduce risk and cost » p. 6

By Murthy Upmaka, Keysight Technologies, Inc.

5 Signal processing Processing challenges ongoing and evolving By Mariana Iriarte, Associate Editor

ARTICLES

6 Test and measurement Using DSP and RF circuit co-design to reduce risk and cost By Murthy Upmaka, Keysight Technologies, Inc.

9 Optics Optical and electrical high-speed communication in HPEC systems By Thierry Wastiaux, Interface Concept

Optical and electrical high-speed communication in HPEC systems » p. 9

12 Optics Rugged fiber optics for radar applications

Interview with Gérald Persaud, Vice-President of Product Management at Reflex Photonics and Ray Alderman, Chairman of the Board for VITA

By Thierry Wastiaux, Interface Concept

14 COTS signal-processing designs COTS in space? Not so fast, say some rad-hard designers By Mariana Iriarte, Associate Editor

18 2016 Resource Guide Hardware

Operating Systems and Tools

COTS in space? Not so fast, say some rad-hard designers » p. 14

By Mariana Iriarte, Associate Editor

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7 Interface Concept – Rugged HPEC boards for your OpenVPX systems

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SIGNAL PROCESSING By Mariana Iriarte, Associate Editor

Processing challenges ongoing and evolving Advancements in processor technology mean that engineers and designers are able to meet the demand of signalprocessing requirements in applications ranging from radar and software-defined radios to high-performance embedded computing (HPEC), and space systems. Designing for exacting high- bandwidth as well as size, weight, and power (SWaP) requirements are no longer a major challenge, but now are simply a checkbox in the design process. Even so, challenges remain, but designers are finding ways to face those issues by using fiber-optic technology, multicore processors, commercial off-the-shelf (COTS) components, and codesign methodologies. Today’s reality: Servers are smaller, while their processing power and capabilities have increased. Users have the option to either build a custom-made system or use COTS components and reap those benefits. Intel processors have, arguably, taken over the market and solved processing capabilities that systems may require. Intel is the dominant player in this world for a simple reason, “Intel has been instrumental in defining not just the core microprocessor and instructionset architecture, but also the architecture of peripherals,” says Dirk Finstell, EVP for the Module Computer Product Segment at Adlink Technology in Frankfurt, Germany. “Companies that provide embedded-computing products based on the x86 architecture have been able to leverage that (chip-level) expertise by providing either proprietary or open-standard products that use a common I/O interface. Through the use of common connector pinouts, it is possible for customers to select from a wide range of hardware- and softwarecompatible peripherals with which they can customize their end products.” Customization is one avenue that designers go down, depending on the need of the user. The technology that has become the game changer in 2015? “The www.signal-processing.mil-embedded.com

the advent of multicore processors from Intel and Freescale as well as the use of multicore ARM processors in nearly every smartphone, everywhere,” states Doug Patterson, VP – Military and Aerospace Business at Aitech Defense Systems in Chatsworth, California. “Integrating the memory crossbar switch into the processor silicon took the bane of memory bandwidth limitations out of the ‘lowerperformance’ and ‘memory-thrashing’ equations altogether. Faster and larger memory has fueled more software developer creativity and more functional and capable systems. Software and operating systems – supporting virtual memory, multiuser and multiprocessing parallel executions of applications simultaneously – have advanced to finally start meeting the promises of true portability and application auto-level loading.” Another avenue is fiber-optic technology, which has enabled applications that require large amounts of data to be transferred at high speeds. It provides a solution that, says Thierry Wastiaux, senior vice president of sales at Interface Concept, is “suitable for use in connecting the thousands of transmit/ receive modules of the active antennas used in an AESA radar platform to the signal-processing system and more generally for connecting sensors generating important flows of data.” Radar and electronic-warfare applications have been able to implement fiber-optic technology in ways never considered in the past. Gérald Persaud, vice-president of product management of Reflex Photonics in Pointe-Claire, Canada states, “Radar is a key platform for fiber optics, especially phased-array radar, which requires a tremendous amount of bandwidth between the antenna array and the beamforming computer. When we get to the signalprocessing computer, we’re also seeing fiber optics being used among processors and FPGA [field-programmable gate array] boards to scale processing.”

Design challenges are not extinct, however, as engineers grapple with puzzles ranging from cost to ruggedization to meeting tomorrow’s requirements. The good news is that companies have new avenues open to solve these issues, whether that means specifying COTS components or covalidating during the design process to keep costs down. “Sometimes it’s cheaper to solve it with a better signal-processing algorithm,” says Dr. Murthy Upmaka, an application engineer at Keysight Technologies in New York City. “Knowing the best place to solve an issue and validating the solution before the final product is assembled is a benefit of an integrated codesign approach, as is the ability to minimize over design and improve system performance for a given budget.” says. Sometimes using COTS components is not always the best option as in space applications for example. While COTS components are attractive because they offer so much in terms of bandwidth and performance, critical space applications call for proven, radiation-hardened components that will last the life cycle of the end use and ensure reliability. To save money, the industry is heading toward “cheaper multicore processors [which] will be the norm for nearly all applications, with operating systems and apps taking advantage of the huge increases in parallelism,” Patterson says. Prices of the processors and memory will drop quickly as demand increases almost exponentially across all markets: commercial/consumer, industrial and defense. Interprocessor communications will continue to rise quickly and efficiently, passing multiple gigabytes-persecond of data between local [onboard] nodes as well as nodes across board boundaries via high-speed copper, then optical pathways, as the fears of implementing and using optical fiber are swiftly moved to the past.”

Signal Processing Design Resource Guide Fall 2016 |

TEST AND MEASUREMENT

Using DSP and RF circuit co-design to reduce risk and cost By Murthy Upmaka

In all areas of business, increased communication leads to more streamlined processes and greater potential for success. This is no less true in system design. Within large design organizations, baseband field programmable gate array (FPGA) and radio frequency (RF) signal processing communities have traditionally been separated both physically and by the resources available to them – with each group using very different techniques and tools. Today, however, many RF functions are moving into the algorithmic world and this is making communication between the two areas more crucial than ever. Co-design, a process whereby all stakeholders actively participate in the design process, offers a solution. While organizations have certainly successfully designed electronic systems like wireless communication systems, smart phones, and space systems without co-design, its use offers not only the potential for reduced risk and cost, but accelerated time-to-market as well. It’s not surprising then, that the co-design of baseband algorithms and RF distributed circuits has emerged as a critical and important trend. For modern design organizations, it’s now more imperative than ever that they simulate both Digital Signal Processor (DSP) and RF circuits together at the system level using mixed signals.

Co-design: benefits and challenges Co-design offers designers a number of important benefits such as when codesigning DSP and RF circuits, over design, inaccurate predictions, and difficulties in assembly can be prevented. In contrast, organizations that utilize

disparate design flows with little to no communication and don’t co-validate along the way can anticipate added cost and complications. The algorithmic engineers have a hard time accounting for RF signal impairments in the signal processing, while those working on RF circuits aren’t able to clearly see how their systems are being used in the overall infrastructure. Co-validation during the design process allows for some of these problems to be accurately accounted for, and lets organizations find the cheapest technique to solve a problem. Sometimes it’s cheaper to solve it with a better signal-processing algorithm. Other times it may be cheaper to buy a better RF amplifier. Knowing the best place to solve an issue and validating the solution before the final product is assembled is a benefit of an integrated, co-design approach, as is the ability to minimize over design and improve system performance for a given budget. Despite these benefits, DSP and RF co-design is not without its challenges. DSP and RF circuits are simulated with different techniques. DSP is typically done in the numeric and time domain whereas RF circuits are designed using frequencydomain techniques. Converting between the two domains takes a long time and even when RF is changed into the time domain, many elements still exist in the frequency domain. You either have a very detailed RF model that is trusted completely, but need to simplify the signals, or arbitrary signals on the baseband side with an extremely simplified RF. Co-design bridges the gap, offering the right level of b ehavioral modeling on both sides. While co-design of DSP and RF circuits can be used in many instances, it is particularly useful when designing phased array systems with adaptive beamforming where

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beam quality must be looked at in a system context. Additionally, it can be used for power amplifier linearization and envelope tracking, when changing the characteristics of the amplifier as a function of time. Co-design is also needed in end-to-end, wide bandwidth communications.

going into 1 dB compression. As it gets close to its compression point, a great deal of detail and sensitivity is lost and washed out. Loss of detail comes from other sources as well. For example, let’s examine an Analog to Digital Converter (ADC). When it is moved from 14-bit to 12-bit and then to 10-bit, banding starts and there is loss of detail (Figure 2). By the time 6-bits is reached,

Co-design in action: synthetic aperture radar To better understand the concept of co-design, consider the design of an RF receiver with acceptable performance that will not render the algorithms ineffective, and in particular, a sidelooking Synthetic Aperture Radar (SAR) on an airplane that covers an area on the ground. As the plane flies, its antenna beam sweeps the area. Linear frequency modulated radar pulses are continuously transmitted and return pulses are collected. Even if the ground is not visible with the naked eye from the plane due to clouds or fog, it is still visible to the radar due to the microwaves that penetrate these obstructions. From the returned pulses, an image is reconstructed. This reconstruction is enabled by signal processing algorithms. The returned signals are at microwave frequencies and, therefore, have to be properly down converted to the baseband before processing them. The RF receiver must perform this task without significantly degrading the signal quality. The reflection from the target is constructed from a picture of the target in the form of JPG or GIF. The reflected signal intensity is proportional to the luminosity of the picture. This type of modeling of the SAR echo is very close to that happens in the field at the same time it is very fast to simulate. While evaluating the quality of the images produced, the RF amplifier, RF mixer, down converting local oscillator (LO), amplifier nonlinearity, LO phase noise, and mixer characteristics are all considered. In this case, the LO phase noise caused the RF receiver’s contrast to suffer slightly (Figure 1). Although difficult to pick up with the eye, the impact can be seen in numeric measurements. On the other hand, a significant visible impact can be seen with the amplifier www.signal-processing.mil-embedded.com

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Figure 1 | From left to right, the impact of an increase in phase noise in the oscillator is shown. The amplifier is close to compression in the right image.

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Figure 2 | The change in image quality as A to D is changed from 14 to 6 bits can be observed from left to right.

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Signal Processing Design Resource Guide Fall 2016 |

TEST AND MEASUREMENT significant amounts of detail in the images are lost. At 6-bits, an Automatic Gain Control (AGC) may need to be added on the front end. Auto scaling can be performed to get it into the sweet spot of the ADC. If some of these things are added together with low quantization levels, phase noise and saturation, it starts to not be useful. In this example, we have also added jitter. In addition to the ADC resolution, there is clock jitter that spatially limits the range resolution on the radar. Whole baseband signal processing is used to clean this up and make the signal. If the transmit and receive architecture is not designed to its best functionality, the ability to architect algorithms to overcome these issues may be lost. High fidelity is needed on both sides for the architecture and algorithms to work together. By co-simulating both the RF and DSP worlds, the amplifier saturation has a relatively higher impact than the number of bits of the ADC. Further studies show that while performing this co-simulation, post-processing algorithms can be debugged and the optimal Fast Fourier Transform (FFT) size required for the pulse compression process derived.

FURTHER STUDIES SHOW THAT WHILE PERFORMING THIS CO-SIMULATION, POST-PROCESSING ALGORITHMS CAN BE DE-BUGGED AND THE OPTIMAL FAST FOURIER TRANSFORM (FFT) SIZE REQUIRED FOR THE PULSE COMPRESSION PROCESS DERIVED.

model of the RF amplifier was captured and used in the system simulation (Figure 3). The X-parameter model preserved the accuracy and detail of the simulation, while significantly reducing the simulation time – in this case, by more than a factor of 10 compared to the circuit level co-simulation. Other advanced techniques like circuit envelope are available to further improve the co-design process. By following this methodology, DSP-RF co-design can be accomplished and simulation times kept to a reasonable level. For modern design organizations, being able to co-validate these domains in one place, enables them to de-risk later aspects of a project, while also cross validating as they go. Ultimately, this allows for lower cost and faster time-to-market. SPD Dr. Murthy Upmaka, is an application engineer at Keysight Technologies. Upmaka’s work focuses on the Aerospace/Defense sector. Upmaka received a Ph.D in Physics from the Indian Institute of Technology, Madras. Keysight Technologies, Inc. • www.keysight.com

In addition to co-design, co-simulation can be used to achieve faster, more accurate simulation. As an example, consider the co-simulation of an actual RF circuit used in the SAR that was designed using Keysight SystemVue Electronic System Level (ESL) software and Advanced Design System (ADS) software. The software and system-level simulator were connected together to create a simulated image that would be created by the SAR (Figure 3). By using the actual RF circuit, the semiconductor level models and board parasitic can be brought into the system-level simulation. The advantage of this approach is that amplifier nonlinearity, noise, input and output mismatch, AM-AM and AM-PM, and memory effects can all be captured in the simulation. This co-simulation is accurate; however, it significantly increases the simulation time. To reduce this time, the X-parameter

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Figure 3 | The top images show a SAR simulation with real circuit co-simulation performed using Keysight SystemVue and Advanced Design System (ADS) software. The bottom images show an SAR simulation with an X-parameter model.

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OPTICS

Optical and electrical high-speed communication in HPEC systems By Thierry Wastiaux

Throughout the defense field, demand for high-volume/high-speed data transfer for high-performance embedded computing (HPEC) is growing rapidly. Systems such as software-defined radio (SDR) use advanced, complex waveforms, all of which need fast sampling and generate huge amounts of data to be transferred. Other tools, such as active electronically scaled array (AESA) radar systems, generate huge amounts of data to be processed and transmitted. High-speed transmission via boards and backplanes is starting to bump up against some physical limitations. Typical high-speed challenges include impedance mismatch, crosstalk noise, power and ground noise, and electromagnetic interference (EMI)/electromagnetic compatibility (EMC) performance. Impedance mismatches can occur due to line-width changes, vias, connectors, and cables. Designers and manufacturers of printed circuit boards (PCBs) must monitor manufacturing tolerances carefully and ensure that such parameters as effective dielectric constant and surface-roughness variation are tightly controlled. Crosstalk noise is due to electromagnetic coupling between signal lines, via-to-via coupling, and digital/RF coupling. Power and ground noise control and tight requirements on the power distribution network (PDN) are essential to provide clean www.signal-processing.mil-embedded.com

power to field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). In particular, an imperfect power and ground delivery system results in simultaneous switching output (SSO) noise that propagates through the PDN. Moreover, most of the above effects produce EM radiation. In order to design electronic boards with high-speed buses, designers can perform prelayout signal-integrity analysis through software simulation using design-automation tools. Such a tool allows the user to define all the constraints for designing PCBs, including material, size of the stack, tracks and vias, anti-pads, stubs, and spacing between the tracks. Post-layout signal-integrity verification must then be performed. Electromagnetic simulation of the designed PCB enables extraction of the “scattering parameters” in order to verify compliance with VITA 68, which defines a VPX compliance channel. To improve impedance control and limit signal reflections, backdrilling techniques on the PCB can eliminate unwanted stubs; this process, however, makes the manufacturing process of the boards more complex. Signal-integrity engineers today find that traditional electrical backplanes allow a data rate of as fast as 25 Gbps per differential link, provided that state-of-the-art techniques are used. The backplane connector remains one of the important limitation factors to reach this level. The industry is now under enormous pressure to develop new technologies, improve the performance of electrical transceivers, and define new standards and protocols to allow ever-higher throughput with lower energy consumption and smaller footprint. Signal Processing Design Resource Guide Fall 2016 |

OPTICS One attempt to overcome these challenges is to use the fiber-optic technologies originally developed for telecom applications. These technologies are now brought to HPEC by designing rugged versions of the standard components that can operate safely in a wide temperature range. In this vein, VITA has approved the 66.1 standard covering fiber-optic connectors, and is currently working on finalizing the 66.4 standard, a variant covering half-width interconnects. Reflex Photonics and Samtec are among the companies currently designing small, low-power, rugged transceivers for use in HPEC designs. These optical solutions are suitable for use in connecting the thousands of transmit/receive modules of the active antennas used in an AESA radar platform to the signal-processing system and more generally for connecting sensors generating important flows of data. These optical fiber solutions are clearly one of the ways to dramatically push the limits of high-speed data transfer

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Figure 1 | NRZ power spectral density.

through VPX backplanes. Moreover, they are the most readily available to designers today, even when higher cost and need for rugged packaging is considered. Signal-integrity engineers are now working on new technologies to try to push the data-rate limits on boards and electrical backplanes and further explore whether higher throughput could be achieved on classical differential links. The current protocols largely use the NRZ (Non Return to Zero) modulation technology. Many protocols – for example, PCIe, 1000BASE-T, 1000BASE-KX, 10GBASE-KX4, 10GBASE-KR, and Aurora – are based on the NRZ simple modulation for their physical layer. Figure 1 tracks the power spectral density of NRZ, “T” being the NRZ symbol

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period, with one symbol corresponding to one bit.

TO IMPROVE IMPEDANCE CONTROL AND LIMIT

As serial data rates go beyond 20/25 Gbit/s per link – and to try to reach 40/50 Gbit/s – signal impairments caused by increasing bandwidth means that the high-speed serial data industry must shift its approach. Simple, baseband, NRZ signal modulation techniques are being left behind in favor of more bandwidth-efficient PAM4 (four-level pulse amplitude modulation). PAM4 – which cuts the bandwidth in half by transmitting two bits in each symbol – must be distinguished from its symbol rate, referred to as Bd (baud). For example, a 56 Gbit/s PAM4 signal is transmitted at 28 GBd. The only high-speed serial PAM4 standard that has been released so far is IEEE 802.3bj 100 Gigabit Ethernet (GbE), 100GBASE-KP4. To reach 100 Gbit/s total data rate, it combines four lanes at 13.6 GBd. The success of PAM2-NRZ has meant limited adoption of 100GBASE-KP4, but does provide a solid basis for the future of the emerging PAM4 standards. Electrical PAM4 specifications will consist of multilane, low voltage, balanced differential pairs with embedded clocking and either transmitter or receiver equalization, or both. The increased impact of signal-to-noise ratio on PAM4 signals calls for forward error correction (FEC), which enables the maximum uncorrected bit-error rate (BER) to be increased to 10-6 for electrical signaling to achieve the data-rate targets, albeit at the price of some hardware complexity. Interface Concept is using high-speed fiber-optic technologies for two purposes. One target allows the connection of many optical fibers to a VITA 57.4 FMC carried by Virtex-7 and UltraScale/ UltraScale+ front-end processing boards. The IC-OPT-FMCa board can thus connect 12 Tx/Rx optical fibers to the highspeed transceivers of the last generation of FPGAs. This configuration offers a bandwidth of 480 Gbps on a small mezzanine board. Thanks to the backwards compatibility of the VITA 57 standard, this FMC can bring high-speed connectivity to VITA 57.1 as well as VITA 57.4 www.signal-processing.mil-embedded.com

SIGNAL REFLECTIONS, BACKDRILLING TECHNIQUES ON THE PCB CAN ELIMINATE UNWANTED STUBS; THIS PROCESS, HOWEVER, MAKES THE MANUFACTURING PROCESS OF THE BOARDS MORE COMPLEX.

FPGA carrier boards. In the case of VITA 57.1, a maximum of ten fibers only can be connected depending on the number of high speed transceivers in front of the high-speed serializer/deserializer (SerDes) pins of the FMC connector. On the IC-FEP-VPX3c, eight fibers can be connected to two Quad Virtex-7 transceivers, as seen in Figure 2. In the second instance, designers are looking to overcome the throughput limitations of the VPX connectors and backplanes by implementing the solutions defined by the VITA 66 standard. As an example, a version of the Interface Concept UltraScale VPX 3U board features a VITA 66.1 connector for 24 optical fibers connected to six quad GTH transceivers on the FPGA and replacing the P2 VPX connector. Simply put, when going well beyond 10 Gbit/s per differential link in a VPX chassis, the best short-term approach lies in using optical technologies. Looking farther out, it is clear that designers are reaching the limits of copper and that PAM4 modulation will be the basis of a believable path towards competitive 50 Gbit/s differential links. SPD Thierry Wastiaux is senior vice president of sales at Interface Concept, a European manufacturer of electronic embedded systems for defense, aerospace, telecom, and industrial markets. He has 25 years of experience in the telecom and embedded systems market, having held positions in operations, business development, and executive management. Prior to joining Interface Concept, he was responsible for the operations of the Mobile Communication Group and the Wireless Transmission Business Unit in Alcatel-Lucent. He holds an M.Sc. from France’s Ecole Polytechnique. Readers may contact him at twastiaux@interfaceconcept.com. Interface Concept • www.interfaceconcept.com

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Figure 2 | IC-FEP-VPX3c block diagram. Signal Processing Design Resource Guide Fall 2016 |

OPTICS

Rugged fiber optics for radar applications By Mariana Iriarte, Associate Editor

To meet size, weight, and power (SWaP) requirements as well as higher-bandwidth demands in radar applications, engineers are leaning towards fiber optics as the answer. The challenge is designing them to be rugged to withstand harsh environments. In this Q&A with Gérald Persaud, vice-president of product management of Reflex Photonics in Pointe-Claire, Canada and Ray Alderman, Chairman of the Board for VITA, they address these challenges. SIGNAL PROCESSING DESIGN: What military applications do we currently see using fiber optics? PERSAUD: Radar is a key platform for fiber optics, especially phased array radar, which requires a tremendous amount of bandwidth between the antenna array and the beam-forming computer. That’s where we’re seeing fiber optics being used because it’s lightweight and it has a lot of bandwidth that can move massive amounts of information. When we get to the signal-processing computer we’re also seeing fiber optics being used among processors and FPGAs boards to scale processing. Engineers are designing radar platforms more with fiber optics, in platforms such as land vehicles, aircraft, and naval ships, which require high-bandwidth systems. Many fiber optics transceivers in the market were not designed to be rugged. In the

past they were used in environments that were fully controlled, now we have ruggedized optics that could be used in extreme, harsh environments that meet high temperature shock, vibration, and damp environment requirements. ALDERMAN: Applications with large data streams and heavy processing requirements like electronic warfare (EW), radar, and signal intelligence are using fiber optics. The problem with copper is that it runs out of steam and can’t feed the advanced CPUs. We are I/O bound in these applications: the CPU can process more data than I/O links can deliver. The interconnects are trying to push toward 20 gigabits per second and copper just doesn’t have the bandwidth. VITA 66.1 standard focuses on optical connections. With optical, we can create huge increases in bandwidth. With V-66 optical connectors you can have up to 12 fibers in one connector. We

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are not talking about data centers and other networking types of implementations; those are benign environments. We are talking about critical military environments. VITA 66.1 tries to bring a lot of the requirements of optical together. The first thing you have to worry about is shock and vibration. You can’t have the beam moving around. If the beam goes off center, you loose data. SIGNAL PROCESSING DESIGN: What are some of the challenges with the use of fiber optics in systems? PERSAUD: From a system perspective, some engineers understand the benefits, but what they are concerned about is the reliability of fiber optics. At a system level, I think, you end up with a more reliable system when you go with fiber optics, especially with highbandwidth system. www.signal-processing.mil-embedded.com

Another concern that engineers always have is vibration. For example, when you mate the fiber cable connector to the optical transceiver, because it’s not a physical contact that’s being locked together, people are concerned that the vibration will cause the fibers to misalign and generate errors. This case is not true if you design the fiber connection correctly. However, where engineers have run into trouble is taking a commercial design and using it in a military application. For example, a DataCOM pluggable module is, such as a QSFP [quad small form factor pluggable]. It is meant for a quick-connect and has a commercial connector. It was never meant to tolerate a high vibration environment. When that quick-connect is used, it generates a lot of errors.

APPLICATIONS WITH LARGE DATA STREAMS AND HEAVY PROCESSING REQUIREMENTS LIKE ELECTRONIC WARFARE (EW), RADAR, AND SIGNAL INTELLIGENCE ARE USING FIBER OPTICS. THE PROBLEM WITH COPPER IS THAT IT RUNS OUT OF STEAM AND CAN’T FEED THE ADVANCED CPUS.

ALDERMAN: Optics are made of glass and plastic fiber. In critical applications, you can’t use plastic fiber. An electromagnetic pulse (EMP) can cause the plastic to degrade. With flexible glass fiber EMP will cause the glass to go dark, but it will recover. Another problem is single mode fiber, with one data channel. By going to multi-mode fiber, bandwidth is dramatically increased. With multi-mode, you can run multiple data channels without crosstalk and interference. There is also a problem with contaminants optics. You can’t get dust, dirt, or other contaminants on polished ends of the fiber. It will diminish the signal level. Those are two big ones, the beam can’t move around and you can’t get contaminants on the fiber faces. SIGNAL PROCESSING DESIGN: Where do you see this technology going in the future? In other words, how will this play out between copper versus optics? ALDERMAN: We are now moving into cognitive EW, which needs serious bandwidth to run algorithms to create a radar profile on the fly. That profile is used to transmit manipulated data and jam [our enemies] radar. Creating a profile of an enemy radar must occur rapidly. The software framework for cognitive EW relies on artificial intelligence (AI) techniques – software that will analyze the enemy signals and create a profile to spoof or jam their system. Optical has the bandwidth for this type of EW and the same for signal intelligence.

›

Figure 1 | The LightABLE is a family of multiple parallel-lane transmitter, receiver, or transceiver operating at 10 Gbps/lane. Photo courtesy of Reflex Photonics.

best option in meeting SWaP requirements and having a reliable system. I see fiber optics naturally displacing copper wires over time. Fiber optics has so many advantages over copper that most engineers have to understand it well in order to maintain a competitive advantage. A lot of VPX suppliers are starting to implement fiber optic connections between boards, as well. These companies are realizing they have no choice. SIGNAL PROCESSING DESIGN: How do you address shock and vibration in a harsh environment? PERSAUD: A rugged optic needs to be able to sustain a low bit air rate at very high bandwidth under harsh operating conditions of extreme temperatures, shock, vibration, and moisture. The question is how do we achieve that? In order to meet extreme shock/vibration environment, the component needs to be small, lightweight, and has to have a low profile and strong attach-strength to a board. For example, LightABLE (Figure 1) has a low profile, less than 5mm high. It’s about square centimeter. What’s key here is its low center of gravity, which allows it to tolerate a high-shock environment. Also, because it is soldered to the board, it has very high attached-strength. SPD

I see more applications needing greater bandwidth than copper connections in the future. Sensors are getting so sophisticated that the copper doesn’t have the ability to move the data. Purely from a performance standpoint, optical is the way to go.

Gérald Persaud Vice-President of Product Management at Reflex Photonics www.reflexphotonics.com

PERSAUD: This technology will displace copper for all types of transmissions in the future. Surveillance systems or information systems are becoming more reliant on high-resolution sensors, whether it’s radar, camera, or acoustic sensors. Because of the amount of bandwidth that is being transferred from these systems, fiber optics is the

Ray Alderman Chairman of the VITA Board of Directors www.vita.com

www.signal-processing.mil-embedded.com

Signal Processing Design Resource Guide Fall 2016 |

COTS SIGNAL-PROCESSING DESIGNS

COTS in space? Not so fast, say some rad-hard designers By Mariana Iriarte, Associate Editor

The role of commercial off-the-shelf (COTS) parts fielded in satellites and other space applications remains a hot topic as the demand for low-cost nanosatellites grows. COTS signal-processing designs are also attractive to military space system designers, but they fear the reliability of such components in long space missions. Budget constraints, demand for inexpensive small satellites, and other issues are forcing space-platform designers to consider using COTS components for space, but COTS parts may not be appropriate or desirable for all space missions.

Space 2.0 The market is open to the idea of using COTS in space. “This whole concept of building large constellations with COTS components, we refer to it as ‘new space.’ I’ve also heard it referred to as Space 2.0,” says Ken O’Neill, director of marketing, space, and aviation for Microsemi’s SoC Products Group in San Jose, California. “We are in dialogue with many companies who are proposing to create systems along the lines of using commercial parts and we are doing what we can to support it. We

also have to acknowledge the reliability of such systems is going to be the proof of the pudding. Everyone is waiting to see if they can create a constellation with cheap commercial products.” Budget constraints may be the driving factor for designers of space applications to find new ways of addressing the challenged posed by COTS components. The reality: Military officials want COTS components in applications where cost needs to be reduced. However, using COTS components where radiation-hardened components are required becomes more of a challenge to implement, versus spending the money in order to have a high-reliability system. “COTS components put a burden on the design team in order to do mitigation on the part,” O’Neill says. “There are mitigation techniques that are in the open domain – redundancy and using spares – those are the two things that you do to mitigate.” However, even using mitigation techniques, “You have to put more parts into the system than you would have otherwise,” he continues. “If you were using a COTS part, you would need to put triple-redundancy parts into this. That presents some challenges from the perspective of board space and power consumption. Now you have to supply power to three parts instead of one.

14 | Signal Processing Design Resource Guide Fall 2016

www.signal-processing.mil-embedded.com

COTS COMPONENTS MIGHT BE THE ANSWER FOR SMALL SATELLITES THAT ARE MISSION-SPECIFIC ONLY. “IN RECENT YEARS THE U.S. MILITARY HAS HAD THEIR OWN INITIATIVE ON SMALLER SATELLITES, WITH THE INTENT TO REDUCE LAUNCH COSTS AND THE TIME TAKEN BETWEEN MAKING A DECISION TO CREATE A SATELLITE TO FULFILL A MISSION AND GETTING THAT SATELLITE IN ORBIT,” O’NEILL SAYS.

Small satellite payloads have the opportunity to fly on rockets for upcoming launches under NASA’s CubeSat Launch initiative. Photo courtesy of NASA.

Using COTS components in space translates to more work: “Even worse,” O’Neill continues, “you also have to put some kind of voting and control mechanism, a system that monitors activity and makes a decision that one of the parts has an upset or is transient and that renders it inoperable, which needs to be reset. Something has to be a watchdog on there. That’s an extra component that needs to be powered and consumes board space.” Extra processing steps would have to be taken to make COTS components meet rad-hard requirements. Therefore, “most of the customers we are talking to today are leaning towards traditional, high-reliability hermetic ceramic packaged products to use in space,” says Larry Longden, vice president and general manager at Data Device Corp. (DDC) in San Diego, California. www.signal-processing.mil-embedded.com

There are still pros to using COTS components. “COTS to me has always had the ability to have a product on the shelf versus having to build to order,” says Chuck Tabbert, vice president of sales and marketing at Ultra Communications in Vista, California. “The advent of the Qualified Manufacturing Line (QML) system has made it possible to have companies build products to forecast and qualify the fabrication line versus building to the next order that comes in the door and running a lotspecific qualification.” Space applications need to last for a few years in orbit. “With small satellite constellations, they’re mostly in low-Earth-orbit (LEO) applications, chasing the ‘Internet in the sky’ mobile communications and Earth observation markets,” he continues. “The mission profile will probably not be that of the geosynchronous constellations and therefore the radiation requirements for these LEO applications will be less severe.”

Mission-specific small satellites COTS components might be the answer for small satellites that are mission-specific only. “In recent years the U.S. military has had their own initiative on smaller satellites, with the intent to reduce launch costs and the time taken between making a decision to create a satellite to fulfill a mission and getting that satellite in orbit,” O’Neill says. “The military runs the program called Operational Responsive Space (ORS), which is managed by the Air Force Research Laboratory (AFRL). There have been a number of ORS satellites already built and launched. Other, experimental, satellites have already been developed and launched, some of which have intended to see what can be done with small form factors.” Tabbert asserts that in order to make COTS components successful in space, rad-hard semiconductor folks [must be able] to anticipate what products will be selling in the small satellite market, keep the line qualified, and have products on the shelf in-house or at distributors, as well as keep the unit price competitive. The good news about the military is that “they will use whatever they can to get the job done – be it small satellite constellations, to hosted payload applications, to standard GEO and MEO constellations,” he continues. “With rumors of nation-states developing anti-satellite capabilities, it just makes sense to diversify one’s assets on Signal Processing Design Resource Guide Fall 2016 |

COTS SIGNAL-PROCESSING DESIGNS numerous platforms so no one strike can take down a capability. Small sat constellations have their place for certain missions.”

The lure of high-end signal processing COTS components are attractive because they offer so much in terms of bandwidth and performance. “The design community in radiation-hardened electronics is really working on solving the big signal-processing challenge,” O’Neill says. “The issue is that satellite operators are looking for an increased amount of information to come from their space assets, whether it’s remote sensing satellites, imaging, radar, or spectrometry.”

›

Figure 1 | NAND and NOR with RadPak technology. Photo courtesy of DDC.

›

Figure 2 | RTG4 development board with FPGA. Photo courtesy of Microsemi.

High bandwidth demands in satellite applications dictate the path designers take with rad-hard electronics. “The industry is leaning towards higher density memory products and higher speed A/D or D/A converters, along with more high-speed interface options,” Longden says. Also commanding attention is the need for speed. “Intra-satellite data-transfer bandwidth requirements are exploding. Point-to-point solutions between sensors and instruments to flight computer to mass-memory storage requirements are requiring 40 [Gigabits per second] Gbps transfer rates, which will increase to 100 Gbps in the next three to five years,” Tabbert says. Because of the high demand, “hardened- [field-programmable gate array] FPGA manufacturers are struggling to keep up. The need for 10 Gbps to 25 Gbps per channel connectivity is coming quickly,” he adds. The ultimate goal of these parts is “to be able to store and process all the data that [operators] are connecting on satellites. It’s a tremendous amount of data, and they

SPACE-SATELLITE BUDGET FUNDING While the military space market has never been known as an explosive one in terms of investment due to its long design cycles and low volumes, industry players say that orders are picking up. “Funding for military space programs have been slightly increasing,” says Ken O’Neill, director of marketing, space, and aviation for Microsemi’s SoC Products Group in San Jose, California. “[However,] the last two or three years have been quite difficult from the point of view of suppliers working with the U.S. defense community, as funding has been slow to release. We feel like we are being drip-fed a little bit.” Funding for satellites is being released at a rate of one satellite at a time, whereas five to ten years ago, those programs would have released funding for two, three, or four satellites at a time,” he notes. “It gives us less visibility from a forecasting point of view and makes things a little more difficult.” Those programs that are funded in manageable chunks only see “some pockets for procurements in the military side, but they are primarily related to satellites that have been on hold since sequestration began,” says Larry Longden, vice president and general manager at Data Device Corp. (DDC) in San Diego, California. “The market is not increasing. An example is that this year they began procurement again on Joint Polar Satellite System (JPSS) satellites, which had been on hold for a while.” To make the situation even more backlogged, already tested platforms are getting first dibs on funding, which puts the brakes on innovation. “I see procurements occurring for already designed satellites, ones that are ready, but I don’t see new budgets being created in the marketplace,” Longden continues. “The government has eliminated most of the budget for development in the space arena.” That’s not always the case, though, says Chuck Tabbert, vice president of sales and marketing at Ultra Communications in Vista, California. “For high data rate transfer applications, the market is booming. Most worldwide prime contractors are through the experimental evaluation and system design phase and many are moving into qualification and production in fiscal years 2016 through 2020.”

16 | Signal Processing Design Resource Guide Fall 2016

need faster and bigger memory to do that,” Longden says. “As well, they need faster and more accurate conversion products to be able to read that data from different analog systems.” One such memory product is DDC Microelectronics’ NAND-Flash memory, aimed at reaching those high-density, high-speed memory requirements for space. (See Figure 1). Another example of a product intended to meet the high-density, high-bandwidth data demands of space is Microsemi’s RTG4 board (see Figure 2). “It is intended to satisfy that demand for onboard signal processing. It has more logic resources and it’s got more multiply-accumulate blocks,” O’Neill says.

Embracing standards Taking advantage of signal processing innovation today also means leveraging standards. “We are seeing a lot of industry involvement in standards such as SpaceVPX,” says O’Neill. “It’s a standard that has a lot of industry alignment behind it,” he says. The standard “provides form factor and interconnect standards for board-to-board communications. In space systems, designers are using serial interconnects – 2.5 Gbps, even some as high as 3 1/8 Gbps, per lane – and of course those lanes can be ganged together,” O’Neill adds. www.signal-processing.mil-embedded.com

TAKING ADVANTAGE OF SIGNAL PROCESSING INNOVATION TODAY ALSO MEANS LEVERAGING STANDARDS. “WE ARE SEEING A LOT OF INDUSTRY INVOLVEMENT IN STANDARDS SUCH AS SPACEVPX,” SAYS O’NEILL. “IT’S A STANDARD THAT HAS A LOT OF INDUSTRY ALIGNMENT BEHIND IT.”

Standardization evens the playing field. Moreover, says Michelle Mundie, business area director, standard products, at Cobham Semiconductor Solutions in Colorado Springs, Colorado, “Leveraging open standards will enable more capabilities for the sensor payload. The SpaceVPX architecture of interconnects drives the standards for performance. New products can interconnect with one another to achieve performance. Standardizing the platforms will reduce design complexity and cost.”

›

Figure 3 | The UT64CAN333x series is packaged in an 8-lead ceramic flatpack. Photo courtesy of Cobham.

Cobham Semiconductor Solutions’ UT64CAN333x series of Controller Area Network (CAN) transceivers are designed to manage rates ranging from 10 kbps to 8 Mbps; all are designed in accordance with the ISO 11898-2/-5 standard (see Figure 3). “Cobham is focusing on rad-hard by design and rad-hard at process techniques while also addressing size, weight, and power (SWaP) requirements,” Mundie says. “This angle allows the company to look at different technology notes and interconnect architectures in satellites.” SPD

OpenSystems Media E-cast Applying HPEC and Deep Learning Technology to Defense Systems Sponsored by Kontron Technologies leveraged from advanced computing at data centers are providing new ways to tackle defense missions across embedded platforms. Deep learning is an increasingly popular approach to processing very large data sets. Attend the webinar to find out more about: • How deep learning algorithms can be applied to HPEC problems such as image processing and signal intelligence (SIGINT) applications • Performance-intense processing improvements with the newest Intel processors • Kontron’s StarVX HPEC system which provides a compact, high-density deployable platform for deep learning or other HPEC applications

ecast.opensystemsmedia.com/689 www.signal-processing.mil-embedded.com

Signal Processing Design Resource Guide Fall 2016 |

Signal Processing Design Resource Guide

Hardware Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that the customer’s applications succeed. We offer training and exceptional special application development support, as well as more conventional support.

High-Speed Fiber Optics in Wild40/100 EcoSystem Annapolis Micro Systems, Inc. is now building powerful FPGA boards with optical 48x connectivity. This VITA 66/67 architecture delivers 5X the bandwidth of copper. It is designed for super-high-performance data acquisition and processing, as is required in phased array radars and other applications where digital-to-analog or analog-to-digital converters are located close to the sensor. In addition, this fiber optic capability will now allow Annapolis Wild 40GbE systems to work at 100GbE.

FEATURES ĄĄ

ĄĄ

On a 6U card, have the capability for 5X the bandwidth of copper VPX 24 fibers in and out of every mezzanine card (48 fibers per 6U slot)

ĄĄ

Supports 14Gbps signaling rates, with 28Gbps to come

ĄĄ

Front panel MPO or VITA 66 backplane blindmate I/O

ĄĄ

Commercial & industrial temp

ĄĄ

Air and conduction cooled

signal-processing.mil-embedded.com/p373720

Annapolis Micro Systems, Inc. www.annapmicro.com

18 | Signal Processing Design Resource Guide Fall 2016

 wfinfo@annapmicro.com  410-841-2514

www.signal-processing.mil-embedded.com

WILDSTAR A10 2PE & 3PE for OpenVPX 6U Annapolis Altera FPGA boards are engineered for superior performance and maximum bandwidth. WILDSTAR A10 FPGA boards utilize Altera’s Arria 10 FPGAs, and are ideally suited for high-performance floating point (fractional integer) data processing. These FPGA cards are hot-swappable and paired with Annapolis OpenVPX compliant 6U/3U backplanes, enable even the most bandwidth-intensive applications. All Annapolis COTS boards are rugged, open, deployable, and offer different cooling options, making them the most cutting-edge Altera-based products on the market. Optional, Annapolis is now building powerful Altera FPGA boards with optical 48x connectivity. This VITA 66/67 architecture delivers 5X the bandwidth of copper.

Annapolis is famous for the high quality of our products and for our unparalleled dedication to ensuring that the customer’s applications succeed. We offer training and exceptional special application development support, as well as more conventional support.

FEATURES ĄĄ General Features

• Up to three Altera Arria 10® GX900, GX1150, GT1150 FPGAs – Hard 8x PCIe Gen3 endpoint for DMA and register access – FPGAs programmable from attached flash or Annapolisprovided software API – 20-nm copper CMOS process – Available with DDR4 DRAM ports on all FPGAs • Optional QDR-IV SRAM ports on IOPEs • Dual Core ARM Cortex-A9 Processor (Cyclone V SoC) – Host Software: Linux API and Device Drivers • PLX PCI Express Gen3 Switch – Allows data plane “chaining” of PCIe bus between adjacent slots. No dedicated PCIe switch slot needed. • A Full Board Support Package using Open Project Builder for fast and easy Application Development • System Management

ĄĄ Backplane I/O

• Two PCIe Gen3 4x Connections to VPX Backplane (P1) • 6 Backplane Protocol Agnostic connections support 10/40Gb Ethernet, IB capable, AnnapMicro protocol and user designed protocol • Optional optical VITA 66/67 connectivity • Radial Backplane Clock Support for OpenVPX backplane signals AUXCLK and REFCLK – Allows 10MHz clock and trigger from backplane to synchronize and clock compatible ADC/DAC mezzanine cards without front panel connections needed

ĄĄ Front Panel I/O

• Two Wild FMC+ (WFMC+) next generation IO sites based on FMC+ specification – Accepts standard FMC and FMC+ cards (complies to FMC+ specification) • Up to 32 High Speed Serial and 100 LVDS connections to FPGA

ĄĄ Mechanical and Environmental

• Available in Extended Temperature Grades • Air or Conduction Cooled Path • RTM available for additional I/O signal-processing.mil-embedded.com/p373743

Annapolis Micro Systems, Inc. www.annapmicro.com

www.signal-processing.mil-embedded.com

 wfinfo@annapmicro.com  410-841-2514

Signal Processing Design Resource Guide Fall 2016 |

Signal Processing Design Resource Guide

Hardware

Signal Processing Design Resource Guide

Hardware

WILDSTAR UltraKVP for OpenVPX 6U & 3U Annapolis Xilinx FPGA boards are engineered for superior performance and maximum bandwidth. WILDSTAR UltraKVP FPGA boards utilize Xilinx Kintex FPGAs, which feature the most multipliers currently deployable, or UltraScale+ FPGAs, which feature 28Gb signaling capability! These FPGA cards are hot-swappable and paired with Annapolis OpenVPX compliant 6U/3U backplanes, enable even the most bandwidth-intensive applications. All Annapolis COTS boards are rugged, open, deployable, and offer different cooling options, making them the most cutting-edge Xilinx-based products on the market. Optional, Annapolis is now building powerful Xilinx FPGA boards with optical 48x connectivity. This VITA 66/67 architecture delivers 5X the bandwidth of copper.

FEATURES ĄĄ General Features

• Up to three Xilinx® Kintex® UltraScale™ XCKU115, Virtex® UltraScale™ XCVU125/XCVU190 or Virtex® UltraScale+™ XCVU5P/XCVU9P FPGAs • – Hard 4x (3U) or 8x (6U) PCIe Gen3 endpoint for DMA • and register access • – FPGAs programmable from attached flash or • Annapolis-provided software API • – 16 or 20-nm copper CMOS process • – Available with DDR4 DRAM ports on all FPGAs • • 6U board has optional QDR-IV SRAM ports on IOPEs • Dual core ARM Cortex-A9 Processor (Zynq SoC) • – Host Software: Linux API and Device Drivers • A Full Board Support Package using Open Project Builder for fast and easy Application Development • System Management

ĄĄ OpenVPX Backplane I/O

• Two PCIe Gen3 4x (3U) or 8x (6U) Connections to VPX Backplane • 6 Backplane Protocol Agnostic connections support 10/40Gb Ethernet, IB capable, AnnapMicro protocol and user-designed protocols. Optional optical VITA 66/67 connectivity. • Radial Backplane Clock Support for OpenVPX backplane signals AUXCLK and REFCLK • – Allows reference clock and trigger from backplane to • synchronize and clock compatible ADC/DAC mezzanine • cards without front panel connections needed

ĄĄ Front Panel I/O

• Wild FMC+ (WFMC+) next generation IO site based on FMC+ specification • – Accepts standard FMC and FMC+ cards (complies to • FMC+ specification) • Up to 32 High Speed Serial and 100 LVDS connections to FPGA

ĄĄ Mechanical and Environmental

• Available in Extended Temperature Grades • Air or Conduction Cooled Path • RTM available for additional I/O signal-processing.mil-embedded.com/p373656

Annapolis Micro Systems, Inc. www.annapmicro.com

20 | Signal Processing Design Resource Guide Fall 2016

 wfinfo@annapmicro.com  410-841-2514

www.signal-processing.mil-embedded.com

Opal Kelly XEM7350 The XEM7350 is a perfect match for all three of the company’s target markets: Integration, Evaluation, and Acceleration. System integrators can build fully-operational prototype and production designs with offthe-shelf FMC peripherals. Manufacturers of high-speed devices such as JESD-204B data acquisition chips can launch evaluation boards as FMC peripherals. The XEM7350 is an ideal platform for demonstrating these devices to customers with a capable, compact system, and custom evaluation software built on the well-supported FrontPanel SDK. With ample logic resources, the Kintex-7 is also suited to signal processing and image processing for acceleration tasks when mated to image capture or data acquisition hardware. Celebrating 10 years of USB FPGA connectivity, Opal Kelly’s Front-Panel SDK fully supports the XEM7350 for real-world transfer rates in excess of 340 MiB/s. FrontPanel includes a multi-platform (Windows, Mac, Linux) API, binary firmware for the on-board Cypress FX3 USB controller, and atomic HDL modules to integrate into your design. FrontPanel is the industry's most full-featured, high-performance, turnkey solution for professional grade USB connectivity.

Opal Kelly Incorporated www.opalkelly.com



FEATURES ĄĄ Xilinx Kintex-7 XC7K70T, XC7K160T, or XC7K410T ĄĄ Small form-factor: 80mm x 70mm x 15.1mm ĄĄ VITA 57.1 FMC-HPC connector ĄĄ 512 MiB DDR3 ĄĄ Up to 170 user I/O + 8 Gigabit Transceivers ĄĄ Low-jitter 200 MHz and 100 MHz clock oscillators ĄĄ Integrated voltage, current, and temperature monitoring signal-processing.mil-embedded.com/p373661

sales@opalkelly.com

 217-391-3724

 opal-kelly-incorporated

 @opalkelly

Hardware

Opal Kelly XEM7360 The XEM7360 Kintex-7 based FPGA module offers a turnkey SuperSpeed USB 3.0 host interface using Opal Kelly's FrontPanel SDK. System integrators can build fully-operational prototype and production designs quickly by integrating this device into their product. Manufacturers of high-speed devices such as JESD-204B data acquisition devices can launch fully-functional evaluation systems without the costly design and maintenance of an evaluation platform. With ample logic resources, the Kintex-7 is well-suited to signal processing, image processing, and other logic-heavy acceleration tasks. Memory-hungry applications enjoy access to 2 GiB of on-board DDR3 memory with a 32-bit wide data bus. Celebrating over 10 years of USB FPGA connectivity, Opal Kelly’s FrontPanel SDK fully supports the XEM7360 for real-world transfer rates in excess of 340 MiB/s. FrontPanel includes a multi-platform (Windows, Mac, Linux) API, binary firmware for the on-board Cypress FX3 USB controller, and atomic HDL modules to integrate into your design. FrontPanel is the industry's most full-featured, high-performance, turnkey solution for professional grade USB connectivity.

Opal Kelly Incorporated www.opalkelly.com

www.signal-processing.mil-embedded.com



FEATURES ĄĄ Xilinx Kintex-7 XC7K160T or XC7K410T ĄĄ 2 GiB DDR3, 2x 16 MiB serial flash ĄĄ Two Samtec QSH-090 expansion connectors ĄĄ Up to 193 user I/O + 8 Gigabit Transceivers ĄĄ Low-jitter 200 MHz and 100 MHz clock oscillators ĄĄ Integrated voltage, current, and temperature monitoring ĄĄ Small form-factor: 100mm x 70mm x 19.65mm signal-processing.mil-embedded.com/p373664

sales@opalkelly.com

 opal-kelly-incorporated

 217-391-3724

 @opalkelly

Signal Processing Design Resource Guide Fall 2016 |

Signal Processing Design Resource Guide

Hardware

Signal Processing Design Resource Guide

Hardware

Model 71791 2-Ch 500 MHz A/D, Virtex-7 FPGA XMC Module Model 71791 is a member of the Onyx® family of high performance XMC modules based on the Xilinx Virtex-7 FPGA. It is suitable for connection directly to an L-band signal for SATCOM and communications systems. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying custom FPGA processing IP. It includes an L-Band RF tuner, two A/Ds and four banks of memory. In addition to supporting PCI Express Gen. 3 as a native interface, the Model 71791 includes general purpose and gigabit serial connectors for application-specific I/O .

The Onyx Architecture The Pentek Onyx Architecture features a Virtex-7 FPGA. All of the board’s data and control paths are accessible by the FPGA, to suport factory-installed functions including data acquisition, control, channel selection, data packing, gating, triggering and memory control. The Onyx Architecture organizes the FPGA as a container for data processing applications where each function exists as an intellectual property (IP) module. The 71791 factory-installed functions include two A/D acquisition IP modules, four DDR3 memory controllers, two digital down converters, an RF tuner controller, a clock and synchronization generator, a test signal generator, and a Gen 3 PCIe interface. Thus, the 71791 can operate as a complete turnkey solution with no need to develop FPGA IP.

Extendable IP Design

FEATURES ĄĄ ĄĄ

Accepts RF signals from 925 MHz to 2175 MHz Programmable LNA handles L-Band input signal levels from -75 dBm to 0 dBm Programmable analog downconverter provides IF or I+Q baseband signals at frequencies up to 123 MHz

For applications that require specialized functions, users can install their own custom IP for control or data processing. Pentek GateFlow FPGA Design Kits include all of the factory-installed modules as documented source code. Developers can integrate their own IP with the Pentek factory-installed functions or use the GateFlow kit to completely replace the Pentek IP with their own.

ĄĄ

Two FPGA-based multiband digital downconverters

Xilinx Virtex-7 FPGA

ĄĄ

Uses Xilinx Virtex-7 VX330T or VX690T FPGAs

ĄĄ

4 GB of DDR3 SDRAM

ĄĄ

Sample clock synchronization to an external system reference

ĄĄ

PCI Express (Gen. 1, 2, & 3) interface, up to x8

The Virtex-7 FPGA site can be populated with one of two FPGAs to match the specific requirements of the processing task. Supported FPGAs are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the received signals. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 installs the P14 PMC connector with 24 pairs of LVDS to match the specific requirements of external custom I/O connections to the FPGA. Option -105 installs the P16 XMC connector with one 8X or two 4X gigabit links to the FPGA to support serial protocols.

Pentek

http://www.pentek.com/go/sigproc71791





ĄĄ

Two 500 MHz 12-bit A/Ds digitize IF or I+Q signals synchronously

Clock/sync bus for multimodule synchronization • VITA 42.0 XMC compatible with switched fabric interfaces • Optional user-configurable gigabit serial interface • Optional LVDS connections to the Virtex-7 FPGA for custom I/O VITA 42.0 XMC compatible with switched fabric interfaces signal-processing.mil-embedded.com/p373647

sales@pentek.com www.linkedin.com/company/pentek

22 | Signal Processing Design Resource Guide Fall 2016

 201-818-5900 www.twitter.com/pentekinc



www.signal-processing.mil-embedded.com

FEATURES

Open Project Builder Open Project Builder™ is an innovative FPGA application development tool that simplifies and speeds programming, providing a remarkably short and efficient programming experience.

ĄĄ

Board Support for latest Altera & Xilinx FPGAs

ĄĄ

Works from High Level, Data Flow Concept

ĄĄ

Intelligent Wizard for HDL Users

ĄĄ

GUI Design Entry and Debug Tools

ĄĄ

Tested & Optimized Open Project Builder IP Cores

ĄĄ

Modules Automatically Handle Synchronization

ĄĄ

Supports Multiple Data Types

ĄĄ

Integrates with Matlab™ Simulation Flow

ĄĄ

Standard Avalon and AXI IP interfaces

Open Project Builder users have the capability to use FPGA IP from any source, such as VHDL, HighLevel Synthesis (HLS), Verilog, or other HDL. Open Project Builder can also port IP to/from other platforms. It uses standard Avalon and AXI IP interfaces. Open Project Builder provides fast portability of applications between Altera and Xilinx and to newer FPGA families.

signal-processing.mil-embedded.com/p373350

Annapolis Micro Systems, Inc. www.annapmicro.com

www.signal-processing.mil-embedded.com

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Signal Processing Design Resource Guide Fall 2016 |

Signal Processing Design Resource Guide

Operating Systems and Tools

Got Tough Software Radio Design Challenges?

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Pentek, Inc., One Park Way, Upper Saddle River, NJ 07458 • Phone: 201.818.5900 • Fax: 201.818.5904 • e-mail:info@pentek.com • www.pentek.com Worldwide Distribution & Support, Copyright © 2013 Pentek, Inc. Pentek, Onyx, ReadyFlow, GateFlow & GateXpress are trademarks of Pentek, Inc. Other trademarks are properties of their respective owners.