VITA Technologies Winter 2017 with Application Guide

p. 5 Editor's Foreword Cybersecurity insecurity

c:J

@VitaTechnology

p. 10

WINTER 2017

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Business barometer

2018 Trend predictions

VOLUME 35

NUMBER 2

SECURING EMBEDDED SYSTEMS BASED ON OPEN SYSTEM ARCHITECTURES

p.14

ANNAPOLIS MICRO SYSTEMS LOW-LATENCY AND HIGH-BANDWIDTH MEZZANINE CARDS p.28

+ MANAGING THE MANY 1/0 OPTIONS OF VPX p.20

Advertiser Index Page Advertiser

Alphi Technology Corp. – Mission critical I/O solutions 1 Annapolis Micro Systems, Inc. – Low-latency and high-bandwidth mezzanine cards 32 Annapolis Micro Systems, Inc. – Keep your FPGA System integration on target and above water 3 Behlman Electronics – When it comes to VPX, one company has the most flavors 11 Dawn VME Products, Inc. – Dawn powers VPX 27 Elma Electronic – Elma’s VPX CMOSS backplane 26 Embedded World – Discover innovations 8 Interface Concept – High-end processing platforms 17 Themis Computer – Reliable composable computing 13 Vector Electronics & Technology, Inc. – VME/ VXS/ cPCI chassis, backplanes & accessories 12 VEROTEC Electronics Packaging – Verotec Integrated Packaging 18 VITA – How will YOU shape critical and intelligent embedding computing?

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EDITORIAL DIRECTOR Jerry Gipper jgipper@opensystemsmedia.com

GROUP EDITORIAL DIRECTOR John McHale jmchale@opensystemsmedia.com

TECHNOLOGY EDITOR Mariana Iriarte miriarte@opensystemsmedia.com

DIRECTOR OF E-CAST LEAD GENERATION AND AUDIENCE ENGAGEMENT Joy Gilmore jgilmore@opensystemsmedia.com

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ECASTS Latest Trends in Embedded Tools, Frameworks, and Systems for Effective Development November 16, 2017 11:00 AM EST http://ecast.opensystemsmedia.com/773

Processing for Radar and Electronic Painlessly Add a Graphic HMI November 16, 2017 2:00 PM EST http://ecast.opensystemsmedia.com/775

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2 | VITA Technologies Application Guide Winter 2017

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When it comes to VPX, one company has the most flavorS

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WINTER 2017 | VOLUME 35 | NUMBER 2

@VitaTechnology

On the cover The VITA Technologies 2018 Application Guide showcases technologies based on VITA standards, including FMC, OpenVPX, XMC/PMC, and related rugged boards, systems, and components. Featured on the cover: Annapolis Micro Systems’ Low-Latency & High-Bandwidth Mezzanine Cards.

Business barometer: 2018 trend predictions »» p. 10

By Jerry Gipper, Editorial Director

FEATURES

10 Special Feature

Jerry Gipper

Business barometer: 2018 trend predictions

14 Technology Features Securing embedded systems based on Open System Architectures

By Jerry Gipper

Managing the infinite possibilities: How to cope with the many I/O options of VPX

By Ken Brown, LCR Embedded Systems

Solving the OpenVPX multi-gigabit I/O Problem

By K. Braund and B. Sullivan, Meritec

Securing embedded systems based on Open System Architectures »» p. 14

By Jerry Gipper, Editorial Director

DEPARTMENTS

5 Editor’s Foreword

Jerry Gipper

Cybersecurity insecurity

6 VITA Standards Update

Jerry Gipper

VITA Standards Organization activity updates

8 Defining Standards

By Mike Southworth, Curtiss-Wright Defense Solutions

Intel’s Xeon-D 10 Gig connectivity drives demand for VITA 76 connector high-speed signal integrity

28 VITA Technologies Application Guide Solving the OpenVPX multi-gigabit I/O Problem »» p. 24

FMC

By K. Braund and B. Sullivan, Meritec

OpenVPX PMC/XMC VME VPX

All registered brands and trademarks within VITA Technologies magazine are the property of their respective owners. ™VPX and its logo is a registered product/trademark of VITA. © 2017 OpenSystems Media © 2017 VITA Technologies enviroink.indd 1

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Editor’s Foreword

By Jerry Gipper, Editorial Director @VitaTechnology

jgipper@opensystemsmedia.com

Cybersecurity insecurity I had a chance to attend an IEEE cybersecurity presentation recently and left wanting to ditch all my computers and smartphones to move into the deep woods as far off the grid as possible.

The presentation included very highlevel demonstrations of several common methods that attackers use to gain access to your PC or smartphone.

Readily available hardware and software were used to illustrate how easy it is for someone to gain unauthorized access.

Within a matter of seconds, a cyber attacker can monitor your every keystroke during a public hotspot session.

To top that, allow them physical access to one of your devices and they can inject a worm in two to three seconds, which gives them complete remote access to your device and anything that it connects to in your personal or business environment.

intervention, never leaving your laptop unlocked and unattended – anywhere, applying updates as they are released, installing a VPN, and using sound password practices raises the access high bar a bit. But true security is very elusive and very difficult on a general-purpose computer system such as a PC that is designed for multiple functions.

The presenters were cybersecurity consultants that work with their clients to seek out vulnerabilities in their company networks. They pointed out that cybersecurity often starts out by conducting some basic penetration testing. Having penetration testers examine your computer networks can provide a comprehensive and prioritized view of what should be done to best protect them from the growing number of cyberthreats. Once penetration testing has exposed the gaps in security, the testers can make recommendations on how to close them.

Many embedded applications have a Windows/PC portal that makes a soft entry point to the massive amounts of data on the inside and access to control functions. These portals usually depend on the same PC caliber of cybersecurity available to you and me.

Their demonstrations were on a common Windows 10-based PC with out-of-thebox protection, which isn’t much. A Windows PC is the most open system architecture possible, making it the prime target for attacks. Fortunately, there are basic steps that one can take to minimize the risk. Things like setting your Wi-Fi connection to require manual www.vita-technologies.com

In the world of embedded computing, the motivation for accessing most devices is much lower than going through the files on your laptop or smartphone. The fact that most industrial devices are behind reasonable firewalls, that they use less scrutinized real-time operating systems, and are dedicated to specific tasks makes them a bit more resistant to attack. However, that does not mean that these devices are not a target. Sometimes the reward for attackers is much greater.

HAVING PENETRATION TESTERS EXAMINE YOUR COMPUTER NETWORKS CAN PROVIDE A COMPREHENSIVE AND PRIORITIZED VIEW OF WHAT SHOULD BE DONE TO BEST PROTECT THEM FROM THE GROWING NUMBER OF CYBERTHREATS. ONCE PENETRATION TESTING HAS EXPOSED THE GAPS IN SECURITY, THE TESTERS CAN MAKE RECOMMENDATIONS ON HOW TO CLOSE THEM.

While what we see in the movies with cyberattacks may not be possible to the degree glorified by Hollywood, you can rest assured that somewhere, someone is going to work every day, in a nice office, searching for ways to attack computer systems around the world. The threat is real, and it is only getting worse.

To illustrate just how critical cybersecurity is, the Department of Defense (DoD) formed the U.S. Cyber Command, charged with three missions: defend the Defense Department’s networks and systems, provide offensive support to other commands in the event of a contingency, and defend the nation from a cyberattack of significant consequence (less than two percent of incidents would qualify as “significant”). While the issue of who should “manage” Cyber Command is ongoing in the DoD, work is underway to address the cybersecurity of our nation.

Our industry is affected by the fact that many of you are designing, building, and using open standard architecture in embedded computing systems that are susceptible to cyberattacks. In the feature, “Securing Embedded Systems Based on Open System Architectures,” I touch on high level concerns and challenges facing designers using Open System Architectures such as VITA technology modules.

In the meantime, keep your devices up-to-date and secure, you never know when you might become a victim.

VITA Technologies Application Guide Winter 2017 |

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VITA Standards Update

By Jerry Gipper jgipper@opensystemsmedia.com

VITA Standards Organization activity updates The November VITA standards meeting was held in Miramar Beach, Florida. This update is based on the results of that meeting. Contact VITA if you are interested in participating in any of these working groups. Visit the VITA website (http://www.vita.com) for details on upcoming VITA Standards Organization (VSO) meetings.

ANSI accreditation Accredited as an American National Standards Institute (ANSI) developer and a submitter of Industry Trade Agreements to the IEC, VITA provides its members with the ability to develop and promote open technology standards.

The working groups meet face-to-face every two months to address embedded bus and board industry standards issues.

VSO study and working group activities Standards within VITA may be initiated through the formation of a study group and developed by a working group. A study group requires the sponsorship of one VITA member, and a working group requires sponsorship of at least three VITA members.

Status: The baseline VPX standard is coming up for its five-year review. The working group is working to align it with recent work on VITA 65, VITA 66, and VITA 67.

Interested parties should contact VITA to participate in the working group.

ANSI/VITA 46.9: VPX: PMC/XMC Rear I/O Fabric Signal Mapping on 3U and 6U VPX Modules Objective: This standard defines PMC or XMC mezzanine rear I/O pin mappings to VITA 46.0 plug-in module backplane connectors.

Status: Various updates and additions have been added for anticipated use in VPX profiles. A recirculation ballot is scheduled to approve changes made during the first ballot.

ANSI/VITA 47: Environments, Design and Construction, Safety, and Quality for Plug-in Units Objective: Supplying vendors’ certification of COTS plug-in units to this standard will facilitate the cost-effective integration of these items into larger systems.

Work in progress

Status: ANSI/VITA 47-2005 (R2007) has been opened for revision to improve interoperability, create less reliance on individual supplier ruggedization guidelines, and make sure environments are concurrent with recent VPX updates. The working group is nearing completion of reviewing comments on the revisions and additions.

Participation is encouraged.

Several working groups have current projects underway; the following roundup summarizes those projects:

VITA 48.4: VPX REDI: Mechanical Specification Using Liquid Flow Through (LFT) Applied to VPX Objective: This standard will establish the mechanical design requirements for an ­LFT-cooled electronic VPX module.

VITA 17.3: Serial Front Panel Data Port (sFPDP) Gen 3.0 Objective: The VITA 17.3 standard defines a serial connection intended for use on front panels of modules. VITA 17.3 enhances the existing ANSI/VITA 17.1 standard by adding support for higher bandwidth protocols.

Status: A draft document has been completed and is under review by the working group.

ANSI/VITA 46.0: VPX: Baseline Standard Objective: The VITA 46 base standard defines physical features that enable high-speed communication in a compliant system.

Status: The working group is reviewing and resolving comments. Vibration testing has been completed. Work on the draft document is near completion.

VITA 48.8: VPX REDI: Mechanical Standard for 3U, 6U Air Flow Through (AFT) Cooling Objective: This document defines an AFT standard using VPX connectors without the need for retainers, using jackscrews instead of levers.

Status: ANSI/VITA 48.8-2017 VPX REDI: Mechanical Standard for 3U, 6U Air Flow Through (AFT) Cooling has been ratified by ANSI. The standard is available for download by VITA members and is posted at the VITA Store for purchase by non-members.

VITA 49.2: VITA Radio Transport (VRT) Standard for Electromagnetic Spectrum: Signals and Applications Objective: The VRT standard defines a transport-layer protocol designed to promote interoperability between radio frequency receivers and signal-processing equipment in a wide range of applications. The VRT protocol provides a variety of formatting options allowing the transport layer to be optimized for each application. The VITA 49.2 standard specifies the rules governing control packets.

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Status: ANSI/VITA 49.2-2017 VITA Radio Transport (VRT) Standard for Electromagnetic Spectrum: Signals and Applications Standard has been ratified by ANSI. The standard is available for download by VITA members and is posted at the VITA Store for purchase by non-members.

Status: The working group has approved this specification and has submitted for ANSI ballot. Several additional dot specifications have been introduced to expand the capability of VNX.

VITA 51.4: Reliability Component Derating Objective: The goal of this study group is to develop a new component derating standard.

Status: The study has been meeting to discuss the scope and outline potential sources of data for this activity.

VITA 57.4: FMC+ Objective: The goal is to develop a next-generation standard implementing a set of connectors to support higher-speed serial interfaces.

Status: The draft standard is under review by the working group. Recent work has added support for IPMI, conduction cooling, and addressed several mechanical clearance and mating compatibility issues. A new study group has been formed, VITA 57.5 Physical Tools to Aid in FMC+ Development, to define a set of development tools.

Interested parties are invited to join this study group.

VITA 78.1: SpaceVPX Lite Systems Objective: This document leverages the work done on ANSI/VITA 78 to create a specification with an emphasis on 3U module implementations. The most significant change from SpaceVPX is to shift the distribution of utility signals from the SpaceUM to the System Controller to allow a radial distribution of supply power to up to eight payload modules.

Status: The working group has developed a draft document of the specification that is currently under review.

VITA 84: Hardware Open System Technology (HOST) Study Group

ANSI/VITA 65: OpenVPX Architectural Framework for VPX Objective: The OpenVPX architectural framework specification is a living document that is regularly updated with new profile information and corrections. Added in this release is ANSI/VITA 65.1-2017 OpenVPX System Standard – Profile Tables that ­documents slot, backplane, and module profiles used in OpenVPX. Status: ANSI/VITA 65.0-2017 OpenVPX Systems Standard and ANSI/VITA 65.1-2017 Profile Tables have been ratified by ANSI. The standard is available for download by VITA members and is posted at the VITA Store for purchase by non-members.

Objective: The vision of this study group is to create a hardware technical reference framework for developing embedded computing systems through successful development of an overarching HOST strategy to maximize platform and system “openness,” modularity, interoperability, scalability, sustainability, and re-use.

VITA 66.5: VPX: Optical Interconnect, Spring-Loaded Contact on Backplane Objective: This document describes an open standard for configuration and interconnect within the structure of VITA 66.0 enabling an interface compatible with VITA 46 containing blind mate optical connectors with fixed contacts on the Plug-In Module and floating displacement on the backplane.

VITA 86: High Voltage Input Sealed Connector Power Supply

Status: The working group is developing the draft document.

VITA 67.3: VPX: Coaxial Interconnect, 6U, Four Position SMPM Configuration Objective: This specification details the configuration and interconnect within the structure of VITA 67.0, enabling a 6U VPX interface containing multi-position blind mate analog connectors with up to four SMPM contacts.

Status: The document has been submitted for ANSI ballot.

VITA 68.2: VPX: Compliance Channel Objective: This standard defines a VPX compliance channel including common backplane performance criteria required to support multiple fabric types across a range of defined baud rates. This allows backplane developers to design a backplane that supports required Bit Error Rates (BER) for multiple fabric types. This also allows module developers to design plug-in modules that are interoperable with other modules when used with a compliant backplane.

Status: The working group is updating the draft of this standard.

VITA 74: VNX Objective: VNX describes a rugged small form factor subsystem intended to be rugged for deployed environments. www.vita-technologies.com

Status: The HOST study group is actively reviewing the draft document and reviewing comments.

Objective: This standard defines an environmentally enhanced connector pair, which is compatible with the pinouts as defined in VITA 62.0 for power supplies operating in harsh environments operating off of a high voltage input (270VDC). The connector pair features wider separation between input pins and a sealed connection.

Status: The working group is collecting inputs before developing a draft document.

Copies of all standards reaching ANSI recognition are available from the VITA online store (www.shop.vita.com). For a more complete list of VITA standards and their status, go to www.vita.com/ Standards.

VITA Technologies Application Guide Winter 2017 |

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Defining Standards

By Mike Southworth, Curtiss-Wright Defense Solutions

Intel’s Xeon-D 10 Gig connectivity drives demand for VITA 76 connector high-speed signal integrity The recent introduction of Intel’s first Xeon System-on-a-Chip (SoC) device, the Xeon-D (codenamed “Broadwell DE”), dramatically changes the range of options for designers of high-performance small-formfactor (SFF) mission computers. Compared to earlier Core/Atom devices, the Xeon-D provides more cores and threads per central processing unit (CPU) – up to 16 cores/32 threads – and adds a significantly greater number of Peripheral Component Interconnect Express (PCIe) lanes (32 PCIe lanes for Xeon-D, compared to 16 lanes for Core i7 or six lanes max for Atom). The Xeon-D also natively provides support for a large number of fast USB 3.0, USB 2.0, 1 Gigabit Ethernet (GigE), and serial interfaces. Most notably, a significant leap forward for designers of modern mission computers is Xeon-D’s support for 10 GigE. Thanks to this extensive and unprecedented range of built-in high-speed inter­faces, the Xeon-D architecture is helping to drive a new era of serverclass SFF processing that provides system designers with far more total throughput and a greater number of high-speed channels for connectivity to more and more devices. Add to this Xeon-D’s low power consumption and extended temperature capabilities, and system designers can now deploy size, weight, and power (SWaP)-optimized rugged systems that bring server-class processing architectures to demanding vehicle and aircraft environments.

Higher data rates raise signal integrity issues The faster data rate speeds of 10 GigE and similar interfaces bring with them issues related to signal integrity. The industry-standard MIL-DTL-38999 circular connector, the long preferred rugged I/O connector for deployed aerospace and defense subsystems (such as ATR [Air Transport Rack] boxes), uses pin and socket contacts that aren’t adequate for ensuring exceptional signal integrity for high speed interconnects over maximum cable length on SWaP-constrained ground, airborne, and shipboard platforms. The faster the signal and longer the cable, the greater the resulting signal degradation is. Many critical aerospace and defense applications simply can’t accept such signal loss, distortion, or cable length

limitations. Consequently, in order to support the higher data rates from modern high performance processors, including the Intel Xeon-D, an alternative to traditional pin and socket 38999 connectors is required.

range of 100 meter (330 ft.). In this case, VITA 76.0 connectors have been successfully validated to support the full rated cable length of the 10GBASE-T standard, whereas traditional 38999 pin and socket inserts can support a mere few feet of cabling.

The VITA 76.0 connector With the emergence of a new class of processors that natively support higher bandwidth interfaces, such as 10 GigE, USB [Universal Serial Bus] 3.0, PCI Express and SATA [Serial ATA] 3.0, demand has grown for a circular military grade connector that is able to support the higher data rates. In response to this requirement, VITA adopted the VITA 76.0 standard (“High Performance Cable – Ruggedized 10 Gbaud Bulkhead Connector for Cu and AOC Cables”) in 2015 to define a new 38999-style connector, one that marries a high-density, high-bandwidth mini-­interconnect scheme and fits within the trusted MIL-DTL-38999 circular shell. The VITA 76.0 connector was born out of the need to address signal integrity, and high density interface issues, while bringing forward the benefits of the standard threaded-coupling 38999 circular shell.

To illustrate just how practical the VITA 76.0 is, let’s take 10GBASE-T standard (IEEE 802.3an-2006) as an example, which supports 10 Gb/s [Gigabits/second] connections over unshielded or shielded twisted pair cables over CAT 6A or CAT 7 twisted pair with a maximum specified

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Prior to VITA 76.0, system designers who needed improved signal integrity to support high-speed signals, but also wanted to retain the traditional 38999 circular connector style, would typically use Quadrax connector inserts.This legacy option, though, came with greater size, weight, power and cost per contact.

The tradeoff meant that in exchange for increased bandwidth capability Quadrax connectors offered reduced pin count and pin density.

The VITA 76.0 connector delivers the same ruggedization and environmental ratings as the traditional D38999 series III (IP67; 175 degrees C; 500 mating cycles; 500 hour salt spray, etc.), but embeds a “Hermi” contact system within a Quali­f ied Production Listed (QPL) D38999 series III shellwork (See Figure 1 for VITA 46 reference). The new contact design, pioneered and first commercialized by Meritec, differs from traditional pin and socket designs in that it uses a flat hermaphroditic contact interface that is identical in both the cable plug and the receptacle. When mated, the flat mating surface provides two points of contact. This approach enables www.vita-technologies.com

FIGURE 1

VITA 46 connector

VITA 76.0 to leverage standard, qualified circular shells, and provides designers with the flexibility to use readily available market-standard backshells and accessories with which they are already familiar.

The VITA 76.0 connector supports up to 145 total contacts, 44 differential pairs, and has special shielding for maximum EMI/RFI [Electromagnetic interference/ radio-frequency interference] protection.

The connector is optimized for use with 10 GbE copper interfaces. Now that industrial-temperature rated 10GBASE-T Ethernet transceivers are available, 10 GbE capable systems are expected to proliferate in deployed applications that have historically been dominated by optical architectures. What’s more, since VITA 76.0 also supports coaxial interconnect requirements, the new connectors will also be utilized in video and radio-frequency (RF) applications.

its XMC [Switched Mezzanine Card] and mini-PCIe sites for mission-specific avionics/vetronics payload interfaces.

This modularity and scalability enables mission-tailored capabilities for Command, Control, Communications, Com­ puters, Intelligence, Surveillance and Reconnais­sance (C4ISR) command and control, image processing, surveillance, virtual machine hypervisor, datacenter server processing and network functional virtualization (NFV) applications in harsh deployed environments.

In the quest to deliver more processing power for embedded applications, without saddling systems with unwieldy size or weight, the recent advent of Intel’s Xeon-D SoC opens up new avenues for designers of small form factor mission computers. With its greater complement of PCIe and Ethernet interfaces, the Xeon-D SoC enables system architects to take full advantage of the device’s server-class performance while leveraging open standard I/O add-on modules, such as mini-PCIe and XMC mezzanine cards to expand functionality without increasing SWaP burden.

FIGURE 2

DuraCOR-XD1500

The server-class performance of the Xeon-D SoC combined with the signal integrity of VITA 76.0 interconnects offers great architectural advantages for system integrators of the latest rugged COTS SFF modular mission computers. True 10 GigE data rates can now be supported in a small footprint, affordably and reliably, while leveraging the rugged characteristics of these new technologies for deployed military and aerospace platforms.

[Editor’s note: See “Advances in MIL-D-38999L connectors lead to smaller, lighter, and greater bandwidth” by Ken Braund, Business Development Manager, Meritec in the 2017 Spring issue of VITA Technologies.] For more information, visit http://bit.ly/2A4gPSf.

Curtiss-Wright Defense Solutions www.curtisswrightds.com

High-end processing platforms

The Parvus DuraCOR XD1500 and VITA 76.0 An example of a rugged mission computer that takes advantage of the higher signal integrity of VITA 76.0 connectors to support 10 GbE is Curtiss-Wright’s recently introduced Parvus DuraCOR XD1500 SFF modular mission computer (Figure 2). It takes advantage of the 100 ohm impedance-matched VITA 76.0 connector to ensure the superior signal integrity of its multiple, high-speed 10 GbE, USB 3.0 and other I/O interfaces. This rugged commercial-off-theshelf (COTS) system was designed to deliver ultra-rugged mission computer capabilities in the smallest, lightest envelope possible. It features a 12-core Xeon-class floating-point processing supported with up to 128 GB of RAM. It also provides 150+ spare pins for add-on expansion I/O functionality from www.vita-technologies.com

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VITA Technologies Application Guide Winter 2017 |

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SPECIAL FEATURE

Business Barometer

Business barometer: 2018 trend predictions

By Jerry Gipper

Last fall we were in the middle of a presidential election, not sure of the outcome. Now we know!

I was contemplating a move to Australia, but I am still here – with my options open! I was reviewing my past predictions in preparation for this year’s forecasts. It was a bit humbling as I realized how slowly technology evolves in many aspects. Watching consumer gadgets roll out every year gives one the impression that our advancements in computing technology are moving quickly but then one realizes that things do not move at the same pace in critical embedded computing.

Review of 2017 predictions After nearly a year of experience with the Trump administration, we still don’t know what to expect! They have pushed NATO nations to deliver on their share of defense spending, while the U.S. budget has remained essentially unchanged.

The FMC+ standard did not quite make the finish line in early 2017 as predicated but work is wrapping up after a restart by the working group.

Intel blasted through two generations of their desktop processors and research continues non-von Neumann architecture processors. Google just made 1,000 of their Tensor Processing Units (TPUs) available for developers of machine learning software. Qualcomm’s tender offer for NXP Semiconductors’ shares has been extended through the end of October.

Cybersecurity continues to rise in urgency as announcements of major data breeches continue to fill our headlines.

But, trends in our space unfold relatively slowly so let’s look at additional trends to watch for in 2018.

Bespoke processors We talk a lot about new features that are added to processors with every generation, but in reality, processors are way overdesigned for most applications. Processor designers try to make the processor as robust and flexible as possible, something that is increasingly easier to do as transistor density exponentially increases. However, most applications leave vast processor resources untouched. I/O features are left unconnected, and scores of cores go totally unused. Mostly a challenge for low-end, low-power microcontrollers that need to operate in minimum power modes, there is a set of applications that face the same challenges using higher end processors.

Research is underway on tools that allow users to analyze just how much of a processor is being utilized in each application. Other research is looking at how processors can be optimized for specific applications. Most board designers in our space use fieldprogrammable gate arrays (FPGAs) in this fashion but imaging the savings in power that could be achieved if millions of unused gates were removed?

Server processors At the same time research is underway to eliminate unused gates, we see server class processors from Intel that are being assigned duty in embedded applications.

For years, single board computer (SBCs) using Intel Architecture processors had to select from a limited set of desktop processor, often limiting key performance characteristics. Now designers of embedded systems can select from higher performance

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SPECIAL FEATURE

You can also be assured that the current options of PCI Express and Serial RapidIO are not standing still.

3-D touch panels Touch panels are used in countless applications. Their performance, precision, and reliability has improved substantially, in part driven by their wide use in consumer devices from watches and smartphones to tablets and laptops. These devices are primarily 2-D with some beginning to respond to varying degrees of pressure as well.

New developments are adding sensors that can also measure distance from the ­surface, opening a new round of panels that can detect hand movements above the surface.

Using ultrasound sensors, they can track hand positions allowing users to adjust settings by raising and lowering their hand. This type of technology has been available

Dawn Powers VPX Dawn’s PSC-6238 VITA 62 compliant 3U VPX Power Supply for conduction cooled systems is designed to operate in a military environment over a wide range of temperatures at high power levels. Up to 800 Watts available power.

server-class processors. More I/O, more cores, more PCIe lanes, all contribute to a lower chip count that leads to reduced overall power requirements for the SBC meaning that they can be used in more rugged environments that are power constrained.

Processor interconnects Things on the processor interconnect front have been quiet for the past several years. Historically the switched serial fabrics that have been used in onboard processor architectures have made their way onto the backplane. PCI Express and Serial RapidIO are classic examples.

Three new bus/interconnect standards for processor to accelerators were introduced in 2016.

Cache Coherent Interconnect for Accel­er­ators (CCIX), Gen-Z, and Open Coherent Accelerator Processor Interface (OpenCAPI) are all interconnects that are addressing similar problems focused on tighter coupling between processors and accelerators (GPUs, FPGAs, etc.) and emerging memory/storage technologies utilizing 25 Gps and faster speeds.

Each approach is different, and each has a strong list of supporters involved with their respective consortia. A possible shake out or convergence is very likely. www.vita-technologies.com

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Business Barometer

SPECIAL FEATURE

for several years in larger gaming s­ ystems such as the Wi, but now they can be embedded in small handheld devices.

This trend opens a new “dimension” for man-machine interfaces.

the right solution, instead consider how the function is being implemented, how does it provide what an attacker desires.

Technology will continue improving, but the real need is for designers to think like the attackers.

Cybersecurity Security has been an issue for many years. Its importance gets higher with each passing year as more of our lives are connected and recorded in cyberspace. Technology continues to improve giving designers more options to choose from. But what really needs to change is the thinking that goes into a design from the very start. With the potential for every electronic device to be connected to the internet, thus making it vulnerable, designers need to think more like the cybercriminals. Look at products from the standpoint of the attacker, and consider how the attacker could benefit from design decisions. Understanding the motivation behind an attack can lead to better security protection. Layering on more security measures may not be

Open System Architectures Increased complexity of the electronics systems in large defense platforms has inspired several Open System Architecture (OSA) initiatives to step up their game.

The Department of Defense does not provide a standardized open architecture framework for common embedded system services forcing programs to look to the commercial world for solutions. Many of the military branches have initiatives underway espousing the module interoperability, maintainability, openness, usability, and reliability virtues of an OSA. These initiatives are utilizing several different open system architectures for board and system form factors; the programs see many different approaches as appropriate (not conflicting),

as there is no “one architecture to rule them all.”

Numerous OSA-related initiatives have active working groups meeting to discuss, develop, and implement strategies. I have observed that the level of cooperation has increased, and I expect we will see results in 2018. The industry is evolving to better utilize the resources that are available. The real challenge will be the speed of adoption. If it takes too long to gain consensus, many initiatives will lag too far behind the technology to reap any rewards. They technologies they zero in on may be obsolete by the time they get to any programs. Working together doesn’t solve the speed of technology to market issues.

Opportunity abounds for 2018, with the world-wide economy expected to strengthen. 2018 should be a good year for VITA technologies. However, I am still leaving my Australia options open!

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TECHNOLOGY FEATURE

Open System Architectures

Securing embedded systems based on Open System Architectures

By Jerry Gipper

C

Many of the standards developed by VITA working groups are for defining modules that are part of Open System Architectures (OSA) – whether they are VME, VPX, PMC, FMC or one of many other standards. These modules are used to build critical embedded systems that are deployed in a variety of application platforms. Today these platforms are typically connected via a network, a network that is often susceptible to cyberattacks. This article introduces you to high level concerns and challenges facing designers using Open System Architecture (OSA) modules.

omputer technology has evolved to increasingly complex levels making it more difficult each day to develop next generation products. Advances in hardware and software make it possible to develop systems that are highly capable and complex and getting more so with each iteration. They also face increasing scale, computation, and security challenges that can quickly overwhelm a project.

into legacy systems. The ecosystem of module suppliers creates a competitive marketplace that reduces program costs and spreads risk. Because OSAs use nonproprietary system architectural standards in which various payloads can be shared among various platforms, technology upgrades are easy to access and implement.

Use of OSA modules based on popular industry standards, for both hardware and software, is a common method to address these challenges. OSA modules reduce the cycle time needed to develop new systems and insert new technology

In past years, protecting real-time, embedded systems was a lower priority as each system was very isolated, but now, security is of paramount importance in embedded computing systems. These systems are becoming more intelligent and connected via wireless networks that are especially vulnerable. Combine that with the fact that major initiatives across multiple industries from telecommunications to defense are using OSA solutions to develop their next generation of platform raises concerns about

However, adding security to an OSA could interfere with its ‘openness.’ As most current security approaches are ad hoc, proprietary, and expensive they are incompatible with OSA principles, especially when each platform developer individually implements and manages the platform security. Therefore, developing a system-level secure embedded system architecture that will seamlessly work with various OSA components is a challenge.

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www.vita-technologies.com

TECHNOLOGY FEATURE

Application and Mission Requirements Functional Requirements

Threat Analysis

System Design

Security Requirements

Performance Evaluation

Security Evaluation

System Implementation

Security Implementation

Test and Evaluation the security capability of OSA modules (Figure 1).

What is an Open System Architecture?

An OSA is any system (or software) architecture that exhibits the following three beneficial characteristics: 1. It is modular, being decomposed into architectural components that are cohesive, loosely coupled with other components (and external systems), and encapsulate (hide) their implementations behind visible interfaces.

2. Its key interfaces between architectural components conform to open interface standards (that is, consensus based, widely used, and easily available to potential users).

3. Its key interfaces have been verified to conform to the associated open interface standards.1 Two of the most important benefits are to increase competition among developers of the architectural components and to avoid single sourcing when it comes to acquiring and updating these components. www.vita-technologies.com

FIGURE 1

In an ideal secure embedded system design process, functionality (blue) and security (gold) are co-designed, yet they are appropriately decoupled during testing so that security does not interfere with functionality. This co-design is often difficult to achieve because functionality and security are two very different disciplines.

The definition does not state that all interfaces must conform to open interface standards, but rather only key interfaces must be open. Moreover, if one examines actual system architectures, one quickly learns that openness is not black and white but rather a matter of degree. Some interfaces are highly open (i.e., they conform to widely used international standards), some interfaces are relatively open (i.e., they conform to less-widely used, more application-domain-specific standards or widely used de facto standards), some interfaces are slightly open (i.e., they conform to product-line-specific conventions), and some interfaces are essentially closed (i.e., they are system-unique or conform to contractor-proprietary “standards”).

Common OSA interfaces There are countless standards that define hardware interfaces for OSAs ranging from highly open to application specific openness. USB, SATA, Display Port, HDMI, DVI, Ethernet, RS232/422/485 and many, many more. Others define system, board, and software architectures, standards such as the VITA VPX family, PICMG’s Advanced Mezzanine Card, and numerous small form factors for boards and Linux for open software.

Challenges in securing embedded systems Security has an asymmetric nature—an attacker can compromise a system by discovering a single, unexpected vulnerability, while a defender must defend against all vulnerabilities. Because it is impossible to correctly predict every future attack, securing an embedded system to prevent attacks is not a guarantee of a secure platform.

An embedded system provides very little, if any, allowance for security, especially for size, weight and power (SWaP) considerations; thus, security must not impose excessive overhead on the protected system. Security technologies must be compatible with VITA Technologies Application Guide Winter 2017 |

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Open System Architectures

TECHNOLOGY FEATURE

embedded systems that use commercialoff-the-shelf (COTS) processor hardware platforms that are common to OSAs. Computer security threats can be divided into four categories, according to whether they threaten confidentiality, integrity, usability, or availability. Breaking security into these elements makes the evaluation of potential solutions easier and more effective.

Confidentiality is the property that is violated whenever information is disclosed to an unauthorized principal. That may be a person or another computing device, either is relevant. Integrity is violated whenever the information is altered in an unauthorized way. It may be altered at a host or in transit between devices.

Usability is a qualitative analysis of the system’s suitability to a task. A system that is highly secure but incapable of delivering the required functionality is not designed well. Usability metrics evaluate a system’s design by considering the system’s throughput, resilience, portability, upgradability, SWaP, and other similar parameters. Availability is the property of a system, which always honors any legitimate requests by authorized principals. It is violated when an attacker succeeds in denying service to legitimate users, typically by using up all the available resources.

of intrusions becoming more common. The National Institute of Standards and Technology (NIST) provides security guidelines for updating BIOS, the point at which the security threat is the greatest. Through these security guidelines – NIST SP 800-147, NIST is setting standards that require authentication of BIOS upgrade mechanisms.

BIOS providers have taken the security challenge seriously and offer suites of products providing multiple levels of security. They support the latest processor technology, which allows users to manage, inventory, diagnose, and repair their systems in efficient, remote, and streamlined ways all without compromising system security. The BIOS providers support the NIST SP 800-147 guidelines and they offer multiple other security options to protect FLASH and other storage devices. Users prefer to keep as much of the security responsibility at the hardware and BIOS level as possible because that is where the defense is strongest.

Operating system Operating systems play many roles in providing increased levels of security. The most recent advancement became more feasible with the introduction of multicore processors that enable the ability to run multiple instances of operating systems on one multicore processor. This has led to hypervisor architectures that can protect key elements of the software environment (Figure 2). Operating systems must address: ›› Authentication – the process of ensuring that users, devices and software on a network are correctly identified. ›› Authorization – grants users and devices the right to access resources and perform specified actions. ›› Network Access Control – mechanisms that limit access to the network to authenticated and authorized devices, software and users. ›› Confidentiality – using ciphers to transform data to make it unreadable to anyone except those authorized and authenticated to view the data. ›› Integrity – checking mechanisms are designed to detect unauthorized changes to transmitted data through the lifecycle of a device, software and data.

Security is critical from the hardware through the layers of software all the way to the end application. Each is important to ensure the most secure system possible. To manage your risk, you must be sensitive to security threats through the entire system architecture.2

Processors Security starts at the processor. A foundation of root-of-trust must be established to provide security services upon which to build a robust security environment.

Today’s mainstream processors typically include the hooks and features needed to support a robust security strategy.

BIOS The next layer of defense is at the Basic Input/Output System (BIOS) level. Attacks on the BIOS are growing with reports

FIGURE 2

16 | VITA Technologies Application Guide Winter 2017

Typical application illustrates the vulnerable points in a system. www.vita-technologies.com

›› Remote Management – a method to monitor, update and manage remotely manufactured and fielded devices.

Supply chain evolution OSA module suppliers have changed the way they address the challenges of security. In the past it was given little or no thought. Now suppliers have refocused key staff on security, creating and staffing positions such as Secure Processing Solutions or Secure Embedded Solutions that live and breathe the challenge of ensuring that their products can meet the demanding requirements of security.

unachievable. Moreover, openness must be weighed against competing requirements to obtain the best architectural solution.

Getting the balance right between openness and security is going to produce the most secure and cost-effective solutions possible. For those interested in learning much more about computer security and cybersecurity, visit the National Institute of Standards and Technology, NIST website at csrc.nist.gov.

References 1. “Open System Architectures: When and Where to be Closed”, Software Engineering Institute, Carnegie Mellon University, Donald Firesmith, October 19, 2015. Retrieved from: https://insights.sei.cmu.edu/sei_blog/2015/10/open-system-architecture-when-and-whereto-be-closed.html 2. “Secure Embedded Systems,” Lincoln Laboratory Journal, 2016. Retrieved from: https://www.ll.mit.edu/publications/journal/pdf/vol22_no1/22_1_9_Vai.pdf [Editors note: Continue reading more about Open Systems Architectures in sidebar on page 18.]

Others have added whole new business units. Mercury Systems formed its Security Center of Excellence in response to rapidly evolving cyber threats.

Their team of security and systems analysts, as well as cryptography, hardware and software engineers, are dedicated to proactively address the most critical security issues across multiple vertical markets to help their customers create a safer, more secure world. Mercury Systems BuiltSECURE technology starts at the design stages and carries all the way through manufacturing to delivery, ensuring that modules and systems designed and built by Mercury Systems meet the most stringent of security requirements.

The Curtiss-Wright Defense Solutions has a similar program; the TrustedCOTS Program designed to address the protection of critical military technologies and data for their customers.

Ensuring that a system is trustworthy begins with the first instruction on trusted hardware. Attacks on computers and networks continue to proliferate despite extensive software approaches to prevent these attacks. Establishing a strong digital identity for both the user and the computer system through hardware-based security is a significant step beyond software-only strategies.

Although an OSA will almost certainly result in important benefits (especially if openness is maintained through the development and lifecycle), good system/­ s oftware architecture engineering will recognize that 100 percent open system architecture is typically www.vita-technologies.com

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Open System Architectures

TECHNOLOGY FEATURE

ROBOTICS FAMILY LEVERAGES OPEN ARCHITECTURES TO COUNTER ORDNANCE THREATS

By Mariana Iriarte, Technology Editor Designers and engineers are taking advantage of the ability of open architectures and commercial off-the-shelf (COTS) technologies to counter emerging threats quicker by more easily upgrading legacy systems with newer, faster technology. In one such project, a U.S. Navy-sponsored program focuses on a family of robotics that will keep soldiers out of harm’s way.

The U.S. Navy teamed up with John Hopkins University Applied Physics Lab (JHU/APL) and an industry team that includes Northrop Grumman, OpenJAUS, and GuardBot to work on the U.S. Navy’s Advanced Explosive Ordnance Disposal Robotic System (AEODRS) program.

The goal of the program is “to develop modular, open-architecture robotic platforms for use in explosive ordnance disposal across the U.S. Navy,” says Danny Kent, Ph.D., president and cofounder of OpenJAUS. “By utilizing an open architecture, components and modules can be reused across the family of systems. In addition, future technologies and capabilities can rapidly be brought from the research laboratory to the warfighter.”

To that end, the team announced in May 2017 that the AEODRS Increment 1 and Spherical Platform for AEODRS Appliance Research (SPAAR) systems had completed a demonstration for Joint Services EOD Action Officers in Indian Head, Maryland. While Increment 2 and Increment 3 systems are still awaiting award, the U.S. Navy’s AEODRS program aims to be “the Navy’s next-generation, open architecture robotic family of systems,” Kent says.

The program is capitalizing on the open architecture movement, which will help today’s warfighters to fight emerging threats by enabling engineers to quickly adapt new technology to current systems.

JHU – along with the industry team – is taking advantage of the move­ment. As technology that was once considered a figment of the imagination becomes a reality, it is clear that open architectures are readily addressing the Department of Defense (DoD) demand to quickly upgrade and stay ahead of the game.

In the AEODRS case, the program addresses the dangers of explosive ordnance disposal (EOD). “It is comprised of three classes of vehicles, Increment 1, Increment 2, and Increment 3. The Increment 1 Primary System Integrator program has been awarded to Northrop Grumman Corp.,” Kent explains.

Leveraging COTS components and open architectures is a big part of the program, as COTS has helped the military control costs, particularly during its sequestration years. “Using COTS components on government programs such as AEODRS enables the military to leverage the rapid progress being made in the robotics community,” Kent says.

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This is especially essential in the field of robotics: “What is innovative technology today may be obsolete in a matter of years and sometimes months,” he explains. OpenJAUS – a Florida company specializing in middleware solutions for unmanned systems developers – is helping commercial companies adapt their technology to the AEODRS program at a quicker pace, lower cost, and at a reduced risk, Kent adds. “By utilizing OpenJAUS’s commercial JAUS and AEODRS software libraries, companies jumpstart integration into the existing AEODRS architecture.”

Officials consider Increment 1 as the first of a family of open architecture robotic systems designed to be interoperable and having the capability to integrate new technology quickly that will benefit the warfighter.

Kent explains that OpenJAUS’s role in the AEODRS program is “to provide our JAUS [joint architecture for unmanned systems] expertise to JHU/APL and others in the form of architecture analysis and recommendations, software development activities, and general consulting and support. OpenJAUS also provides system integration testing, evaluation, and support to Northrop Grumman as part of its AEODRS Increment 1 project.

Under the program, OpenJAUS supplies software services including “integration of hardware with the program architecture for risk reduction and development of more user-friendly interfaces to tools developed for testing and validation of the AEODRS architecture,” he adds.

Robotic-vehicle maker GuardBot, with support from OpenJAUS, developed the SPAAR system, which enables reconnaissance in harsh environments. Engineers at OpenJAUS integrated the SPAAR architecture with the AEODRS system architecture, according to a statement released by OpenJAUS. The results of this collaboration enabled engineers to integrate and demonstrate a system using “AEODRS Handheld Operator Control Unit (HOCU) and the Multi-Robot Operator Control Unit (MOCU) software application.” (See Figure 1.)

The end result of the SPAAR program demonstrates that technology can be more interoperable and will likely prompt engineers to quickly integrate new technologies into the AEODRS family, both of which will benefit military-sponsored programs.

FIGURE 1 AEODRS Increment 1 system and handheld operator control unit.

Photo courtesy of OpenJAUS.

www.vita-technologies.com

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TECHNOLOGY FEATURE

VITA Technology Applications Uncovered

Managing the infinite possibilities: How to cope with the many I/O options of VPX

By Ken Brown

P

art of the reason for the appeal of 3U VPX in addition to the performance, ruggedness, and SWaP/C advantages, is the high degree of openness of VPX backplanes. System designers have what seems like nearly infinite possibilities for I/O and backplane interconnects, allowing the architecture to fit within an astonishing array of applications in terms of quantity of I/O, speed and signal integrity, flexibility, and the physical path taken by the I/O (copper, RadioFrequency (RF), fiber optics, etc.).

However, these infinite possibilities create infinite choices and decisions, during both the design and upgrade processes. No two customers want the same I/O from their systems, and small changes at the board level can translate into significant backplane and

Thanks to its flexibility, performance, and suitability for harsh and varied environments, VPX – especially the size, weight, and power-cost (SWaP-C)-friendly 3U VPX – has rapidly established itself as the form factor of choice for aerospace and defense programs. The majority of new opportunities are in the 3U VPX VITA 48.2 (conduction cooled) form factor, housed in an ARINC 404 enclosure, commonly called Air Transport Rack (ATR). ATR enclosures are notorious for restrictive I/O limitations.

I/O design changes later on in the design process. In addition to this, upgrades become equally fraught as the flexibility of the architecture can make it difficult to perform simple “drop-in” upgrades without a major redesign, and the popular ARINC 404 chassis form factor severely limits the card cage orientation and backplane access.

Options to manage the flexibility Balancing the I/O possibilities often causes a designer to settle on one of the following options as part of their design process, depending on which of the factors is the most important to the customer: 1. An all-in-one-piece backplane and I/O board connected to one another by means of a monolithic flex assembly; 2. Discrete backplane and I/O board connected to one another by means of a discrete flex assembly; 3. Separate backplane and I/O board connected by means of backplane cables; 4. Separate backplane and I/O board connected by means of a transition board; 5. Rear Transition Module (RTM) options, which are problematic within a spaceconstrained ARINC 404-style enclosure: a. Accessing I/O by means of individual Rear Transition Modules (RTMs); and b. Connecting the I/O board to the cards by means of VPX RTM cables.

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Discrete backplane/flex Since this option (Figure 2) isolates the backplane and the I/O board from one another by means of a flex interconnects, it offers a reduction in signal integrity, but with the benefit of a reduction in cost and a slight increase in flexibility, since an upgrade would only require a redesign of the affected boards. It also offers similar scaling in cost of assembly manufacture as volumes increase, but still requires specialized design and manufacturing capabilities.

Backplane-I/O connections via cabling This option (Figure 3) offers excellent flexibility. It is inexpensive, and upgrades will often require only cable replacement or even simply a re-spinning of the I/O. However, it can be very difficult to match the signal integrity or density of the flexrelated options, and the manual labor required is susceptible to human error and causes costs to increase proportionally as production volumes increase. This option can also require shielding and consume valuable enclosure space.

Each of these options comes with its advantages and disadvantages. Many users in fact prefer to choose a combination solution. However, these are overall the dominant means by which I/O is often pulled from a 3U VPX enclosure, and each one is treated separately in more detail below.

FIGURE 1 Monolithic backplane/flex.

Monolithic backplane/flex In this option (Figure 1), the backplane and I/O board are effectively one unit, connected by a flex segment and manufactured as one assembly. Advantages of this option include exceptional signal density and integrity due to the absence of any interconnects and decreasing costs per unit as the volume of units increases, although it can be costly in low volumes.

This is due to the entire assembly once designed can be manufactured mechanically in a way that does not require manual labor, the cost for which of course scales roughly linearly as volumes increase.

However, a monolithic backplane/flex assembly is also usually expensive and requires specialized design and manufacturing capabilities. Since it consists of one monolithic piece, it is also an inflexible solution and potentially requires complete redevelopment and replacement when any part of the system is upgraded. www.vita-technologies.com

FIGURE 2 Discrete backplane/flex.

FIGURE 3 Backplane cables.

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VITA Technology Applications Uncovered

TECHNOLOGY FEATURE

Backplane-to-I/O transition board Connecting the backplane and I/O board by means of a transition board is one of the options that offers the greatest balance between flexibility and signal integrity, and is implemented frequently (Figure 4). The transition board can support excellent signal integrity, and while it can be expensive in low volumes, assembly costs do not scale as quickly since there is limited manual labor required for assembly.

Perhaps most significantly, the hard mount between the backplane and the I/O board offers excellent ruggedness in addition to the option to include supporting circuitry for functions like filter­ing, circuit protection, or processing.

Tight tolerances are often required.

FIGURE 4 Backplane to I/O transition board.

FIGURE 5 Rear transition modules.

Accessing I/O via rear transition modules While this option (Figure 5) offers good signal integrity and flexibility along with the option to add supporting circuitry,

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PERHAPS MOST SIGNIFICANTLY, THE HARD MOUNT BETWEEN THE BACKPLANE AND THE I/O BOARD OFFERS EXCELLENT RUGGEDNESS IN ADDITION TO THE OPTION TO INCLUDE SUPPORTING CIRCUITRY FOR FUNCTIONS LIKE FILTERING, CIRCUIT PROTECTION, OR PROCESSING.

FIGURE 6 RTM cables.

one that minimizes connection points, as each interconnect degrades the signal.

Hard-mounted products are usually more rugged, but require tight tolerances.

FIGURE 7 Discrete flex and backplane cables.

Lastly, the relative costs of flex assemblies versus cabling to connect backplanes and I/O boards scale differently with production volumes. Flex assemblies are more expensive in low volumes, but require no manual labor and hence their cost per unit goes down with larger volumes.

They are also less error-prone than cable assemblies, which require more manual labor. And while they offer better signal performance, they are also far less flexible when upgrades are required.

FIGURE 8 I/O Transition board and blade cables.

the requirements for an RTM card cage can make this an expensive and challenging option to implement, especially in space-constrained enclosures such as Air Transport Racks, which do not offer RTM access.

Occasionally custom solutions that combine the discussed options are required – implementing a backplane-to-I/O transition board with cabling to individual blades, or implementing a discrete backplane/flex assembly supplemented by backplane cables. (Figure 7 and 8).

Accessing I/O via VPX RTM cables

Clearly, the best option for a given environment or application will depend on many things, including cost, schedule, production volumes, the need for signal integrity, and crucially, accurate prediction of the system’s most likely upgrade paths so that the customer can be left with the best choices in the future for a given design.

In summary, while the I/O options of the popular VPX form factor can be intimidating, we’ve found that the best designs usually fall within one of the above six options, with some room for further customization, and that a careful consideration of the most important factors to the environment and application can provide excellent guidance for anyone trying to pick an optimal path through the present and future of their VPX implementation.

However, there are certain general guidelines that can be used to pick a path through the possible choices. If signal integrity is a concern, the best design may be

Ken Brown is an engineer and project manager at LCR Embedded Systems.

In terms of flexibility, this option (Figure 6) is by far the best, allowing the designer to extract signal from any individual pin on the backplane. However, due to this exceptional flexibility, this option is expensive and usually involves extremely long lead times. The number of cables can also impact signal integrity and offer challenges in cable management in rugged or space-constrained enclosures. As with the previous option, it is often not an option in ATR-style enclosures due to the lack of RTM access.

How to strike a balance: Weighing your choices

www.vita-technologies.com

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TECHNOLOGY FEATURE

VITA Technology Applications Uncovered

Solving the OpenVPX multi-gigabit I/O Problem

By K. Braund and B. Sullivan

T

The success of Meritec’s VPX+ cabling system has spawned a new cabling system that replaces the need for the Multi-Gig (TE TM) connector and it is field deployable. The new VPX+ DA (Direct Attach) cabling system (product currently in development) reduces weight and cost while improving performance. Preliminary VPX+ DA SI simulations are showing 25Gigabits/seconds (Gb/s) performance. The VPX+ DA is an ideal solution for pulling various protocols from slot-to-slot and backplane to I/O at higher speeds.

VPX+ DA is the ideal size, weight, and power (SWaP) solution.

he data rates of serial switched fabric protocols used for OpenVPX slot-to-slot interconnect planes’ have increased from Gen1 (3+ Gbaud) through Gen2 (6+ Gbaud) and now to Gen3 (10+ Gbaud), with Gen4 (16 Gbaud) and Gen5 (25+ Gbaud) just around the corner (Table 1). At the same time some critical types system I/O have transitioned to high speed serial at similar baud rates.

What happens when the multi-gigabit I/O baud rate goes up?

Historically, rugged deployed system units (e.g. ATR boxes) have routed I/O signals using traces on backplanes and I/O panels, but this has become increasingly difficult, as baud rates have increased.

OpenVPX rugged deployed system units often have I/O traces spanning 12 to 18 inches to get from backplane connectors to the external rugged I/O connectors. Because signal traces are very small conductors, IL for these long traces is significant, and it continues increasing as serial I/O baud rates and corresponding signal frequencies go up. For today’s multi-gigabit I/O, these high trace losses can spell disaster!

For high speed serial signaling, the Insertion Loss (IL) at the Nyquist frequency (one-half of the baud rate) is the first thing to look at. Although IL is merely one of several important signal integrity parameters, if we have too much end-end loss in the channel we have already lost the battle because there is virtually nothing left of the original signal! Commonly used OpenVPX Gen3 fabrics’ Nyquist frequencies range from 4.0 GHz to 5.15625 GHz for various protocols, while Gen4 fabrics’ Nyquist frequencies go up, ranging from 6.0 GHz to 8.0 GHz. When the baud rate and Nyquist frequency go up, the corresponding IL increases, so things get a lot worse.

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TECHNOLOGY FEATURE

AT GEN3 SPEEDS, THESE I/O TRACE LOSSES ARE

Solving the multi-gigabit I/O trace loss problem for rugged OpenVPX systems I/O trace losses for today’s multi-gigabit I/O are simply too high, so a lower loss alternative is needed instead of the traces (Figure 1). Fortunately, cables have dramatically lower loss than traces, so a rugged cable solution is an obvious alternative.

Each fabric type has a budget for worstcase channel characteristics, so there is a maximum end-end IL budget at Nyquist for each fabric type and baud rate. Let’s take PCI Express (PCIe) as an example.

At PCIe Gen3 baud rate of 8.0 Gbaud, the channel IL budget at Nyquist (4 GHz) is 22 dB. A typical 12" low loss trace at Nyquist (4 GHz) has an IL of approximately -5 dB, or 23 percent of the total channel budget; 18" traces would consume 50 percent more, or 34 percent of the total channel budget. At Gen3 speeds, these I/O trace losses are large enough to cause serious problems when interconnecting two similar units. A typical 18" low loss cable at Nyquist (4 GHz) has IL of approximately -0.75 dB, or three percent of the total channel budget. This is more like it!

Moving to PCIe Gen4 with a baud rate of 16.0 Gbaud, the channel IL budget at Nyquist (8 GHz) is 23.5 dB. A typical 12" low loss trace at Nyquist (8 GHz) has an IL Interconnect Type

Interconnect Standard

Backplane Fabric

SRIO (Serial RapidIO)

Networking

of approximately -10 dB, or 39 percent of the total channel budget; 18" traces would consume 50 percent more, or 59 percent of the total channel budget! At Gen4 speeds, these I/O trace losses are large enough to cause catastrophic problems when interconnecting two similar units. A typical 18" low loss cable at Nyquist (8 GHz) has an IL of approximately -1.5 dB, or six percent of the total channel budget. This is more like it!

We would argue that a reasonable system level loss budget target would be: ›› 15 percent for each VPX module (x2 to cover both ends). This is consistent with ANSI/VITA 68.1. ›› 10 percent for each VPX chassis from backplane slot to I/O connector (x2 to cover both ends) ›› 50 percent for external I/O cable between the two ATR’s

FIGURE 1 Loss characteristics of traces versus cables. *Note: Does not include losses on the VPX modules nor losses in the external cable between the two ATR’s.

Gen2 (Gbaud)

Gen3 (Gbaud)

3.125

6.25

10.3125

PCIe (PCI Express)

2.5

5.0

8.0

16.0

Ethernet (KR types)

3.125

N/A

10.3125

N/A

Ethernet

3.125

N/A

10.3125

N/A

25.78125

2.5

5.0

10.0

14.0625

25.78125

2.125

4.25

8.5

14.025

28.050

SATA

3.0

6.0

N/A

12.0

SAS

3.0

6.0

N/A

12.0

Fiber Channel

HD Video

INTERCONNECTING TWO SIMILAR UNITS.

Gen1 (Gbaud)

InfiniBand Storage

LARGE ENOUGH TO CAUSE SERIOUS PROBLEMS WHEN

Gen4 (Gbaud)

HDMI

2.55

4.5

N/A

DisplayPort

2.7

5.4

8.1

N/A

Peripheral

PCIe (PCI Express)

2.5

5.0

8.0

16.0

Nyquist Frequency

Half of Baud Rate (GHz)

1.0625 – 1.5625

2.125 – 3.125

4.0 – 5.15625

6.0 – 8.0

TABLE 1

Gen5 (Gbaud)

25.78125

12.890625 – 14.025

Baud rates for various backplane and I/O standard.

www.vita-technologies.com

VITA Technologies Application Guide Winter 2017 |

25

VITA Technology Applications Uncovered

TECHNOLOGY FEATURE

The insertion loss of I/O traces is already a serious issue at current PCIe Gen3 rates, and will become a catastrophic problem at PCIe Gen4 rates (Figure 2). Each switched serial fabric has slightly different baud rates and budgets, but you can expect similar results.

The I/O signal loss problem can be addressed by either significantly reducing the I/O signal loss, or by adding active devices (repeaters/re-timers) close to the I/O connectors to restore signal integrity.

Development and demonstration using VPX+ cabling system Replacing long I/O traces with rugged cables can solve the loss problem, avoiding the need for active devices to restore signal integrity. In OpenVPX applications, an excellent

FIGURE 2

PCIe end-end channel insertion loss budget for (2) VPX ATR’s: Traces versus cables.

approach for Gen3 rates and higher is to utilize Meritec’s VPX+ cabling system for development and VPX+ DA (Direct Attach) cabling system for deployment.

The VPX+ cabling system has been used in many development systems. It effectively mates with standard OpenVPX backplane rear transition module (RTM) connectors. It can be used for slot-slot connections as well as for I/O connections, supporting custom slot-slot interconnects and often avoiding the need for custom backplanes in development applications. VPX+ is used with commercially available development backplanes in many applications, because extra signals can be easily added with the VPX+ cables. A shock and vibration test report is available from Meritec.

The VPX+ cabling system enables rapid evolution from development systems to demonstration systems (Figure 3).

Optional deployment rails provide additional strain relief for more rugged applications.

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Nuremberg, Germany

27.2 – 1.3. 2018

DISCOVER INNOVATIONS Immerse yourself in the world of embedded systems and discover innovations for your success.

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1

www.vita-technologies.com 22.09.17 09:49

FIGURE 4

VPX+ DA cable system press-fits in place of VPX RTM connectors using same vias.

directly replaces both the RTM backplane connectors and mating VPX+ connectors for both cost and weight reduction while realizing increased performance.

Ken Braund is the Business Development Manager at Meritec Bob Sullivan is a VITA Distinguished Fellow.

FIGURE 3

VPX+ cable system mates with VPX RTM connectors.

Rugged deployment using VPX+ DA (Direct Attach) cabling system Deployed platforms require a more rugged solution. Meritec’s VPX+ DA cabling system is the preferred approach for rapidly transitioning demonstration systems to moderately rugged applications such as air-cooled rack-mount platforms. VPX+ DA eliminates backplane RTM connectors that are used with VPX+, saving cost and improving performance. It can be easily dropped in to replace VPX+ cabling.

VPX+ DA press-fits directly into OpenVPX backplane connector holes, in place of backplane RTM connectors. The press fit connection is lower in cost, more rugged than VPX+ and with improved signal integrity performance.

In highly rugged systems such as conduction cooled ATRs the VPX+ DA offers other benefits. Its low profile is suitable for space-constrained or rugged conduction cooled applications such as ATRs (Figure 4). VPX+ DA can be used for some or all of the I/O signals and it can be combined with other I/O strategies such as I/O panels.

For development and demonstration applications, VPX+ cabling is a good solution for multi-gigabit OpenVPX I/O and custom slot-slot backplane interconnect in lieu of using one or more RTMs. For rugged deployment applications, VPX+ DA cabling is the rugged solution to solve trace loss issues for today’s newest multi-gigabit OpenVPX I/O. As compared to VPX+ cabling, VPX+ DA cabling www.vita-technologies.com

VITA Technologies Application Guide Winter 2017 |

27

VITA Technologiess Application Guide

FMC

APPICATION GUIDE INDEX

Sponsored By:

Company Page

FMC Sponsored by Annapolis Micro Systems . . . . . . . . . 28

Low-Latency & High-Bandwidth Mezz Cards

OpenVPX Advantech . . . . . . . . . . . . . . . . . . . . . . . 28

Ultra-Low Latency DRFM Mezzanine Cards have been designed from the ground up for latency sensitive DRFM applications.

The Board Support Interface provides a Digital Bypass Mode to achieve the lowest possible latency and a Fabric Space Mode to allow the user to do additional processing of the ADC data before returning it out the DAC. The Fabric Space Mode adds as little as 13ns of latency. Open Project Builder, Annapolis’ Design Tool, allows the user to design a DRFM-optimized application in minutes.

Features: • Single or Dual Channel available, running at up to 6.0 GSps • Ultra Low Latency from ADC SMA input to DAC SMA output • Digital Bypass Mode (SMA-to-SMA): as low as 15ns • Fabric Space Mode (SMA-to-SMA): as low as 23ns

Dawn VME Products . . . . . . . . . . . . . . . . . . 29

Dawn VME Products . . . . . . . . . . . . . . . . . . 29

Interface Concept . . . . . . . . . . . . . . . . . . . 29

Interface Concept . . . . . . . . . . . . . . . . . . . 30

PMC/XMC Alphi Technology Corp. . . . . . . . . . . . . . . . . 30

VME Sponsored by Themis Computer . . . . . . . . . . . . . 29

Artesyn Embedded Technologies . . . . . . . . . . . 30

VPX Sponsored by ADLINK Technology, Inc. . . . . . . . . . 30

• Converter channels easily synchronized High Bandwidth Mezzanine Cards have been designed from the ground up for maximizing data throughput. WFMC+ enabled cards include 32 high-speed serial lanes and 100 LVDS lines to accommodate even the most bandwidth-hungry ADCs or DACs. All Annapolis wide-bandwidth mezzanine cards deliver high channel counts, allow for synchronization across multiple cards, and have flexible high-precision trigger options. These rugged COTS mezzanines are optimized for high-performance operation in Wireless Communication, SATCOM Uplink/Downlink, Phased Array RADAR, SIGINT, and EW. Features: • Channels: 1-16 • Sample Rate: Up to 12.0 GSps • Resolution: 10-16 bits • Converter channels easily synchronized wfinfo@annapmicro.com • 410-841-2514 www.annapmicro.com/product-category/mezzanine-boards/ http://vita.opensystemsmedia.com/p374132

28 | VITA Technologies Application Guide Winter 2017

OpenVPX

Advantech MIC-6314 Advantech’s growing range of VPX CPU boards has been designed to serve compute-intensive, data and signal-processing applications in rugged military and aerospace environments. Their server-grade performance and proven reliability along with Advantech’s enhanced software, customization and long lifecycle provide equipment manufacturers maximum flexibility and confidence to focus on added-value mission-critical application development. Advantech’s VPX blades are VITA 46 and VITA 65 compliant commercial-off-the-shelf modules that can be integrated into standard OpenVPX backplanes. They support all the major fabric protocols, Serial RapidIO, PCI Express and Ethernet, for the highest speed data throughput and Linux, Windows and VxWorks operating systems. www.advantech.com/nc/spotlight/rugged http://vita.opensystemsmedia.com/p374488

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VME Dawn VME Products

VITA Technologiess Application Guide

Open VPX

Sponsored By:

PSC-6265

VITA 62 compliant 6U power supply for conduction cooled systems.

Dawn’s VITA 62 compliant 6U PSC-6265 can operate continuously in diverse environments over a wide range of temperatures at high power levels. The standard model is conduction to wedge lock cooled with an operating temperature range of -40° C to +85° C and a nonoperating range of -55° C to +105° C. The PSC-6265 operates continuously at a power level of 580 watts. For systems that require higher power levels, up to three supplies may be operated in parallel. Fault monitoring and control circuits protect the system from over-voltage, over-current, and over-temperature conditions.

HDversa

www.dawnvme.com/product-category/power-supplies http://vita.opensystemsmedia.com/p372930

Open VPX

Dawn VME Products PSC-6236

Universal AC Input VITA 62 3U Power Supply Dawn VME Products PSC-6236 universal AC input VITA 62 compliant 3U power supply for air or conduction cooled OpenVPX systems. True 6 channel supply with up to 400 watts output. Mission critical wide temperature range at high power. Input 85 VAC to 264 VAC, 47 Hz to 400 Hz. Can be special ordered to support high current single channel applications. Embedded RuSH™ technology actively monitors voltage, current and temperature, and provides protective control. Ruggedized – VITA 47 compliant. Rugged, Reliable and Ready. www.dawnvme.com/product-category/power-supplies http://vita.opensystemsmedia.com/p371658

OpenVPX

Interface Concept ComEth4510a The ComEth4510a is a combined Control and Data Plane switch for 6U OpenVPX Ethernet architectures. The Ethernet packet processor of our well-proven ComEth 43xxa range is used for the Control Plane, the Data Plane is implemented thanks to the Second-Generation Marvell Prestera CX platform, offering leading performance and port density with multiple 40 GbE/10 GbE configurations and full duplex line rate switching capability.

The two Ethernet switches are managed by a Multicore 64-bit PowerPC, offering two optional out-of-band 1000Base-T ports (front and rear) and traffic log recording on NAND Flash.

http://www.interfaceconcept.com/products/cometh-4510a.html http://vita.opensystemsmedia.com/p374477

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The perfect upgrade path for 6U VME & CompactPCI systems, the Themis HDversa features a redundant power backplane with twelve module bays that fit standardized storage, graphics, networking, and management modules.

Designed to easily fit in the same physical space as legacy VME platforms, this rugged solution simplifies technology upgrades, reduces costs, accelerates workloads, and offers a wide-range of functionality for tactical data centers, machinery control systems, signal processing systems, and remotely-located console controllers Only 10" (254mm) deep and 6U (44.45mm) tall, the HDversa is a lightweight, low power computing platform – requiring only 50-100W of power for each hot swappable module.

Each Compute Module includes: • Intel® Xeon® D-1587 (16-core, 32-thread) or D-1541 (8-core, 16-thread) processor •

Up to 128GB of DDR4-2133 ECC memory

•

Two USB 3.0 ports

•

M.2 NVME storage up to 2TB

•

Two 10Gigabit and two 1Gigabit Ethernet ports

•

VGA and serial ports

•

TPM 2.0 support

•

IPMI 2.0 with remote KVM

With six module options, the versatile HDversa offers a wide-range of functionality suited for any mission critical application.

www.themis.com/hdversa http://vita.opensystemsmedia.com/p374474

VITA Technologies Application Guide Winter 2017 |

29

VITA Technologiess Application Guide

VPX

OpenVPX

Sponsored By:

Interface Concept ComEth4580a

VPX3010 Rugged 3U VPX Intel® Xeon® D-1500 CPU Blade

The ComEth4580a is a high performance OpenVPX fully managed Ethernet Switch, providing up to 6 ports 10G, up to 32 Gigabit ports and 4 SFP cages. Its Ethernet matrix featuring a highly flexible L2/L3 forwarding, classification and policy engine, provides the ComEth4580a with state-of-the-art packet processing technology. The management application, named SWITCHWARE, is carried out by the ComEth 4580a embedded ARM processor and provides IPv6 support, RIPng, OSPF v3, VRRP, security features, configurable memory allocation, and new status counters.

The ComEth4580a is compliant with VITA 46.0 standard, and available in air-cooled and conduction-cooled versions. http://www.interfaceconcept.com/products/cometh-4580a.html http://vita.opensystemsmedia.com/p374476

The ADLINK VPX3010 with Intel’s latest Xeon Processor D SoC provides faster processing and GPGPU acceleration for boosted workload throughput. This SWaP-optimized rugged VPX blade can be equipped with a 384 CUDA core NVIDIA GeForce GT 745M GPU XMC module for greatly enhance performance capabilities.

The VPX3010 Series is a 3U VPX processor blade featuring the Intel® Xeon® Processor D-1500 SoC with up to 12 cores.

The VPX3010 provides up to 16GB DDR4-2133 dual channel ECC memory soldered onboard, one PCI Express x8 Gen3 XMC expansion slot with VITA 46.9 rear IO, and onboard soldered 32GB SLC SATA solid state drive. Rear I/O via P1 and P2 includes 2x 10GBASE-KR, 2x 1000BASE-T (or one 1000BASE-T and two 1000BASE-BX by BOM option), 2x SATA 6 Gb/s, 1x USB 2.0, 2x USB 3.0, 6x GPIO, VGA, 1x RS-232, 1x RS-232/422, and up to PCIe x16 Gen3 supporting non-transparent bridge for peer-to-peer communication (dependent on BOM option).

The VPX3010 Series is available in rugged conduction and air cooled versions with conformal coating, making it ideal for mission critical applications in radar; intelligence, surveillance and reconnaissance (ISR); signals intelligence (SIGINT) and UAV/UGV platforms. ®

Each Compute Module includes: • Intel® Xeon® Processor D-1500 SoC up to 12 cores (formerly “Broadwell-DE”) • DDR4-2133 soldered ECC SDRAM up to 16GB • Dual 10G-KR, up to three 1G Ethernet ports • Up to PCIe x16 Gen3 interface supporting nontransparent bridge • One XMC expansion slot, PCIe x8 Gen3 with Rear I/O to P2 • Conduction or air cooled with conformal coating • OS support: VxWorks 7.0, Red Hat Linux 6.5 and Windows 7 http://www.adlinktech.com/PD/web/PD_detail.php?cKind=&pid=161 0&seq=&id=&sid=&source=&utm_source=&category=VPX_VPX-3U &source=&mktg_source=OSM http://vita.opensystemsmedia.com/p374478

30 | VITA Technologies Application Guide Winter 2017

PMC/XMC

Alphi Technology Corp PCIe-Mini-ARINC429-4/8 Features: • ARINC 429-based PCIe-Mini card ARINC controller • Up to 4 transmitters and 8 receivers channels for ARINC controller • Programmable label recognition for 256 labels per channel • 32 x 32 Receive FIFOs and Priority-Label buffers • Dependent data rates for Transmit and Receive • Meets the ARINC 429 specifications for loading, level detection, timing, and protocol • Software selected data rate of 12.5kbps or 100kbps with automatic slew rate adjustment • Burst and continuous mode available • Programmable word length selection, with the parity bit generated automatically • Programmable Interrupt support • Differential IRIG B Input www.alphitech.com http://vita.opensystemsmedia.com/p372995

VME

Artesyn Embedded Technologies MVME250X Series VME64x SBC with NXP QorIQ P2010/P2020 Artesyn’s MVME250X series features the NXP® QorIQ® single-core P2010 or dual-core P2020 processor. It is a cost-effective migration path for older generation boards used in many automation, medical, and military applications – backed by Artesyn’s 35+ years of development expertise and commitment to expanding and supporting our VME portfolio through 2025 and beyond. Memory includes up to 2GB DDR3 and 512KB non-volatile MRAM. The MVME2502 variant has 8GB soldered eMMC solid state memory for additional rugged, non-volatile storage. Connectivity includes Gigabit Ethernet, USB2, serial, SATA and either one or two PMC/ XMC sites. A hard drive mounting kit and conformal coating are available. https://www.artesyn.com/computing/products/category/vmebus http://vita.opensystemsmedia.com/p374090

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