Advances in Microelectronic Engineering (AIME) Volume 2 Issue 4, November 2014
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A Simplified DC Thermal Model of Recessed Gate P-HEMTs for CAD Applications Leonardo Suriano*1, Roberto Marani*2, Anna Gina Perri*3 123
Department of Electrical and Information Engineering, Polytechnic University of Bari
via E. Orabona, 4. 70125 Bari, Italy annagina.perri@poliba.it
*
Abstract In this paper we presents a DC thermal model of recessed gate P-HEMTs in which we propose several issues to allow an easy implementation in circuit simulators. In particular we identify transistor thermal parameters, which have greater influence on the device behaviour. In order to verify the accuracy of the proposed model, the results are compared with those of a model, already proposed, obtaining a negligible relative error. However the proposed simplified model can be easily used for CAD applications, with computational time very short. Keywords HEMT; Thermal Effects; Modeling; Output Characteristics; CAD
Introduction In (Chaibi et al., 2012) a mathematical model for thermal effects on HEMT devices has been proposed. It is based on the mathematical equations for accurately modeling the drain to source current in recessed gate P-HEMT devices (Fernandez et al., 1999). However it cannot be directly and easily used for CAD applications. In this paper we present a simplied DC thermal model that reproduces the I - V characteristics for the recessed gate P-HEMT devices. In our model, based on the work described in (Chaibi et al., 2012), we propose several issues to allow an easy implementation in circuit simulators. In particular we identify which transistor parameters have greater influence on the device behaviour for temperature variations. In order to verify the accuracy of the proposed model, the results are compared with those of Chaibi model (Chaibi et al., 2012), obtaining a negligible relative error with the improvement that the proposed model can be easily used in modelling languages, such as SPICE, with computational time very short. The Proposed DC Thermal Model Generally the empirical DC models of electronic
devices for CAD purposes are developed by using mathematical functions, whose graphical representation is similar to the measured I-V curves. The use of empirical parameters enables the modeled curves to be matched to the measured curves as well as possible. The absolute error between measured and calculated current values is minimised and the parameter extraction procedure is performed. In terms of computability an empirical model is much more easily tailored to fast convergence performance, computing time and accuracy as well as second-order effects. On the other hand, this kind of model is less intuitive than a physical model. Consequently, much more assistance is needed for the parameter extraction of the model, especially to perform an initial estimation of the empirical parameters that will give low CPU time consumption and the extraction of the best set of parameters, allowing the best fit between measured and modeled current values. Moreover the drain-source current is modeled as a function of internal voltages, considering the voltage drop due to the source and drain parasitic resistances. This is a limitation of this type of model, since the resistances depend on the bias conditions. In fact the parameter extraction procedure needs very difficult measurement of parasitic resistances under many bias conditions. The problem can be overcome by assuming a constant value for these resistances, but this approach affects the model with many approximations regarding the extracted parameters (Marani et al., 2009) (Gelao et al., 2011). Moreover, the empirical parameters are generally considered independent of, or weakly dependent on, the bias conditions, reducing the model accuracy, particularly at the beginning of the saturation region (Perri, 2011), (Marani et al., 2011), (Marani et al., 2012), (Marani et al., 2012), (Marani et al., 2013) and (Marani et al., 2014).
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Advances in Microelectronic Engineering (AIME) Volume 2 Issue 3, July 2014
The DC thermal model that we propose has been implemented with the following aims: 1.
to improve the accuracy of simulated I-V curves, in particular in the knee and saturation regions;
2.
to give the device source-drain current as a function of external voltages, as seen at the device gates, by-passing the very difficult measurement of parasitic resistances for the IV characterisation.
3.
to use empirical parameters to be extracted by a quick and accurate procedure, the initial estimation of empirical parameters being performed referring to measured I-V curves and to physical considerations, making univocal, fast and easy the extraction of the best fitting parameter set.
4.
to reproduce the I-V characteristic both in static (dc) condition and in dynamic (pulse) condition in order to predict the device behaviour at high current levels and to improve the trend of dynamic curves in the different operating regions (knee, pinch-off, saturation, etc). Therefore it is appropriate to employ continuous expressions depending on the instantaneous control voltages vgi(t) and vdi(t).
For these previous reasons, our initial approach has been to start from the following expression of the drain-source current Ids, already proposed in (Chaibi et al., 2012): I ds = I dss
v δ giflch ⋅ exp − µ
⋅ v gitoff
(
)(E+ K E ⋅vgi )
S L ⋅ v di ⋅ tanh I dss ⋅ 1 − K G ⋅ v gi
S ⋅v ⋅ 1 + S di I dss
(
v git
lch
(
1 ⋅ χ ⋅ v git + v git lch 2η
[
(
[
( )]
= ln 2 ⋅ cosh χ ⋅ v git
)]
(1)
)
(2) (3)
= ln 2 ⋅ cosh v gif
(4)
v git = v gi − (VP + γ ⋅ v di )
(5)
v gif = v gi − VPF
(6)
v gif
lch
In the previous equations for our model the 2
In this paper the problem of thermal dependence of DC characteristics, which may be approached by the calculations of the thermal gradient inside the device and drain-source current Ids (Perri, 2011), has been dealt, considering self-heating and trapping effects. In particular, in Equations (1-6), there are 13 model parameters, i.e.: Idss, VP, VPF, γ, χ, η, KG, SL, SS, KE, E, µ and δ whose values vary with temperature. Therefore we have studied their effects on I-V curves in the temperature range from -70°C to +70°C, modeling, for any variable, a dependance on temperature by a linear law, in agreement with (Chaibi et al., 2012): piDCT = piDCT 0 + K iDC (T − T0 )
(7)
where piDCT is the i-th parameter of DC model for Ids at the temperature of interest T; piDCT 0 is the value of the same parameter at room temperature T0 and K iDC defines the temperature dependence of i-th parameter. (from Chaibi et al., 2012)..
)
Analysis of Thermal Device Parameters
TABLE 1. VALUES OF MODEL AND THERMAL PARAMETERS
where: v git off =
considered voltages are external, i.e. measured at the device external terminals both in dc and in pulse conditions. In this way it is possible to overcome the problem of measurement of the parasitic resistances, thus making easier the parameter extraction procedure and the use of the model for circuit design. If the complete DC device characterisation requires the resistances to be determined, the linear approximation can be used for them without affecting the I-V model accuracy.
Parameter
DC value at T0
Idss VP VPF γ χ η KG SL SS KE E µ δ
443.26 (mA) - 2.2467 (V) 0.7012 (V) - 0.0657 0.962 3.612 73.223 (V-1) 24.8032 423.844 (mA/V) - 0.7593 (V-1) -2.8967 0.2892 0.3102
Thermal parameter K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13
Value -1.0061.10-3 (A/K) -1.95.10-3 (V/K) 2.4568.10-4 (V/K) 9.9949.10-5 (K-1) -1.6190.10-3 (K-1) -6.6054.10-3 (K-1) 0.68329 (V-1/K) 0.23443 (K-1) 9.0356.10-4 (A/(V.K)) -7.6036.10-4 (V-1/K) -3.7347.10-3 (K-1) -4.1814.10-4 (K-1) 6.4947. 10-5 (K-1)
In order to study the effect of each variable on I-V curves and to compare them with experimental curves reported in (Chaibi et al., 2012), we have used the
Advances in Microelectronic Engineering (AIME) Volume 2 Issue 4, November 2014
same parameters values listed in Table 1.
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0.14
0.12
0.1
Ids [A]
We have implemented a Matlab tool, regarding 3 temperatures (-70 °C, 27 °C and +70 °C, where we have experimental data. In particular the device under test is a 8 x 75 µm (8 fingers of 75 µm long each) AlGaN/GaN P-HEMT, having a 0.2 µm recessed gate length, manufactured by III-V Laboratory (Fernandez et al., 1999). In Fig. 1 we have reported Ids – Vds characteristics considering only Idss changes with temperature T, while in Fig. 2 the same when VP varies with T.
0.08
0.06 27°C -70°C +70°C
0.04
0.02
0
0.12
0
5
10
15 Vds [V]
20
25
30
FIG. 3. SIMULATED IDS – VDS CHARACTERISTICS FOR VPF CHANGES WITH T.
0.1
0.08 Ids [A]
0.12 0.06
0.1 0.04 27°C -70°C +70°C
0.08 Ids [A]
0.02
0
0
5
10
15 Vds [V]
20
25
0.06
30
0.04
FIG. 1. SIMULATED IDS – VDS CHARACTERISTICS FOR ONLY TEMPERATURE VARIATIONS OF IDSS .
27°C -70°C +70°C
0.02
0
0.14
0
5
10
15 Vds [V]
20
25
30
0.12
FIG. 4. SIMULATED IDS – VDS CHARACTERISTICS FOR TEMPERATURE VARIATIONS OF γ .
Ids [A]
0.1
0.08
0.12
0.06
0.1 27°C -70°C +70°C
0.04
0.08
0
Ids [A]
0.02
0
5
10
15 Vds [V]
20
25
0.06
30
0.04
FIG.2. SIMULATED IDS – VDS CHARACTERISTICS FOR VP CHANGES WITH T.
Similarly, in Figures 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 and 13, we have shown the Ids – Vds characteristics considering, one at a time, the changes with T of the other thermal parameters, i.e. VPF, γ, χ, η, KG, SL, SS, KE, E, µ and δ respectively.
27°C -70°C +70°C
0.02
0
0
5
10
15 Vds [V]
20
25
30
FIG. 5. SIMULATED IDS – VDS CHARACTERISTICS FOR χ CHANGES WITH T.
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0.12
0.14
0.12
0.1
0.1
0.08
Ids [A]
Ids [A]
0.08
0.06
0.06
0.04 0.04
27°C -70°C +70°C
0.02
0
0
5
10
15 Vds [V]
20
25
0.02
0.12
0.12
0.1
0.1
0.08
0.08
0.06 27°C -70°C +70°C
0
5
10
15 Vds [V]
20
25
20
25
30
27°C -70°C +70°C
0
5
10
15 Vds [V]
20
25
30
FIG. 10. SIMULATED IDS – VDS CHARACTERISTICS FOR TEMPERATURE VARIATIONS OF KE .
0.12
0.12
0.1
0.1
0.08
0.08
Ids [A]
Ids [A]
15 Vds [V]
0.06
0
30
0.06
0.06
0.04
0.04 27°C -70°C +70°C
0.02
0
5
10
15 Vds [V]
20
25
FIG. 8. SIMULATED IDS – VDS CHARACTERISTICS FOR SL CHANGES WITH T.
4
10
0.02
FIG. 7. SIMULATED IDS – VDS CHARACTERISTICS FOR KG CHANGES WITH T.
0
5
0.04
0.02
0
0
FIG. 9. SIMULATED IDS – VDS CHARACTERISTICS FOR SS CHANGES WITH T.
Ids [A]
Ids [A]
0
30
FIG. 6. SIMULATED IDS – VDS CHARACTERISTICS FOR TEMPERATURE VARIATIONS OF η.
0.04
27°C -70°C +70°C
27°C -70°C +70°C
0.02
30
0
0
5
10
15 Vds [V]
20
25
FIG. 11. SIMULATED IDS – VDS CHARACTERISTICS FOR E CHANGES WITH T.
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Advances in Microelectronic Engineering (AIME) Volume 2 Issue 4, November 2014
Discussion of Results
0.2
The analysis of the previous figures (in particular of Figures 1, 3 and 13) allows us to assert that Idss, VPF and δ thermal parameters have practically no influence in the DC thermal model and therefore we have neglected them, thus saving processing time and making our simplified model suitable to be introduced in commercial simulators (like SPICE, ADS, etc.).
0.18 0.16 0.14
Ids [A]
0.12 0.1 0.08
In fact, in Fig.14, we have reported the simulated Ids – Vds characteristics for the device under test, obtained from Chaibi model (continuous lines) and from our simplified model (dashed lines).
0.06 27°C -70°C +70°C
0.04 0.02 0
0
5
10
15 Vds [V]
20
25
30
FIG. 12. SIMULATED IDS – VDS CHARACTERISTICS FOR µ CHANGES WITH T. 0.12
0.08 Ids [A]
We have evaluated the relative error, obtaining a maximum value of 2.76 % at T = - 70 °C and at Vds = 10.1 V. For other temperatures Ids – Vds characteristics obtained from Chaibi model and from our model are practically coincident and overlapping with experimental data. These results have been obtained calculating the root mean-square errors between our model and Chaibi model, obtaining however a CPU calculation time much more low.
0.1
0.06
0.04
In this way we may assert that our simplified model is particularly suitable to be introduced in commercial simulators.
27°C -70°C +70°C
0.02
0
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Conclusions 0
5
10
15 Vds [V]
20
25
30
FIG. 13. SIMULATED IDS – VDS CHARACTERISTICS FOR δ CHANGES WITH T.
We have presented a simple DC thermal model of recessed gate P-HEMT devices for CAD applications. In our model, based on a work described in (Chaibi et al., 2012), we have proposed several issues to allow an easy implementation in circuit simulators, identifying which transistor parameters have greater influence on the device behaviour for temperature variations. The main aims have been to improve the accuracy of modelled I-V curves, in particular in the knee and saturation regions; to give the device source-drain current as a function of external voltages, as seen at the device gates, by-passing the very difficult measurement of parasitic resistances for the I-V characterisation and to reproduce the I-V characteristic both in static and in dynamic conditions in order to predict the device behaviour at high current levels and so to improve the trend of dynamic curves in the different operating regions.
FIG. 14. SIMULATED IDS – VDS CHARACTERISTICS OBTAINED FROM CHAIBI MODEL (CONTINUOUS LINES) AND FROM OUR SIMPLIFIED MODEL (DASHED LINES).
To verify the accuracy of the proposed model, the results have been compared with those of the model proposed in (Chaibi et al., 2012), obtaining a negligible
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Advances in Microelectronic Engineering (AIME) Volume 2 Issue 3, July 2014
relative error at T = - 70 °C and Vds = 10.1 V.
Progedit, 2011, ISBN 978-88-6194-081-946.
For other temperatures Ids – Vds characteristics obtained from Chaibi model and from our simplified model have been practically coincident and overlapping with experimental data, with however a CPU time much more low. REFERENCES
Chaibi M., Fernandez T., Mimouni A., Rodriguez-Tellez J., Tazon A. and Mediavilla A. “Nonlinear modeling of trapping and thermal effects on GaAs and GaN MESFET/HEMTdevices”.
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Progress
In
Electromagnetics Research, vol. 124, 163-186, 2012. Fernandez T., Garcia J.A., Tazon A., Mediavilla A., Pedro J.C. and Garcia J.L. “Accurately modeling the drain to source current in recessed gate P-HEMT devices”. In IEEE Electron Device Letters, vol. 20, n.11, 557-559, 1999. Gelao G., Marani R., Diana R. and Perri A.G. “A SemiEmpirical
SPICE
Model
for
n-type
Conventional
CNTFETs”. Im IEEE Transactions on Nanotechnology, vol. 10, n.3, 506-512., 2011. Marani R. and Perri A.G. “A Compact, Semi-empirical Model of Carbon Nanotube Field Effect Transistors oriented
to
Simulation
Software”.
In
Current
Nanoscience, vol. 7, n. 2, 245-253, 2011. Marani R. and Perri A.G. “A DC Model of Carbon Nanotube Field Effect Transistor for CAD Applications”. In International Journal of Electronics, vol, 99, n. 3, 427 – 444, 2012. Marani R. and Perri A.G. “CNTFET Modelling for Electronic Circuit Design”. In ElectroChemical Transactions, vol. 23, n.1, 429 – 437, 2009. Marani R. and Perri A.G. “Modelling of CNTFETs for Computer Aided Design of A/D Electronic Circuits”. In Current Nanoscience, vol. 10, n. 3, 326-333, 2014. Marani R., Gelao G. and Perri A.G. “Comparison of ABM SPICE library with Verilog-A for Compact CNTFET model implementation”. In Current Nanoscience, vol. 8, n. 4, 556-565, 2012. Marani R., Gelao G. and Perri A.G. “Modelling of Carbon Nanotube Field Effect Transistors oriented to SPICE software for A/D circuit design”. In Microelectronics Journal, vol. 44, n. 1, 33-39, 2013. Perri A.G. “Dispositivi Elettronici Avanzati.” Bari, Italy, Ed.
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Perri A.G. “Modelling and Simulations in Electronic and Optoelectronic Engineering”. Ed. Research Signpost, 2011, ISBN 978-81-308-0450-7. Leonardo Suriano received his bachelor degree in Electronics Engineering from Polytechnic University of Bari, Italy, in 2007. He started to work as a electronic designer for Industrie Dial Face on July, 2008, and in the 2009 he became a technical manager of production. Now he is completing his studies at University of Glasgow. Roberto Marani received the Master of Science degree cum laude in Electronic Engineering in 2008 and his Ph.D. degree in 2011 from Polytechnic University of Bari. In December 2008 he received a research grant by Polytechnic University of Bari for his research activity. In December 2008 he received a research grant by Polytechnic University of Bari for his research activity. He worked in the Electronic Device Laboratory of Bari Polytechnic for the design, realization and testing of nanometrical electronic systems, quantum devices and FET on carbon nanotube. Dr. Marani has published over 100 scientific papers. Anna Gina Perri received the Laurea degree cum laude in Electrical Engineering from the University of Bari in 1977. In the same year she joined the Electrical and Electronic Department, Polytechnic of Bari, where she is Full Professor of Electronics from 2002. Since 1977 her principal interests have involved optical fiber communication systems, microwave MESFET amplifier design and applications, and design and test of electronic systems for domiciliary teleassistance. For these activities in 2004 she was awarded the “Attestato di Merito” by ASSIPE (ASSociazione Italiana per la Progettazione Elettronica), Milano, BIAS’04. Her current research is in the area of numerical modelling and performance simulation techniques of heterojunction electronic devices. Moreover she works in the design, realization and testing of nanometrical electronic systems, quantum devices and FET on carbon nanotube. Prof. Perri is the Director of Electron Devices Laboratory of the Polytechnic University of Bari and currently is President of the Board of Professors of Master of Science in Electronic and Telecommunications Engineering. She is author of over 250 book chapters, journal articles and conference papers and serves as referee for many international journals.