A CIS-Based for Check-Scanning System

International Journal of Information and Computer Science (IJICS) Volume 3, 2014 doi: 10.14355/ijics.2014.03.010

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A CIS-Based for Check-Scanning System Hou Ligang , Zhang Zhiyuan , Geng Shuqin College of Electronic Information & Control Engineering, Beijing University of Technology, Beijing, 100124, China zhangzy@emails.bjut.edu.cn Abstract In this paper, we describe a sophisticated scanning system, which is based on an advanced Contact Image Sensor (CIS), used to scan the image and to verify the authenticity of the checks. The entire structure works on the FPGA platform, and the CIS is responsible for sampling the image information served as analog signal that is sent to A/D converter subsequently, aiming to convert analog signal to digital signal. It is important that those digital signal is sent to PC through Cypress non-destructively because those data need to be analyzed by a software on PC to acquire the useful information. This implementation not only clearly scans the image of checks, but it is high precision, simple design, and easy to carry.

needn't to be preheated, immediately work on power.

That those three kinds of color, (red, green and blue,but infrared and ultraviolet haven't been referred in this step)provide three-primary-color which is used to scan the check by switching the light source fast.

The revolution of CIS is 600 dpi and it collects 2592 points which is equal among those three kinds of light.

Furthermore, switching fast light emitting diodes

can

System Structure PC

analog signal

CIS; FPGA; A/D; Cypress; CCD

CIS (Contact Image Sensor) is a relatively recent technological innovation in the field of optical flatbed scanners that are rapidly replacing CCD in low power and portable applications. A CIS typically consists of a linear array of detectors, covered by a focusing lens and flanked by red, green, blue, infrared and ultraviolet. The use of LEDs allows the CIS to be highly power efficient, allowing scanners to be powered through the minimal line voltage supplied via a USB connection. CIS devices typically produce lower image quality compared to CCD devices; in particular, the depth of field is greatly limited, which poses a problem for material that is not perfectly flat.

However, a CIS contact sensor is smaller and lighter than a CCD line sensor, and allows all the necessary optical elements to be included in a compact module, thus helping to simplify the inner structure of the scanner.

CIS

The system uses ALTERA's Cyclone IV development board. When the system on working, FPGA supply a stable clock signal that is 24M for CIS and AD9822 to cater the desired mode of its work by the system, and then the data collected by CIS has been stored in the FPGA internal ram.

Keywords

Introduction

therefore

AD9822 via USB to PC

CY68013

CIS

Digital signal

send by package

FPGA

FIG. 1 SYSTEM STRUCTURE Firstly, a 50MHz-clock signal produced by crystal has been divided into 8MHz which is provided to AD9822 through a digital PLL. FPGA is the core on control of image-scanning and handling, and controlling the driven signal when CIS works, including a lightsource signal, CIS start signal and a clock signal, etc.

Meanwhile FPGA also need to be responsible for a high-speed A/D converter AD9822 to provide the conversion clock signal. Under the control of FPGA, CIS transmits all analog signal collected by each point as analog voltage value to signal-conditioning circuit through the serial shift mode, then those analog signal is sent to differential amplifier circuit together with the reference voltage from CIS. The signal which is amplified by differential amplifier circuit is transmitted to AD9822 aiming to convert the analog signal to a digital signal that will be sent to FPGA to package via A/D converter. Finally, every package of

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data has been sent to PC to analyze and generating waveforms and images depend on relative software.

System block diagram shown in Fig. 1 and Fig. 2: CIS interface

AD9822 analog signal

control

CIS interface

Digital signal

FIFO

control

CDSLK2/ADCCLK /SCLK/SLOAD/S DATA

FIG. 2 SYSTEM STRUCTURE State Machine There is a system status machine which is divided into three parts in FPGA; the first one is SYSTEM-IDLE; the second one is A/D-CONFIGURATION, and the last one is SYSTEM-SCAN. At the beginning of the system work, the system status is set to be SYSTEM-IDLE. The system status automatically jumps into next status, called A/D-CONFIGURATION when the systemstatus-counter counts 9. Meanwhile the system status counter is cleared and the transmission enable signal of SPI data bus jumps to a high level. In other words, System can transmit configuration commands to AD9822. Under the configuration status of AD9822, SPI enable signal changes from high to low, which means SPI data transmission is end and the system status steps into system scan status, enable signal of CIS stays open, that is CIS is capable of keep normal working conditions. When scanning of the CIS is finished, the system status is back to the initial status of the system—SYSTEM-IDLE. System state transition diagram shown in FIG. 3:

SYS_STATE～10

SYS_IDLE

SYS_AD_CF G

SYS_SCAN

FIG. 3 STAE SWITCHING Timing When analogy data is sent to AD9822, the timing of

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A/D is one of the most important element. Here, we use the 1-Channel SHA Mode. This mode operates in the same way as the 3-channel SHA mode, except the multiplexer remains stationary. Only the channel specified in the MUX register is processed. The input signal is sampled with respect to the voltage applied to the OFFSET pin. With the OFFSET pin grounded, a 0 V input corresponds to the zero-scale of ADC output. The OFFSET pin may also be used as a coarse offset adjust pin. A voltage applied to this pin is subtracted from the voltages applied to the red, green, and blue inputs in the first amplifier stage of the AD9822. The input clamp is disabled in this mode. For more information, see the Circuit Operation section.

Timing for this mode is shown in Figure 3. CDSCLK1 should be grounded in this mode of operation. 1Channel CDS Mode Timing shown in FIG. 4: 8MHz's clock signal is recommended to the system as a work clock, and every 160 clock cycles system generates a pulse signal called CIS_SI. When CIS_SI's rising edge comes, AD9822 start to begin to collect a set of data. CIS's work timing shown in FIG. 5:

FIG. 4 TIMING CLK

...

...

...

...

CIS_SI

AD_DATA

FIG. 5 TIMING Result Drawing on the experience of previous as well as the continuous improvement process on design ideas, by adjusting the time interval of AD9822 data collection and tentatively raising the CIS brightness from the original "300" to "1900", finally, replacing AD9822 internal reference voltage by its external reference voltage change, and ultimately we make the output waveform be stable, as shown FIG. 6: Because of the shortage of charge in hand, we use a RMB to be sample, the image through scanning as

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completing precision scanning for image.

shown in FIG. 7:

ACKNOWLEDGMENT

This work is supported by the National Natural Science Foundation of China (No.61204040, 60976028), the Ph.D. Programs Foundation of Ministry of Education of China (No.20121103120018), the Plan Program of Beijing Education Science and Technology Committee (No. JC002999201301), and the Beijing Municipal Natural Science Foundation (No. 4152004).

FIG. 6 OUTPUT WAVEFORM

REFERENCES

A.Kumar et.al. “Reconfigurable Multi-Processor Network-on-Chip on FPGA.” ASCI 2006 Fritz Mayer-Lindenberg. “High Level FPGA Programming through Mappings Process Networks to FPGA Resources.”

Paper

presented

at

the

International

Conference

on

Reconfigurable Computing and FPGAs, 2009 Haris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, and Venkata

FIG. 7 IMAGE

Jakkula. “Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems.” IEEE Design &

Conclusions Basing on the research to current banknote scanning technology, this paper proposed and completed check scanning program's design with independent intellectual property rights through building circuit platform which is mainly made of the FPGA, CIS, AD9822, CY7C68013 for the acquisition, conversion, packing, processing of image data, successfully

Test, NEC Laboratories America, 2004 R. Dimond, O. Mencer, W. Luk. “CUSTARD- A Customisable Threaded FPGA Soft Processor.” FPL’05 T.Harris et al. “Compiilation from Matlab to Process Networks realized on FPGA.” Sig. Syst. Comp. 2001

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