Simulation of μ-Bump and TSV in 3-D Integration

Simulation of µ-Bump and TSV in 3-D Integration K. Weide-Zaage, A. Moujbani RESRI Group IMS-AS, Leibniz Universität Hannover, Hannover, 30655, Germany weide-zaage@ims.uni-hannover.de; moujbani@ims.uni-hannover.de Abstract The reduction of package and chip size by the need of cost reduction on one hand and the need of high voltage metallization on chip for power applications on the other hand the thermal electrical-mechanical management concerning the reliability becomes more and more critical. Breakdown failures due to mechanical stress, moisture uptake, migration effects caused by current crowding, temperature gradients due to Joule heating and stress gradients and intermetallic phase growth have an increasing importance. With the help of simulations the weakest links as well as locations with high thermal electrical and mechanical loads can be determined. This will be shown for selected examples.

Keywords Simulation; Reliability; 3D-Integration; Migration; Mechanical Stress

Introduction The increase of high integration of chip and package leads to problems in system on chip (SoC) development influencing the costs and the time-to-market negatively. The system complexity results in integration of analog and digital components on a single chip and the use of new packaging concepts.

The environment as well as new materials like Pb-free solder material, the use of organic materials and new dielectrics influence the reliability and quality of the devices and systems and can yield in the worst case to a complete re-design (Figure 1). One example in conjunction with chip package interaction (CPI) is the structural integrity for Cu/low-k ICs during fabrication and the integration into high-density flip-chip package. Caused by the thermo-mechanical deformation due to the CTE mismatch between the silicon die and the organic substrate in the package high mechanical stress occurs. This leads to intrinsic stress and strain in the structures provoked also by different processing temperatures.

FIGURE 1. RELIABILITY; QUALITY AND LAYOUT DEPANDENCE OF SOME PHYSICAL FAILURES IN THE DEVICE AND COMPONENTS.

One possible solution new packaging concepts is the usage of through silicon via (TSV). Several problems can occur in the active region (the transistor region) of the chip. This leads to the definition of keep-out-zones (KOZ) International Journal of Engineering Practical Research, Vol. 4 No. 1-April 2015 2326-5914/15/01 079-04 © 2015 DEStech Publications, Inc. doi: 10.12783/ijepr.2015.0401.16

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around the TSV, which are responsible for restrictions in the placement. Due to CTE mismatch of the different materials in the back-end-of-line (BEOL) and front-end-of-line (FEOL) mechanical stress can lead to cracking and ratcheting due to normal shear stress under temperature load. Through-silicon-vias (TSV), interconnects and landing pads have also a strong mismatch in their proportions. Beside high temperatures high applied currents can influence the reliability of the systems and components. Also the electrical performance can be drastically influenced shown in Figure 2.

FIGURE 2. RELIABILITY PROBLEMS IN 3D INTEGRATION OF TSV DUE TO CTE MISMATCH IN BEOL AND FEOL. TABLE 1 MATERIAL PARAMETERS FOR THE TSV AND INTERCONNECT USED IN THE SIMULATIONS

Material

α [1/K]

E [GPa]

ρ [Ωµm]

W

0.45 10-3

362

0.056

Κ [W/(mK)] 178

Cu

1.6 10-3

125

0.0174

395

SAC TiN SiN

2.0 10-3 11 10-3 0.8 10-3

45 80.6 312

0.132 0.11 1.0 10-6

55.52 208 70

Example Mechanical Simulation of TSV The thermal-electrical-mechanical simulations were carried out with the finite element program ANSYS®. Local temperature and temperature gradient distributions as well as local mechanical stress can be achieved by the simulations. In the past the prediction of local weak spots in interconnect contacts as well as TSVs and solders bumps by finite element simulations were described as a helpful procedure [1, 2]. The birth-death method was used to replicate the manufacturing steps. The results were compared with calculations using a reference temperature for the stress free state, which is usual in the mechanical simulations. The mechanical and electrical material properties used in the simulations are given in Table 1. The material data were taken from literature or measurements of earlier investigations [2, 3]. The geometrical data were taken partly from [4, 5].

FIGURE 3. MECHANICAL STRESS AROUND THE TSV NEAR THE ACTIVE REGION WITH PROCESS TEMPERATURES. AND RIGTH PICTURE WITH REFERENCE TEMPERATURE.

FIGURE 4. MECHANICAL STRESS AROUND THE TSV NEAR THE ACTIVE REGION WITH REFERENCE TEMPERATURE.

Simulation of µ-Bump and TSV in 3-D Integration

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The thermal-electrical-mechanical behavior was calculated. It was found that the mechanical stress around the TSV near the active region shows values one order of magnitude higher for the reference temperature comparing to the values including the intrinsic stress shown in figure 3 and figure 4. The processing temperatures should be included in the mechanical simulations of the TSV. Example Interconnects of µ-Bumps For the determination of a reliable layout of µ-bumps based on IMC phases the determination of electromigration (EM) induced mass flux divergences can be used. The procedure for the calculation of the mass fluxes is described in [6]. The structure used in this investigation based on a test structure for electromigration investigation described in [7]. The simulation model is shown in figure 5. The µ-bump has a diameter of 25µm and a height of 10µm and consist of Cu3Sn (yellow) and Cu6Sn5 (cyan). The embeeded Cu interconnects (not visible) are covered by SiN (blue), Si in red. The Cu interconnect had a thickness of 0.5µm and 3µm. The current density was applied to the on chip interconnects marked yellow and green.

The mass flux of SAC bumps is magnitudes higher compared to µ-bumps. Due to this they have a higher EM risk compared to the µ-bumps. Also the Cu interconnects connecting the bumps show a EM risk comparable to values calculated in the µ-bump phases itself. The thinner the interconnect is the higher the mass flux divergence is determined. Due to this the design of the interconnects have to be considered concerning EM risk in future 3-D applications as well.

FIGURE 5. MODEL OF A µ-BUMP.

FIGURE 6. MASS FLUX DIVERGENCE DISTRIBUTION IN THE CONNECTING CU-INTERCONNECTS. A) THIN AND B) THICK INTERCONNECT.

Conclusions The finite element analysis of TSV or µ-bumps provides an insight into local temperatures and stress distributions with the possibility of mass flux divergence calculation. This helps to predict weak links in the structures and allows an increase of the reliability during the design phase and to decrease costs and avoid potentially necessarily re-designs.

REFERENCES

[1]

Barnat, S.; Frémont, H.; et.al.: “Design for reliability: Thermo-mechanical analyses of Stress in Through Silicon Via”, in Proc. IEEE - EuroSimE (2010)..

[2]

Meinshausen, L.; Weide-Zaage, K.; Fremont, H.: „Electro- and Thermomigration induced Failure Mechanisms in Package on Package”, Microelectronic Reliability, Vol. 52, No. 12 (2012), pp. 2889-2906.

[3]

Weide-Zaage, Kirsten: “Exemplified calculation of stress migration in a 90nm node via structure”, in Proc. IEEE-EuroSimE

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(2010).

[4]

Lo, W.-C.; Chen, Y.-H.; et.al: TSV and 3D Wafer Bonding Technologies For Advanced Stacking System and Application at ITRI, Symposium on VLSI Technology Digest of Technical Papers, (2009), pp. 70-71.

[5]

Kitada, H.; Maeda, N.; et.al.: Development of Low Temperature Dielectrics down to 150°C for Multiple TSVs Structure with Wafer-on-Wafer (WOW) Technology, in Proc. IEEE- CMPT Tokyo (2010).

[6]

Weide-Zaage, Kirsten: Finite Element Analysis - New Trends and Developments" edited by Farzad Ebrahimi, ISBN 978953-51-0769-9 Intech-open.

[7]

Labie, R.; et. al, Reliability testing of Cu-Sn intermetallic micro-bump interconnections for 3D-device stacking”, in Proc.

IEEE ESTC, Berlin, (2010)

Kirsten Weide-Zaage is senior lecturer (Privatdozent) in the field of microelectronics at the Faculty of Electrical Engineering and Computer Science of the Gottfried Wilhelm Leibniz Universität in Hannover, Germany. She studied Physics with main topic Biophysics and made her PhD in Electrical Engineering. She is working since 1988 at the Faculty of Electrical Engineering and Computer Science from 1991 until 2014 at the Information Technology Laboratory as researcher and leader of the simulation group ‘Robust Electronics’ in the field interconnect and package reliability. Since 2015 she moved with her renamed group ‘Reliability: Simulation and Risk Analysis’ to the Institute of Microelectronic Systems, Architectures and System Section.

She is author of more than 80 scientific articles, including journal and conference publications, book chapters, a book and invited papers.

PD Dr.-Ing. Weide-Zaage is member of IEEE, VDE, ITG Group 8.5.6, and SMTA. Aymen Moujbani received his Diploma in Electrical Engeniering 2013 at the Universität Hannover. He is research engineer and Phd student in the ‘Reliability: Simulation and Risk Analysis’ at the Institute of Microelectronic Systems, Architectures and System Section.