Simulation of µ-Bump and TSV in 3-D Integration K. Weide-Zaage, A. Moujbani RESRI Group IMS-AS, Leibniz Universität Hannover, Hannover, 30655, Germany weide-zaage@ims.uni-hannover.de; moujbani@ims.uni-hannover.de Abstract The reduction of package and chip size by the need of cost reduction on one hand and the need of high voltage metallization on chip for power applications on the other hand the thermal electrical-mechanical management concerning the reliability becomes more and more critical. Breakdown failures due to mechanical stress, moisture uptake, migration effects caused by current crowding, temperature gradients due to Joule heating and stress gradients and intermetallic phase growth have an increasing importance. With the help of simulations the weakest links as well as locations with high thermal electrical and mechanical loads can be determined. This will be shown for selected examples. Keywords Simulation; Reliability; 3D-Integration; Migration; Mechanical Stress
Introduction The increase of high integration of chip and package leads to problems in system on chip (SoC) development influencing the costs and the time-to-market negatively. The system complexity results in integration of analog and digital components on a single chip and the use of new packaging concepts. The environment as well as new materials like Pb-free solder material, the use of organic materials and new dielectrics influence the reliability and quality of the devices and systems and can yield in the worst case to a complete re-design (Figure 1). One example in conjunction with chip package interaction (CPI) is the structural integrity for Cu/low-k ICs during fabrication and the integration into high-density flip-chip package. Caused by the thermo-mechanical deformation due to the CTE mismatch between the silicon die and the organic substrate in the package high mechanical stress occurs. This leads to intrinsic stress and strain in the structures provoked also by different processing temperatures.
FIGURE 1. RELIABILITY; QUALITY AND LAYOUT DEPANDENCE OF SOME PHYSICAL FAILURES IN THE DEVICE AND COMPONENTS.
One possible solution new packaging concepts is the usage of through silicon via (TSV). Several problems can occur in the active region (the transistor region) of the chip. This leads to the definition of keep-out-zones (KOZ) International Journal of Engineering Practical Research, Vol. 4 No. 1-April 2015 2326-5914/15/01 079-04 © 2015 DEStech Publications, Inc. doi: 10.12783/ijepr.2015.0401.16
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