A Linear Model for Characterizing Transient Behaviour in Wide Bandgap Semiconductor‐ based Switching

International Journal of Automation and Power Engineering, Volume 5 2016 www.ijape.org doi: 10.14355/ijape.2016.05.001

A Linear Model for Characterizing Transient Behaviour in Wide Bandgap Semiconductor‐ based Switching Circuits Raghav Khanna 1*, Ansel Barchowsky 2, Andrew A. Amrhein2, William E. Stanchina2, Gregory F. Reed2, and Zhi‐Hong Mao2 Electrical Engineering and Computer Science Department, University of Toledo, 2008 Nitschke Hall, OH, 43606

1

Electrical and Computer Engineering Department, University of Pittsburgh, 1238 Benedum Hall, Pittsburgh, PA 15261 2

*

Raghav.Khanna@utoledo.edu

Abstract This paper presents a linear model for characterizing transient behavior in power conversion circuits that use wide bandgap semiconductors. It details analytical and experimental characterization of the circuit‐level transient phenomena affecting the performance of wide bandgap (WBG) semiconductors. Specifically observed behaviors including voltage overshoot, ringing, and false turn‐on are analyzed using equivalent linear circuit models supplemented with experimental characterization. The effect that the parasitic device capacitances have on each of these transient events is also investigated. In order for WBG semiconductor devices to deliver their full performance potential of significantly enhancing next generation power electronic systems, the aforementioned transient characteristics must be eliminated. Due to the agreement between the models’ predicted results and experimental waveforms, the work presented here lays the foundation for optimizing the transient performance of power conversion circuits using WBG semiconductor devices.

Keywords MOSFET; Synchronous Buck Converter; Transient Switching Losses; WBG Semiconductors; Linear Model

Introduction Future generations of power electronic circuits will require high conversion efficiency over a smaller operating volume, particularly in renewable energy and electric vehicular applications. To meet these forthcoming challenges, continued improvement on power switching transistor technology is essential [1]. Wide bandgap (WBG) semiconductors based on silicon carbide (SiC) and gallium nitride (GaN) are promising transistor technologies for enhancing the performance of next generation power electronic circuits. Both SiC and GaN have been shown to maintain superior performance in high switching frequency applications, thereby enabling the use of smaller filter components within the converter topology, thus leading to a reduction in power conversion volume. Additionally, both semiconductors can sustain relatively high operating temperatures, making them particularly attractive in renewable energy and electric vehicular applications [2]. In spite of the many theoretical advantages that SiC and GaN possess over conventional power switching transistors, considerable technological readiness limitations have hindered their widespread adoption. For example, at the device physics level, GaN transistors have demonstrated several undesirable phenomena due to “electron‐trapping,” “punch‐through,” and substrate lattice mismatches etc.

[3]. At the device circuits level, the fast switching capability of GaN and SiC has led to detrimental transient behaviour such as “overshoot,” “ringing,” and “false turn‐on” [4‐8]. In order for WBG semiconductors to deliver their full potential of enhancing forthcoming power electronic systems, the aforementioned unfavourable characteristics of GaN and SiC must be mitigated.

This paper presents analytical linear modeling techniques that include the circuit‐level transient phenomena arising from the use of SiC MOSFETs and WBG semiconductors in general. First, a high dv/dt test circuit is proposed for evaluating the effect of the parasitic device capacitances on overshoot, ringing, and false turn‐on (with more focus on false turn‐on). Initially, the test circuit is analyzed using semiconductor equivalent circuit modeling techniques in the frequency domain. The analytical results are then supplemented with experimental

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results which validate the model’s predictions. Second, the SiC MOSFET is implemented both analytically and experimentally in a synchronous buck converter and a classic power conversion circuit where transient high dv/dt phenomena are often observed. As device operating capabilities continue to increase, the experimentally validated analytical results in this paper can be used to aid in the design of future versions of WBG semiconductors. This analytical tool for device optimization is a key result.

Analytical semiconductor device models such as the one reported here are advantageous for evaluating both the benefits and limitations of WBG semiconductor based power conversion systems. Generally, two types of analytical models have been utilized to assess device performance. The first type is the physics‐based approach where the physical parameters of the device serve as inputs to the model [9], [10]. In [11], a physics‐based model for a virtual silicon (Si) based MOSFET was created to measure the effect of the device’s output capacitance on its switching losses. The results from the virtual model were confirmed by experimentally varying the output capacitance of the MOSFET and measuring the resulting switching losses. The physics‐based approach has been recently applied to GaN transistor technology [12]. In general, the results obtained from the physics‐based models match the experimental results, but at the expense of increased computation times [13].

The second type of analytical device model is the equivalent circuit model derived to reproduce dynamic behaviours of the device. For example, [14] and [15] presented comprehensive equivalent circuit models for a transistor which included the parasitic inductances of the device. These detailed, nonlinear models offered accurate description of the device behaviour during various stages of the switching period. However, due to the “curse of dimensionality,” these models may experience challenges when integrated into larger‐scale circuits and systems.

Even for a converter, it has been considerably complex to construct a full‐scale circuit model consisting of detailed device models within the converter topology, not to mention those power electronic circuits with multiple switching devices [16].

This paper is aimed to derive relatively simple linear equivalent circuit models that can provide quick insights on transient behaviour of WBG semiconductors implemented in practical circuits. These approximate models with reduced complexity and better scalability can be used to assess and predict the influence of the parasitic device capacitances on overshoot, ringing, and false turn‐on. It will be shown that the source of these detrimental characteristics is due to the low capacitance to inductance ratio in WBG semiconductors. Thus, our work provides a foundation for semiconductor device optimization. That is, the results of this paper can be utilized to optimize the size of certain device capacitances, so that switching losses can remain low while the aforementioned transient phenomena are mitigated. Alternatively, the results of the paper provide deeper insight on the extent to which the parasitic package and loop inductances need to be reduced in WBG semiconductor based circuits. Due to their inherently lower intrinsic capacitances, WBG semiconductors are able to switch faster than Si transistors. However, this apparent advantage forces the parasitic inductance in WBG‐based circuits to have a larger adverse effect on circuit performance, leading to the aforementioned second order transient effects. The results in this paper demonstrate how the loop inductance in WBG‐based circuits can have a more significant negative impact on circuit performance relative to the impact of the relatively comparable loop inductance in Si based circuits. While the research results to be reported here are based on characterization of a SiC MOSFET, many of the transient circuit‐ level effects discussed in this paper apply to GaN transistors as well.

Problem Context: Transients in WBG Semiconductors Voltage Overshoot The first transient characteristic to be described here is voltage overshoot. This event occurs when a terminal voltage on the device exceeds its maximum rated specification, causing failure of the device. To demonstrate this, consider the EPC2007 [17], a 100 V GaN device from Efficient Power Conversion ®. For full channel conductivity, the EPC2007 requires a gate‐source voltage of 5 V. At this voltage, the on‐resistance of the device is minimized.

However, it is also specified on the datasheet of the device that the maximum operating gate‐source voltage is 6 V. Thus, only one volt of safety margin is available between the desired steady‐state operating voltage and the maximum allowable voltage. Due to the fast switching capability of GaN, overshoot is often observed and is usually mitigated with added gate resistance. Although the added gate resistance keeps the device in its safe

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operating regime, it can slow the switching speed of the device and thus increase switching losses. To illustrate this, consider the commonly observed turn‐on‐characteristic of a device, vgs vs t as shown in Fig. 1. The gate resistance RG is varied with three values considered: RG1 < RG2 < RG3. When RG1 is used, the turn‐on characteristic is rapid, but the overshoot exceeds the maximum operating voltage of the device, thus causing failure. Conversely, when RG3 is used, the device is kept in its safe operating regime, but with reduced switching speed (efficiency). These observations can be illustrated quantitatively if one considers a “gate‐charging” model as shown in Fig. 2(a). The constituent components of the circuit elements in Fig. 2(a) are seen in Fig. 2(b). It should be pointed out that all the inductors seen in Fig. 2(b) make up “LEQ” seen in fig. 2(a). However, only CGS and CGD of Fig. 2(b) constitute the “CEQ” seen in Fig. 2(a). Fig 2(a) is an equivalent circuit of the device while charging to conduction. When vdrive is a step function (whose Laplace transform, vdrive(s) equals 1/s), vgs can be derived using frequency domain analysis and expressed as (the definition of all variables can be seen in Appendix Table I):

1   s2  C L 1 eq eq vgs ( s)   1 s  2 RG s s  Leq Ceq Leq 

   (1)   

FIG.1. TURN‐ON CHARACTERISTICS UNDER VARIOUS VALUES OF RG: RG1 < RG2 < RG3.

(a)

(b)

FIG. 2. (a) GATE CHARGING CIRCUIT. (b) CONSTITUENT COMPONENTS OF ELEMENTS SEEN IN GATE CHARGING CIRCUIT.

where s is the Laplace variable, vgs(s) is the Laplace transform of vgs(t), Ceq = CGS + CGD, and Leq = Lg +

Ls Ld . The Ls  Ld

denominator of (1) can then be compared with the canonical form of second‐order systems:

s 2  2n s  n2 (2) where  is the damping ratio and n is the natural frequency of the system. From inspection of (1) and (2), it can be

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seen that:

 

n 

RG 2

Ceq Leq

1 Leq Ceq

(3)

(4)

As reported in [8] and [18], WBG transistors traditionally have lower intrinsic capacitance thus making the damping ratio in (3) relatively small. Consequently, the voltage overshoot seen in WBG‐based conversion circuits can be significant and damaging. The example given here also applies to the drain‐source terminal voltage where maximum values are specified on device datasheets as well. It should be further noted that as for experimental optimization of the gate resistance, RG is standard practice in modern power electronic circuit design, particularly in synchronous converters. This paper lays a foundation for obtaining the optimal value analytically as opposed to experimentally, which can be time‐consuming and tedious.

Ringing The second transient characteristic examined here is ringing. This characteristic is described by repeated oscillations of a device’s voltage for an extended period of time. One example of the detrimental effect of ringing is during device turn‐off, as seen in Fig. 3. Due to the relatively low parasitic capacitances in WBG semiconductors, the ringing frequency seen in (4) is particularly high. As such, there is a possibility of a secondary turn‐on by the device during the transient ringing of the turn‐off sequence if the ringing voltage exceeds the threshold voltage, VTH [18]. Both GaN and SiC have relatively low threshold voltages, and therefore the risk of the secondary turn‐on during the turn‐off cycle is even greater. To damp out the ringing frequency, a higher RG is required, which again can increase switching losses.

FIG. 3. TURN‐OFF CHARACTERISTIC OF A DEVICE.

False Turn‐On To illustrate the mechanism of false turn‐on, we chose a first order circuit model for a transistor in its off state as shown in Fig. 4 [19]. Since the transistor is in its off‐state, there is no channel between its drain and source terminals, and the input gate signal is effectively at ground potential. If during power conversion operation a high dv/dt is induced on the drain terminal of the transistor in Fig. 4, a current will flow through the gate‐drain capacitance, CGD. In turn, a current flows out of the gate of the transistor and across the external gate resistor, RG. If the resulting voltage across RG exceeds the threshold voltage of the device, the transistor is forced into the conduction, spuriously leading to significant switching losses [20].

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FIG.4. FIRST ORDER CIRCUIT MODEL FOR TRANSISTOR IN OFF‐STATE [19].

Small signal modelling techniques can be applied, if the induced voltage on the gate‐source terminals is low enough (although sufficiently large to falsely turn the device on). In analysing the circuit in Fig. 4, the transfer function from vds to vgs can be expressed as follows, vgs ( s ) vds ( s )



sRG CGD (5) 1  sRG (CGD  CGS )

The Laplace variable “s” in a transfer function also corresponds to an operation of differentiation in the time domain. Therefore (5) offers insights about the dv/dt in the power conversion circuit. In WBG‐based power converters, the dv/dt is significantly high due to the very fast switching capability of GaN and SiC. This can make the susceptibility to false turn‐on higher in WBG based circuits. Furthermore, from (5), it can be seen that higher values of RG will induce a larger vgs during false turn‐on. It has been explained in previous sections that a larger RG may be necessary in WBG‐based circuits to damp out transient overshoot and oscillation, and thus tuning the value of RG to obtain optimal circuit behavior is particularly essential yet time‐consuming in WBG‐based power converters. Finally, the lower threshold voltage of WBG devices also makes them more vulnerable to high dv/dt induced false turn‐on effects; but on the other hand, WBG based devices have a low gate charge ratio, QGD to QGS which may prevent false turn‐on behavior [21]. These opposing effects point to the increased need for accurate device/circuit models such that circuit performance can be optimized through design simulation.

Having discussed three common transient phenomena particularly affecting the performance of WBG semiconductors, the goal of this paper is to model these characteristics with experimental validation. The results obtained from the analytical equivalent models can be used to optimize the design of next generation WBG semiconductors so that switching losses remain low while undesirable transient behavior is eliminated.

High dv/dt Test Circuit Modelling Approach As shown in Fig. 5(a), the proposed high dv/dt test circuit is utilized here to analytically and experimentally study transient behavior in an example 1200 V SiC MOSFET [22], from Powerex ®. The gate terminal of the MOSFET is grounded via an external gate resistor, RG. A square wave from a function generator is used to drive the drain terminal of the transistor via an external test resistance, RD. As shown in Fig. 5(b), the complete circuit model is prepared for Fig. 5(a), which includes all the parasitic components of the MOSFET as well as the parasitic inductance of the two resistors denoted as LRD and LRG. A rearrangement of the elements in Fig. 5(b) is shown in Fig. 5(c), where the MOSFET is in its off‐state and therefore there is no channel between its drain and source terminals.

It is desired to analytically model the behavior of the gate‐source and drain‐source voltages, where the generated square wave input is modeled as a unit step function. Since the intent is to investigate and analyze the dynamic response of the transistor, the device is operated at 50 V, well below its rated voltage level. This enables the use of the previously mentioned small signal modeling techniques. From analyzing the node currents in Fig. 5(c), Kirchhoff’s Current Law (KCL) can be used to obtain the following expressions (the definition and values for all variables can be seen in Appendix Table I and Table II):

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V

SQ

 VDS

sLRD  RD



VDS  V '

D

sLD

(6)

V DS  V D' ' ) sC  (V ' ) sC (7)  (V DS DS GD GD sL D ' ) sC  (V ' ) sC  (V GD GD GS GS

VG' (8) sLG  RG

VS'  (V ' ) sC DS  (V ' ) sC GS (9) DS GS sLS

V ' V G

sL

G

GS



V

GS

R  sL G

(10) RG

FIG. 5. (A) HIGH DV/DT TEST CIRCUIT. (B) TEST CIRCUIT RE‐DRAWN WITH PARASITICS. (C) EQUIVALENT TEST CIRCUIT WITH SIC MOSFET IN OFF‐STATE.

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In order to solve (6)‐(10) simultaneously, the step response for the gate‐source and drain‐source voltages can be obtained. These modeled results are shown in Figs. 6 and 7 with their experimental counterparts plotted simultaneously with the analytical data. Both analytical figures show relatively good agreement with their experimental counterparts. As seen in Fig. 6, the gate‐source voltage rises rapidly to approximately 3 V during the false turn‐on and then oscillates around 0 V for approximately 500 ns before settling. The minimum threshold voltage of the SiC MOSFET is 1.5 V, and therefore false turn‐on would occur for some of these devices (since the threshold voltage of similar devices can vary). The parasitic inductance values used (as shown in the in Appendix) were estimated by measuring each of the dynamic terminal switching currents at known voltages and using V = L*di/dt.

FIG. 6. ANALYTICAL AND EXPERIMENTAL STEP RESPONSE FOR VGS.

FIG. 7. ANALYTICAL AND EXPERIMENTAL STEP RESPONSE FOR VDS.

Fig. 7 shows that the drain‐source voltage rises and oscillates for approximately 500 ns before settling at 50 V. The minor discrepancies between the analytical and experimental waveforms can be attributed to the linear modeling of the parasitic device capacitances. In reality, the capacitances vary non‐linearly with both the drain‐source and gate‐source voltages. Here, we slightly sacrifice accuracy to achieve significant reduction of the model complexity.

In the proposed analytical model, the frequency domain expression for the drain source voltage consists of a damping ratio  and natural frequency n . Figs. 8(a) and 8(b) show how each of the capacitances of the SiC MOSFET affects  and n . This analysis was accomplished by individually varying each capacitance in the model and consequently evaluating the system’s new  and n . The trends shown in Figs. 8 provide a better picture

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about how each capacitance affects the overshoot, ringing, rise time, and settling time of the drain‐source voltage.

As these metrics significantly influence switching loss and detrimental transient loss, the data seen in Figs. 8 provide a pathway to device parameter optimization.

(a) (b)

FIG. 8. DAMPING RATIO AND NATURAL FREQUENCY VS CAPACITANCES. (a) DAMPING RATIO. (b) NATURAL FREQUENCY.

Effect of CGS on Gate‐Source Voltage To further demonstrate the model’s validity, it was desired to assess the effect of the gate‐source capacitance on the magnitude of the induced gate‐source voltage. Seen from the analysis of the transfer function in (5), it can be inferred that large values of CGS can suppress the magnitude of the induced gate‐source voltage during false turn‐ on. Fig. 9 shows the analytical model’s predicted gate‐source voltage when the value of CGS increases to 30 nF. The experimental counterpart is also shown in Fig. 9. To experimentally obtain 30 nF of gate‐source capacitance, a 19 nF capacitor was placed across the gate and source terminals of the SiC MOSFET. This external capacitance was effectively in parallel with the device’s intrinsic CGS of 11 nF. Therefore, the total CGS is 30 nF. As seen in Fig. 9, reasonable agreement is obtained in the trend and behavior of the induced gate‐source voltage during false turn‐on.

The magnitude of the voltage is now approximately 1 V, whereas previously in Fig. 6 it was shown to be 3 V under nominal conditions. This shows the advantage of CGS in suppressing the magnitude of the induced gate‐source voltage during false turn‐on. It should be noted that higher values of CGS would lead to the increasing switching losses (for a given peak gate drive current) during intended turn‐on of the device, thereby pointing to the need of parameter optimization in WBG‐based power conversion circuits which contain high dv/dt effects.

FIG. 9. ANALYTICAL AND EXPERIMENTAL INDUCED GATE‐SOURCE VOLTAGE WITH CGS = 30 NF.

The data reported in this section are intended to aid in the design of future generation WBG semiconductor devices.

The linear equivalent circuit models shown here can be used to optimize the area and layout of forthcoming WBG devices so that certain capacitances can be retained to reduce detrimental transient behavior while keeping switching losses minimal. In the next section, a practical example for such an optimization problem is presented using the synchronous buck converter, a classic low voltage power conversion circuit [23], [24].

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Analytical and Experimental Transient Characterization of the Synchronous Buck Converter The Synchronous Buck Converter The synchronous buck converter seen in Fig. 10 contains a “high side” transistor, Q1, and a “low side” transistor, Q2.

The synchronous buck converter has the advantage of significantly reducing the conduction losses observed in the conventional buck converter, which uses a diode instead of Q2. However, due to the added switching dynamics contributed by the additional transistor in the synchronous buck converter, several undesirable transient phenomena can be observed. In particular, during the rapid turn‐on of Q1, while Q2 is off, the high dv/dt induced on the drain‐terminal of Q2 can lead to a false turn‐on in addition to ringing and overshoot in various signals of the converter. It is desired to characterize these events both analytically and experimentally, thus laying the foundation for system optimization. To understand the occurrence of false turn‐on in Q2, the synchronous buck converter in Fig. 10 was experimentally constructed and tested, where the previously discussed SiC MOSFET served as Q2. The input voltage was 50 V with 50% duty cycle resulting in an output voltage of approximately 25 V. Again, the device is operated far from its maximum ratings so that small signal modeling techniques can be applied. The switching frequency was 10 kHz.

FIG. 10 . THE SYNCHRONOUS BUCK CONVERTER.

An analytical model would then be developed around the measured data from the circuit. During the interval where Q1 is at the point of turn‐on, voltage measurements were taken for vgs1, vds2, and vgs2, which can be seen in Fig. 11. The location for the three aforementioned signals within the converter is illustrated in Fig. 12. It should be noted that the driving signal on Q2 is at ground potential because the measurement is taken when Q2 is off during the turn‐on of Q1. As observed in Fig. 11, vgs1 initially increased towards its steady‐state value with no oscillation.

However, as the channel forms in Q1, the impedance of Q2 becomes apparent to Q1. This can be observed as the drop and subsequent transient recovery of vgs1 and corresponding dramatic rise in vds2. Prior to reaching its steady‐ state value at approximately 400 ns, vds2 shows observable overshoot and ringing in its behavior. Furthermore, the quick rise in vds2 corresponds to a rapid transient response in vgs2, which is sufficiently large enough to produce false turn‐on in Q2. As shown in the waveform vgs2, its induced magnitude is approximately 2V, which is higher than the SiC MOSFET’s minimum threshold voltage of 1.5 V, therefore increasing the likelihood of false turn‐on.

The goal then becomes to model this phenomenon analytically to predict false turn‐on and optimize system parasitics. The following sections will therefore analytically detail the stages of false turn‐on in the synchronous buck converter where the results will match the experimental waveforms given here, thereby providing a path towards system optimization.

FIG. 11. EXPERIMENTAL WAVEFORMS FOR TRANSIENTS IN SYNCHRONOUS BUCK CONVERTER, 10:1 TESTING PROBES WERE USED.

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FIG. 12. TEST POINTS ACROSS SYNCHRONOUS BUCK CONVERTER FOR VGS1, VDS2, VGS2.

Analytical Synchronous Buck Converter: Stages of False Turn‐on.

Just prior to false turn‐on occurring, vdrive1 begins to charge the gate of Q1 so that vgs1 increases towards VTH1. Once VTH1 is attained, a channel forms gradually across the drain and source terminals of Q1. During the formation of Q1 channel, CDS1 continuously discharges causing vds1 to decrease. When the channel is completely formed, vds1 reaches its minimum steady‐state value (approximately zero, depending on the value of RON1). The equivalent circuit for the entire synchronous buck converter at this particular moment is shown in Fig. 13(a) (see Appendix Table I and Table III for component values and definitions). A small and fast Q1 was used in order to obtain higher dv/dt and purposely observe and characterize the false turn‐on behavior. A simplified version of Fig. 13(a) is shown in Fig. 13(b) where all of the circuit’s pertinent node voltages are clearly indicated for Q1. Similarly, a simplified version of Fig. 13(a) is shown in Fig. 13(c), where the pertinent node voltages are clearly indicated for Q2. In Fig. 13(b), Zeq represents the equivalent impedance of Q2 in its off‐state in parallel with the output of the converter. It should be noted that at the interval under investigation, CDS1 has been completely discharged and has thus been removed from the circuit of Fig. 13. From the analysis of Fig. 13(b), the equations seen in (11)‐(16) (using KCL) can be used to analytically create the experimental waveform for vgs1 seen in Fig. 11:

(a)

(b)

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(c) FIG. 13. EQUIVALENT CIRCUITS FOR SYNCHRONOUS BUCK CONVERTER IMMEDIATELY AFTER FORMATION OF Q1 CHANNEL. (a) FULL CONVERTER MODEL WITH EQUIVALENT CIRCUIT MODELS FOR Q1 AND Q2. (b) SIMPLIFIED VERSION OF FIG. 13(A) WITH NODE VOLTAGES INDICATED FOR Q1. (c) EQUIVALENT CIRCUIT FOR ZEQ OF FIG. 13(b) WITH NODE VOLTAGES INDICATED FOR Q2.

* vds2  vdrive1  vg1

R1  sL2

* * *  sC2 (vd1  vg1 )  sC3 (vg1  vs1* ) (11)

vds2  vdrive1  vg1 R1



* vg1  vg1

sL2

(12)

* VDC  vd1 v*  v * * *  d1 s1  sC2 (vd1  vg1 ) (13) sL1 R4

* vd1  vs1* v*  v * + sC3 (vg1  vs1* ) = s1 ds2 (14) RON1 sLs1 * vs1*  vds2 vds2  vgs1  vg1 vds2 (15)   sL3 sL2 Z eq

vgs1  vg1  vds2 . (16)

In order to solve (11)‐(16) simultaneously, the step response for vgs1 is obtained (Fig. 14). The step response for vgs1 is derived by treating both VDC and vdrive1 as step‐input voltages, and thus invoking the superposition theorem. It should be noted that in practice, VDC is always on, and is therefore not a step function. However, modeling VDC as a step function simulates the formation of the Q1 channel and the resulting near‐instantaneous effect that VDC has on the rest of the circuit. When comparing the analytical step response for vgs1 in Fig. 14 with its experimental counterpart also in Fig. 14, we can see that reasonable agreement is obtained. Here, the experimental data were taken from Fig. 11 and plotted simultaneously with the analytical results seen in Fig. 14. Both waveforms show significant oscillation with no overshoot above the steady‐state value of 14 V. The trend and phase of the oscillations in both waveforms are also similar. Again, the minor discrepancies in modeled and experimental behavior can be attributed to the linear modeling of the parasitic device capacitances.

FIG. 14. ANALYTICAL AND EXPERIMENTAL WAVEFORM VGS1.

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As previously mentioned, during and after the channel formation across Q1, current flows into the parasitic components of Q2, seen in Fig. 13(a) and Fig. 13(c), causing vds2 to increase. To find the step response for vds2, the relations (11)‐(16) remain relatively un‐changed with the exception that vdrive1 is no longer considered an input as it is assumed to have reached its steady‐state value. Thus, to derive the proper response for vds2, only VDC is considered as a step input voltage. As a result, (11) and (12) take on the form seen in (17) and (18), respectively, while (13)‐(16) remain the same: * vds2  vg1

R1  sL2

* * *  sC2 (vd1  vg1 )  sC3 (vg1  vs1* ) (17)

vds2  vg1 R1



* vg1  vg1

sL2

(18)

In order to solve (13)‐(18) simultaneously, the step response for vds2 can be obtained as seen in Fig. 15. When comparing the analytical vds2 with its experimental counterpart seen in Fig. 15, adequate agreement is again obtained. As seen in both figures, vds2 rises, overshoots, and undershoots its steady‐state value with some ringing before settling at approximately 400 ns.

FIG. 15. ANALYTICAL AND EXPERIMENTAL WAVEFORM VDS2.

Due to the rapid increase in vds2, the dv/dt seen at the drain terminal of Q2 is high, thus inducing a current through CGD2. Consequently, a voltage will develop across RG2 despite that the driving signal on Q2 is effectively at ground potential. If the voltage across RG2 exceeds VTH2, the device is forced into conduction. To model these transitions, the circuit in Fig. 13(c) is utilized, where vds2 is a known quantity previously found. This leads to: * vds2  vd2 * * *  sCds2 (vd2  vs2* )  sCgd2 (vd2  vg2 ) (19) sLd2 * * sCgd2 (vd2  vg2 )

* vg2

Rg2  sLg2

*  sCgs2 (vg2  vs2* ) (20)

* * sCds2 (vd2  vs2* ) + sCgs2 (vg2  vs2* ) = *  vgs2 vg2

sLg2



vgs2 Rg2

vs2* (21) sLs2

(22)

vds2 vgs2 vgs2 (23)  VDC vds2 VDC In order to solve (19)‐(23) simultaneously, the step response for vgs2 can be obtained as seen in Fig. 16. The experimental waveform for vgs2 is also seen in Fig. 16, and again reasonable agreement is obtained. Both waveforms oscillate above and below zero for 400 ns before settling after approximately 500 ns. The magnitude of the induced voltage is 2 V, which is larger than VTH2, which is 1.5 V. Thus, the frequency domain approach for modeling transients introduced in Section III has been applied to a practical converter here, and is utilized to reproduce experimental waveforms.

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FIG. 16. ANALYTICAL AND EXPERIMENTAL WAVEFORM VGS2.

The validated modelling techniques shown here demonstrate a means to optimize the layout and configuration of the next generation power electronic circuits. Optimization techniques can lead to the identification and selection of ideal values for RG and certain device capacitances. Furthermore, the model shown here allows designers to analytically adjust certain inductance values to obtain a desired outcome such as mitigation of false turn‐on or ringing. This can enable designers to target maximum values of parasitic inductance to obtain optimal device performance.

Conclusion Owing to their high breakdown potential, high electron mobility and faster switching capabilities, WBG semiconductor devices are well poised to enhance the performance of next generation power electronic systems.

However, due to several technological readiness shortcomings at both the device physics and circuits levels, WBG devices have not been able to deliver their full potential. Presented here was a modeling approach based on frequency domain analysis for characterizing the transient phenomena affecting the circuit performance of WBG semiconductor devices. The source of these transient phenomena can be attributed to the relatively low capacitance‐to‐inductance ratio in WBG‐based power conversion circuits. While generally considered to be a beneficial feature, it has been shown here that this low ratio can lead to undesirable and potentially detrimental behavior. Considerable efforts continue to be made towards reducing the parasitic loop inductance in WBG‐based power conversion circuits in order to offset the low ratio. Our work offers a different approach, laying the foundation for optimization of the parasitic device capacitances. The models shown here can be used to optimize the area and layout of next generation semiconductor devices so that switching losses can remain minimal while retaining enough capacitance to eliminate undesirable transient phenomena. Finally, the linear model and methods in this paper can serve as a basis for design optimization techniques in other more complex converters containing faster WBG devices and high dv/dt effects.

REFERENCES

[1]

H. Zhang and L. M. Tolbert, ʺEfficiency impact of SiC power electronics for modern wind turbine full scale frequency converter,ʺ IEEE Transactions on Industrial Electronics, vol. 58, no. 1, pp. 21‐27, January 2011.

[2] M. Gurfinkel, H. D. Xiong, K.P. Cheung, J. S. Suehle, J. B. Bernstein, Y. Shapira, A. J. Lelis, D. Habersat, and N. Goldsman, ʺCharacterization of transient gate oxide trapping in SiC MOSFETs using fast I‐V techniques,ʺ IEEE Transactions on Electron Devices, vol. 55, no. 8, pp. 2004‐2012, Aug. 2008.

[3] A. Nakajima, K. Takao, and H. Ohashi, ʺGaN power transistor modeling for high‐speed converter circuit design,ʺ IEEE Transactions on Electron Devices, vol. 60, no. 2, pp. 646‐651, February 2013.

[4] D. Reusch and J. Strydom, ʺUnderstanding the effect of PCB layout on circuit performance in a high‐frequency gallium‐ nitride based point of load converter,ʺ IEEE Transactions on Power Electronics, vol. 29, no.4, pp. 2008‐2015, April 2014.

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[5] Z. Liu, X. Huang, F. C. Lee, and Q. Li, ʺPackage parasitic inductance extraction and simulation model development for the high‐voltage cascode GaN HEMT,ʺ IEEE Transactions on Power Electronics, vol. 29, no.4, pp. 1977‐1985, April 2014.

[6] B. Hughes, J. Lazar, S. Hulsey, D. Zehnder, D. Matic, and K. Boutros, ʺGaN HFET switching characterstics at 350V/2A synchronous boost conveter performance at 1 MHz,ʺ in IEEE Applied Power Electronics Conference, Orlando, Fl, 2012, pp.

2506‐2508.

[7] R. Khanna, A. A. Amrhein, W. E. Stanchina, G. F. Reed, and Z.‐H. Mao, ʺAn analytical model for evaluating the influence of device parastics on Cdv/dt induced false turn‐on in SiC MOSFETs,ʺ in Applied Power Electronics Conference, Long Beach, CA, 2013, pp. 518‐525.

[8] A. Lemmon, M. Mazolla, J. Gafford, and C. Parker, ʺStability considerations for silicon carbide field‐effect transistors ʺ IEEE Transactions on Power Electronics, vol. 28, no.10, pp. 4453‐4459, October Oct. 2013.

[9] T. R. McNutt, A. R. Hefner, H.A. Mantooth, D. Berning, and S.‐H. Ryu, ʺSilicon carbide power MOSFET model and parameter extraction sequence,ʺ IEEE Transactions on Power Electronics, vol. 22, no.2, pp. 353‐363, March 2007.

[10] A. R. Hefner, ʺModeling buffer layer IGBTʹs for circuit simulation,ʺ IEEE Transactions on Power Electronics, vol. 10, no.2, pp.

111‐123, March 1995.

[11] Y. Xiong, S. Sun, H. Jia, P. Shea, and Z. J. Shen, ʺNew physical insights on power MOSFET switching losses,ʺ IEEE Transactions on Power Electronics, vol. 24, no.2, pp. 525‐531, February 2009.

[12] M. Esposto, A. Chini, and S. Rajan, ʺAnalytical model for power switching GaN‐based HEMT design,ʺ IEEE Transactions on Electron Devices, vol. 58, no. 5, pp. 1456‐1461, May 2011.

[13] Z. Chen, D. Boroyevich, R. Burgos, and F. Wang, ʺCharacterization and modeling of 1.2 kV, 20A SiC MOSFETs,ʺ in 2009 IEEE Energy Conversion Congress and Exposition, San Jose, CA, USA, September 2009, pp. 1480‐1487.

[14] M. Rodriguez, A. Rodriguez, P. F. Miaja, D. G. Lamar, and J. S. Zuniga, ʺAn insight into the switching process of power MOSFETs: an improved analytical losses model,ʺ IEEE Transactions on Power Electronics, vol. 25, no.6, pp. 1626‐1640, June 2010.

[15] Y. Ren, M. Xu, J. Zhou, and F. C. Lee, ʺAnalytical loss model of power MOSFET,ʺ IEEE Transactions on Power Electronics, vol.

21, no.2, pp. 310‐319, March 2006.

[16] J. Brown, ʺModeling the switching performance of a MOSFET in the high side of a non‐isolated buck converter,ʺ IEEE Transactions on Power Electronics, vol. 21, no.1, pp. 3‐10, January 2006.

[17] EPC 2007. Available: http://epc‐co.com/epc/documents/datasheets/EPC2007_datasheet_final.pdf [18] A. Lemmon, M. Mazzola, J. Gafford, and C. Parker, ʺInstability in half‐bridge circuits with wide bandgap transistors,ʺ IEEE Transactions on Power Electronics, vol. 29, no.5, pp. 2380‐2392, May 2014.

[19] T. Wu, ʺCdv/dt induced turn‐on in synchronous buck regulators,ʺ Technical Report, International Rectifier [Online].

Available: http:///www.irf.com, 2007.

[20] Q. Zhao and G. Stojcic, ʺCharacterization of Cdv/dt induced power loss in synchronous buck DC‐DC converters,ʺ IEEE Transactions on Power electronics, vol. 22, no.4, pp. 1508‐1513, July 2007.

[21] R. K. Burra, S. K. Mazumeder, and R. Huang, ʺDV/DT related spurious gate turn‐on of bidrectional switches in a high frequency cycloconverter,ʺ IEEE Transactions on power Electronics, vol. 20, no.3, pp. 1237‐1243, Nov. 2005.

[22] Powerex SiC MOSFET Datasheet. Available: http://www.pwrx.com/pwrx/docs/qjd1210007.pdf [23] D. K. H.N. Nagaraja and A. Petra, ʺDesign principles of a symmetrically coupled inductor structure for multiphase synchronous buck converters,ʺ IEEE Transactions on Industrial Electronics, vol. 58, no.3, pp. 988‐997, March 2011.

[24] R. Pilawa‐Podgurski and D. J. Perreault, ʺSubmodule integrated distributed maximum power point tracking for solar photovoltaic applications,ʺ IEEE Transactions on Power Electronics, vol. 28, no.6, pp. 2957‐2967, June 2013.

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Appendix TABLE I: ALL SECTIONS OF PAPER

TABLE II: FOR SECTION 3.

Circuit Name

Full Definition

Parameter

Value

CGD

gate‐drain capacitance

CGS

gate‐source capacitance

CDS

drain‐source capacitance

LG

parasitic gate inductance

LD

parasitic drain inductance

LS

parasitic source inductance

RON

transistor on‐state resistance

CDS CGD CGS LD LG LS LRD LRG RD RG VSQ

1.0 nF 0.1 nF, 10.1 nF 15 nH 15 nH 1 nH 50 nH 50 nH 5 Ω 5 Ω 50 V

TABLE III. FOR SECTION 4.

MODEL VARIABLE

PARAMETER

VALUE

C1 C2 C3 C4 C5 C6 C7 L1 L2 L3 L4 L5 L6 L7 R1 R2 R3 R4 VDC VO

CDS1 CGD1 CGS1 CDS2 CGD2 CGS2 CO (OUTPUT) LD1 LG1 LS1 LD2 LG2 LS2 LO (OUTPUT) RG1 RG2 RO (OUTPUT) RON1 VDC VO

D

DUTY CYCLE

FS

SWITCHING FREQUENCY

0.170 NF 0.0077 NF 1.022 NF 1.0 NF 0.1 NF, 10.1 NF 10 MF 1 NH 1 NH 1 NH 15 NH 15 NH 1 NH 2.5 MH 5 Ω 5 Ω 10 Ω 0.5 Ω 50 V 25 V

0.5

10 KHZ

Dr. Raghav Khanna received his PhD degree from the University of Pittsburgh in 2014. His research interests are in characterizing and modeling wide bandgap semiconductors for applications in next generation power electronic converters, particularly in renewable energy and electric vehicle circuits.

Raghav has also developed novel maximum power point tracking control algorithms for photovoltaic power conversion circuits. He has first authored publications in IEEE Transactions on Power Electronics, in addition to prestigious conferences such as the Energy Conversion Congress and Exposition (ECCE) as well as the Applied Power Electronics Conference (APEC). For his presentation on transient behavior on SiC MOSFETs, Raghav won the Best Presentation Award at APEC 2013. He has also served as an invited peer reviewer for IEEE Transactions on Power Electronics and IEEE Transactions on Industrial Electronics.

In 2013, Raghav worked at HRL Laboratories in Malibu, CA where he was directly involved with the development of GaN based battery chargers for electric vehicles. In the 2014‐2015 academic year, Raghav was a visiting assistant professor in the Electrical and Computer Engineering Department at Bucknell University. Recently, Raghav joined the Electrical Engineering and Computer Science Department at The University of Toledo to continue his research and teaching expertise in the areas of devices, power electronics, energy, and control systems. He is a member of IEEE and Power Electronics Society.

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Ansel Barchowsky is a PhD candidate at the University of Pittsburgh. He has developed a deep interest in the development of power electronics and their applications throughout electric power systems. He aims to apply his background in power grid studies, advanced control, and power electronics design to the development of novel power electronic technologies. In his research, Ansel aims to achieve new limits for high‐power density in both DC/DC and DC/AC converters, through the use of advanced topologies, adaptive control, and wide‐bandgap semiconductors.

Andrew A. Amrhein graduated from the University of Pittsburgh in May 2012 with a B.S. in Electrical Engineering and assisted in construction of test circuits for analyzing switching loss at University of Pittsburgh May 2015 through August 2015. While studying power electronics at Virginia Polytechnic Institute and State University, he researched new techniques and topologies for the induction heating of various metals at the Virginia Tech Future Energy Electronics Center June 2013 through May 2015. He graduated with a M.S. in Electrical Engineering from Virginia Polytechnic Institute and State University in June 2015 and is currently working in industry as a design engineer developing induction heating equipment for commercial cooking and food warming applications.

Dr. William E. Stanchina (Professor of Department of Electrical & Computer Engineering, Swanson School of Engineering, University of Pittsburgh). From 2005 through 2015, Bill was also Chair of the ECE Department. His research interests in recent years have included development of novel heterojunction electronic and optoelectronic devices and their application, e.g.: 

Wide bandgap semiconductor power transistors (e.g. GaN and SiC) – primarily modeling and characterization for compact, efficient power conversion circuits



Wide bandgap semiconductor nanowires – growth and transistor development



Point‐of‐contact medical diagnostics utilizing optoelectronic sensing

His recent teaching has included courses on semiconductor device theory, electronic circuit analysis and design, IC fabrication.

Prior to joining Pitt, Bill came from HRL Laboratories, LLC (previously known as the Hughes Research Laboratories, Malibu, CA) where he had been the Director of Microelectronics. Over 21 years at HRL Labs, he conducted research in basic semiconductor materials growth through development of microelectronic devices and IC fabrication processes (e.g. InP HBT IC technology). He has over 85 technical publications and 16 issued US patents. Bill received the PhD and MS in electrical engineering from the Univ. of Southern California and the BSEE from the Univ. of Notre Dame.

Gregory F. Reed (M’1985) is the Director of the University of Pittsburgh Center for Enegy, Director of the Electric Power Systems Laboratory in the Swanson School of Engineering at Pitt, and Professor of Electric Power Engineering in the Swanson School’s Electrical & Computer Engineering Department. He is also a member of the National Academies of Sciences and Engineeringʹs Energy Ambassador Program. His research interests, teaching activities, and related pursuits include advanced electric power grid and energy generation, transmission, and distribution system technologies; power electronics and control technologies (FACTS and HVDC); micro‐grids and DC infrastructure development, renewable energy systems and integration; smart grid technologies and applications; and energy storage. Dr. Reed has nearly 30 years of combined industry and academic experience in the electric power and energy arena, including engineering, research & development, and executive management positions throughout his career with the Consolidated Edison of New York, ABB Inc., Mitsubishi Electric Corp., and DNV‐KEMA. He is an active member of the IEEE Power & Energy Society and the American Society of Engineering Education. Dr. Reed earned his Ph.D, in electric power engineering from the University of Pittsburgh (1997), M.Eng. from Rensselaer Polytechnic Institute (1986), and B.S. from Gannon University (1985).

Zhi‐Hong Mao is an Associate Professor and William Kepler Whiteford Faculty Fellow in the Department of Electrical and Computer Engineering and Department of Bioengineering at the University of Pittsburgh, Pittsburgh, PA. His research interests include networked control systems and human‐in‐the‐loop control systems. He received his B.Eng. (1995), B.S. (1995), and M. Eng. (1998) degrees from Tsinghua University, Beijing, China, and S.M. (2000) and Ph.D. (2005) degrees from the Massachusetts Institute of Technology, Cambridge.

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