Journal of electronic design technology (vol5, issue2) by STM Journals Publication

Journal of Electronic Design Technology (JoEDT)

May-August 2014

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Journal of Electronic Design Technology (ISSN: 2321â&#x20AC;&#x201C; 4228) Focus and Scope Covers Electronics Circuits ? ? Electronics Theory ? Computer Aided Design (CAD) ? Analog Electronics ? Digital Signal Processors ? Mathematical methods in Electronics

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Dr. Pankaj Poddar

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Dr. Nandini Chatterjee Singh Associate Professor, National Brain Research Centre, Manesar, India.

STM Journal (s) Advisory Board & Editorial Board

Dr. Priyavrat Thareja

Dr. Rakesh Kumar

Head, Materials and Metallurgical Engineering department, PEC University of Technology, Chandigarh, India.

Assistant Professor, Department of Applied Chemistry, BIT Mesra, Patna, India.

Dr. Shankargouda Patil

Dr. Shrikant Balkisan Dhoot

Asst. Prof., Department of Oral Pathology, KLE Society's Institute of Dental Sciences, Bangalore, India.

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Prof. Subash Chandra Mishra

Prof. Sundara Ramaprabhu

Professor, Metallurgical & Materials Engineering Department, NIT, Rourkela, India.

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Prof. Yuwaraj Marotrao Ghugal Professor and Head Department, Govt. College of Engineering Station Road, Osmanpura, Aurangabad, India.

Prof. Sajal K. Paul Department of Electronics Engineering, Indian School of Mines Dhanbad-826004, India.

Editorial Board

Prof. Satyabrata Jit

Dr. Sanjay Lakshminarayanan

Professor, Department of Electronics Engineering, Indian Institute of Technology (BHU) Varanasi, India.

Associate Professor, M.S. Ramaiah Institute of Technology, MSR Nagar, Bangalore, India.

Prof. Sajal K. Paul

Dr. Sanket N. Bhavsa

Professor, Department of Electronics Engineering, Indian School of Mines, Dhanbad, India.

Professor & Head, Mechatronics Engineering Department, G H Patel College of Engineering & Technology, Valabh Vidyanagar, Anand, Gujarat, India.

Director's Desk

STM JOURNALS

I take the privilege to present the hard copy compilation for the [Volume 5 Issue (2)] of Journal of Electronic Design Technology (JoEDT). The intension of JoEDT is to create an atmosphere that stimulates creativeness, research and growth in the area of Electronic Design Technology. The development and growth of the mankind is the consequence of brilliant Research done by eminent Scientists and Engineers in every field. JoEDT provides an outlet for Research findings and reviews in areas of Electronic Design Technology found to be relevant for National and International recent developments & research initiative. The aim and scope of the Journal is to provide an academic medium and an important reference for the advancement and dissemination of Research results that support high level learning, teaching and research in the domain of Electronic Design Technology. Finally, I express my sincere gratitude and thanks to our Editorial/ Reviewer board and Authors for their continued support and invaluable contributions and suggestions in the form of authoring writeups/ reviewing and providing constructive comments for the advancement of the journals. With regards to their due continuous support and co-operation, we have been able to publish quality Research/Review findings for our customers base. I hope you will enjoy reading this issue and we welcome your feedback on any aspect of the Journal.

Dr. Archana Mehrotra Director STM Journals

Journal of Electronic Design Technology

Contents

1. Wireless Sensor Networks Simulation Sachin Gajjar, Mohanchur Sarkar, Kankar Dasgupta

2. Implementation of 2nd Order CMOS Gm-C IF Tuning Filter Operating at GSM and FM Band: Wireless System with Monte Carlo Analysis Kehul A. Shah, N. M. Devashrayee

3. Design and Simulation of Micro-cantilever for MEMS Applications Tanvi Chandel, Balwinder Singh

4. Analysis of LSDCCFF at 0.09 Âľm Technology Misbah Saad, Sangeeta Mangesh

Journal of Electronic Design Technology ISSN: 2229-6980 (online), ISSN: 2321-4228 (print) Volume 5, Issue 2 www.stmjournals.com

Wireless Sensor Networks Simulation Sachin Gajjar1*, Mohanchur Sarkar2, Kankar Dasgupta3 1

Dept. of Computer Science and Engg., Nirma University Ahmedabad, Gujarat, India Space Application Centre, Indian Space Research Organisation, Ahmedabad, Gujarat, India 3 Indian Institute of Space Science and Technology, Thiruvananthapuram, India

Abstract The formidable growth of Wireless Sensor Network (WSN) research has raised challenging issues of examining the micro behaviour of proposed protocol and carrying out its performance evaluation. The methodologies to realize this is: mathematical modelling; experimentation and simulation. For WSNs, experimentation has financial constraints and mathematical modelling at times requires deep expertise in mathematics. Thus simulation has become the first choice for research in WSNs. There are several researchers using simulators but there is limited number of simulation studies in the literature. To bridge the gap, this paper discusses the elements of WSN simulation, parameters of an ideal WSN Simulator and briefly describes the most significant simulation frameworks available. The selection of the simulation frameworks is based on their popularity, simulation results published in literature, important characteristics and features.

Keywords: Wireless sensor Network simulation, Simulators, Comparative review

Journal of Electronic Design Technology ISSN: 2229-6980 (online), ISSN: 2321-4228 (print) Volume 5, Issue 2 www.stmjournals.com

Implementation of 2nd Order CMOS Gm-C IF Tuning Filter Operating at GSM and FM Band: Wireless System with Monte Carlo Analysis Kehul A. Shah1*, N. M. Devashrayee2 1

Department of Electronics and Communication, SPCE, Visnagar, India Department of Electronics and Communication (VLSI Design), NIRMA University, India

Abstract Designed folded cascode OTA has a 52 dB DC gain and provides a unit gain bandwidth of around 400 MHz. Design of CMOS Gm-C 2nd order biquad filter implementation using OTA, operating at center frequency 70 and 10.6 MHz. The filter can be operated at center frequency of 70 MHz under 1.8 V power supply and is suitable for intermediate frequency (IF) range in most of the wireless systems operating at 900 MHz GSM and at 88â&#x20AC;&#x201C;108 MHz FM

Keywords: Folded cascode OTA, gm/ID methodology, active filters, S-parameter, smith chart, (OTA-C) filters, GSM, FM

Journal of Electronic Design Technology ISSN: 2229-6980 (online), ISSN: 2321-4228 (print) Volume 5, Issue 2 www.stmjournals.com

Design and Simulation of Micro-cantilever for MEMS Applications Tanvi Chandel*, Balwinder Singh Academic and Consultancy Services Division, Centre for Development of Advanced Computing, Mohali-160071, India Abstract Micro-cantilevers belong to MEMS set of devices and are often used for detection of forces in micromechanical sensors (e.g., pressure sensors and accelerometers) and probe for force sensor to atomic force microscope used as transducers, transport mechanisms, relays, switches, resonators, etc. This paper presents as to how the displacement of micro-cantilever is affected by the load applied to the micro-cantilever. The effect of width change on the displacement of the cantilever is also analyzed. The micro-cantilever is designed using COMSOL Multiphysics and the mathematical analysis of the effect of different loads and width change on the cantilever is done using MATLAB software. The analysis is done for different materials (polysilicon, tungsten and copper). Then the theoretical and simulated results are compared. It has been observed that the value of displacement increases with the increase with applied boundary load and decreases with the increase in the width of the cantilever.

Keywords: Micro-cantilever, MEMS, displacement, load, width

Journal of Electronic Design Technology ISSN: 2229-6980 (online), ISSN: 2321-4228 (print) Volume 5, Issue 2 www.stmjournals.com

Analysis of LSDCCFF at 0.09 µm Technology Misbah Saad*, Sangeeta Mangesh Department of Electronics Engineering, JSS Noida, India Abstract The traditional low swing differential conditional capture flip-flop (LSDCCFF) for LC resonant clock distribution network has wide range of applications but has poor power consumption. These characteristics can be improved by using the modified LSDCCFF. This paper presents the design of modified LSDCCFF with less delay and low operating power. The implementation of the circuit is done using LSDCCFF. By using voltage scaling technique, the average power consumption can be reduced. An analysis of the LSDCCFF is presented. The design has been implemented in 0.09 µm technology. The modified LSDCCFF exhibits a D-Q delay of 1.32 ns, and average power consumption of 8.87µw.

Keywords: Delay, flip-flop, low-swing, average power, SR latch