Journal of
Semiconductor Devices & Circuits May - August 2014
(JoSDC)
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Dr. Rakesh Kumar
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Sukumar Basu
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Aminul Islam Assistant Professor, Department of Electronics and Communication Engineering Birla Institute of Technology Mesra, Ranchi, Jharkhand, India.
Angsuman Sarkar Assistant Professor, Department of Electronics & Communication Engineering, Kalyani Government Engineering College, Nadia, West Bengal, India.
Anil Kumar Gupta Department of Electronics and Communication Engineering, National Institute of Technology Kurukshetra, India.
Ashok Kumar Goel Associate Professor, Department of Electrical & Computer Engineering, Michigan University, USA, United States.
Brajesh Kumar Kaushik Assistant Professor, Department of Electronics and Communication Engineering, Indian Institute of Technology-Roorkee, India.
D. Nirmal Department of Electronics and Communication Engineering, School of Electrical Sciences, Karunya University, Coimbatore, India.
Dinesh Pundalik Amalnerkar Executive Director Center for Materials for ElectronicsTechnology (C-MET) (Under Department of Information Technology ,Govt.Of India), India.
Gagan Khanduri Research Associate, Centre for Applied Research in Electronics Indian Institute of Technology, Delhi, India.
Maheswari Murali Department of Electronics and Communication Engineering,J.J College of Engineering and Technology Trichy, India.
Mohankumar Nagarajan Professor & Head, Department of PG Studies ECE IEEE EDS Madras Chair Engineering College Tiruvannamalai Tamil Nadu India.
Rupendra Kumar Sharma Microelectronics Department, Faculty of Electrical Engineering, Czech Technical University in Prague, Czech Republic.
Servin Rathi School of Electronics and Electrical Engineering,Sungkyunkwan University, Republic Of Korea.
Director's Desk
STM JOURNALS
I take the privilege to present the print version for the Volume 1 Issue (2) of Journal of Semiconductor Devices and Circuits. The intension of JoSDC is to create an atmosphere that stimulates creativeness, research and growth in the area of semiconductor devices, circuits and allied applications. The development and growth of the mankind is the consequence of brilliant Research done by eminent Scientists and Engineers in every field. JoSDC provides an outlet for Research findings and reviews in areas of found to be relevant for national and international recent developments & research initiative. The aim and scope of the Journal is to provide an academic medium and an important reference for the advancement and dissemination of Research results that support high level learning, teaching and research in the domain of semiconductor devices, circuits and allied applications. Finally,I would like to thank Authors for their continued support and invaluable contributions and suggestions in the form of authoring. I express my sincere gratitude and thanks to our Editorial/ Reviewer board for write ups/ reviewing and providing constructive comments for the advancement of the journals. With regards to their due continuous support and co-operation, we have been able to publish quality Research/Reviews findings for our customers base. I hope you will enjoy reading this issue and we welcome your feedback on any aspect of the Journal.
Dr. Archana Mehrotra Director STM Journals
Journal of Semiconductor Devices and Circuits 1. 3D Simulation of Multi-Gate Mosfet Analysis for Analog Circuit Design Parameters Nirmal D., Chacko J. K., Thaya J. S., Manoj S., Lyndon B. G., Jebalin B. K.
Contents
1
Journal of Semiconductor Devices and Circuits Volume 1, Issue 2 www.stmjournals.com
3D Simulation of Multi-Gate Mosfet Analysis for Analog Circuit Design Parameters Nirmal D.*, Chacko J. K., Thaya J. S., Manoj S., Lyndon B. G., Jebalin B. K. Department of Electronics and Communication Engineering, Karunya University, Coimbatore 641114, Tamilnadu, India Abstract Chip density and performance improvements of semiconductor devices have been driven by their aggressive scaling. The performance of multi-gate FET for analog applications is explored in this paper. Analog operation of CMOS devices and its parameters are very important for future cutting edge technologies. The multi-gate technology shows excellent scalability and better immunity to short channel effects in MOSFETs. They are being easily assessed for CMOS applications beyond the 45 nm of the SIA roadmap 2010. Moreover, the optimization of the tri-gate device is done by varying the length of the three gates. The scalability of nanoscale device is done and the comparison of the threshold voltage, Ion current, Ioff current, Ion/Ioff ratio, and transconductance for different multigate FET structures are analyzed.
Keywords: tri-gate FET, threshold voltage, Ion current, Ioff current, Ion/Ioff ratio, transconductance.
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