2nd reviewer

Given the equation f(v, w, x, y, z) = x’wy + (zv’ + w(yz)’)’ + vzx + z’w’v.

1. Find the canonical POS form of the equation f.

2. Draw the truth table of f.

3. Draw the K-map of f.

4. Find the simplest form of equation f using minterms. The result must in SOP form.

Implement 2-to-1 multiplexer using 2 NOT gates, 2 AND gates and 1 OR gate. Label S as select line, IN0 and IN1 as input lines, OUT as output line.

1. Given the following gate delays.

NOT = 0.5 ns AND = 3.7 ns OR = 2.3 ns How long must I wait for the circuit to produce correct output?

2. If the gate delays are equal, regardless of type, what is the gate delay of each gate given that the maximum frequency of the clock signal that allows the circuit to produce correct output is 31.08 ns?

Refer to Figures 1 and 2. Plot the output signal for 1. Negative-edge triggered 2. Level sensitive Use timeline in drawing the output signal for each item.

Figure 1: Section 2, Problem 3

Figure 2: Section 2, Problem 3 I implemented 2 improvements in my processor: improvement A and improvement B. • Improvement A halved the execution time of 20% of instructions.

• Improvement B quartered the execution time of 50% of instructions not affected by Improvement A. What is the resulting speedup? (2.5 pts) I implemented 3 changes in my processor: Changes A, B, and C. An instruction could only be affected by a single type of change.

• Improvement A halved the execution time of 20% of instructions.

• Improvement B tripled the execution time of 6% of instructions.

• Improvement C quartered the execution time of X% of instructions.

If the 3 changes resulted in no speedup(and no degradation), what must be X? A single-cycle processor, executing a program with 1000 instructions, has an operating frequency of 100 MHz. The processor was pipelined, which cause its CPI to increase 3 by 5%. Assume that we were able to distribute the delay among the pipeline stages perfectly, and we are using the new maximum usable frequency. If the new execution time is 0.00000105s, into how many stages was the processor pipelined? Ignore the fill-in time(time at the beginning of program execution when pipeline is being filled) and drain time(time at the end of the program when the pipelined is being drained).

If the program shown in Code Block 1 is run in a pipelined MIPS processor(shown in Figure 3) which could not properly deal with data hazards, after the program is ran...

• What would be the value of register t1?

• What would be the value of register t4?

• What would be the value of register t5?

• What would be the value of register t6?

Code Block 1 li $t0, 0 li $t1, 1 li $t2, 2 li $t3, 3 li $t4, 4 li $t5, 5 li $t6, 6 li $t7, 7 li $t8, 8 add $t1, $t2, add $t4, $t1, li $t0, 0 add $t5, $t4, li $t0, 0 add $t6, $t5, add $t7, $t6, 3.6 $t3 $t1 $t2 $t1 $t4

Figure 3: Pipelined Processor