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2019 resource Guide PG 28

Crystal Group Rugged Systems Edge Computing for IoT PG 29

Secure software & SPARK AdaCore co-founders Cyrille Comar and Franco Gasperoni know there’s something wrong with embedded software security. And they've fixed it.

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CONTENTS

Fall 2019 | Volume 17 | Number 2 opsy.st/ECDLinkedIn

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COVER

Arm flexible access reflects the state of today's semiconductor market

By Brandon Lewis, Editor-in-Chief

FPGAs & Arduino drive motor control

By Brandon Lewis, Editor-in-Chief

Achieving effective verification and validation of vehicle E/E systems

By Lance Brooks, Mentor, a Siemens business

SPARK security into your system software Interview with Franco Gasperoni and Cyrille Comar, AdaCore

The AUTOSAR C++ and MISRA C++ integration and adaptive development: So good, or so what?

In this issue: Our Fall 2019 Resource Guide (pg. 28), our editor dives into using FPGAs for motor control, an exploration of verification and validation of vehicular electrical and electronic systems, and an interview with AdaCore’s Cyrille Comar (co-founder and president) and Franco Gasperoni (co-founder and CEO).

By Mark Pitchford, LDRA

WEB EXTRAS

28 2019 RESOURCE GUIDE

Ą Applying machine learning on mobile devices

By Igor Markov, Auriga Inc. https://bit.ly/2lrvRhU

Ą The fundamentals of transimpedance amplifiers

By Bonnie C. Baker, Maxim Integrated https://bit.ly/2mYetlj

EVENTS ĄĄĄITC – International Test Conference

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November 12-14, 2019 Washington, DC itctestweek.org

ĄĄĄembedded world 2020 February 25-29, 2020 Nuremberg, Germany embedded-world.de

ĄĄĄEmbedded Technologies Expo & Conference June 9-11, 2020 San Jose, CA embeddedtechconf.com

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COLUMNS 5

TRACKING TRENDS

RISC-V: Too open to succeed

By Brandon Lewis, Editor-in-Chief

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Embedded Computing Design RESOURCE GUIDE | Fall 2019

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TRACKING TRENDS

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RISC-V: Too open to succeed

By Brandon Lewis, Editor-in-Chief Earlier this year, I wrote a column entitled “RISC-V: Too Open to Fail” in which I outlined several reasons why the open hardware initiative will be a success.

Now it’s time to look at a few reasons the technology could fail. And they start with the fact that RISC-V is open source.

Can open-source hardware really be a long-term commercial success?

As a reminder, RISC-V defines an opensource, royalty-free instruction set architecture, not actual IP cores or chips. Cores based on the ISA are being developed by companies like Si-Five, Codasip, Esperanto, and GreenWaves. Even wellestablished industry players like Andes and Western Digital have RISC-V cores.

NXP and Microchip (via its Microsemi acquisition) have SoCs based on RISC-V. But there’s the rub: Because only the ISA is defined, core implementations can – and do – vary across vendors. In fact, Si-Five, the de facto RISC-V IP standard bearer, has publicly announced multiple engagements of customizing RISC-V cores for specific client use cases.

This flexibility to customize and tune the most fundamental hardware building blocks to the specific needs of a particular application is the beauty of opensource technology.

But the flexibility of open-source hardware could also potentially be its downfall. It’s a matter of conformity and compliance, as currently there are no tried-and-true guarantees that a RISC-V core from one IP vendor can be used in place of another’s without significant rework down at the VHDL/Verilog level.

And that can be incredibly expensive.

There is a RISC-V Compliance Task Group, but there hasn’t been much news out of it in several months.

Without more strict compliance, betting a system design on a core from one of the www.embedded-computing.com

many RISC-V startups, for example, can be a frightening proposition for customers. The looser environment also makes it more difficult for software ecosystems to take hold.

Without software?

Previous open hardware initiatives like OpenRISC and OpenSPARC failed commercially largely because no software ecosystem ever materialized around the relatively few cores that were produced. RISC-V has a similar problem, only in the sense that with the potential for so many different core permutations it will be difficult for tools, middleware, and operating system providers to develop and support a robust software ecosystem.

Yes, major tool providers like IAR and SEGGER have announced support for RISC-V. And because tools like Embedded Workbench and Embedded Studio target the ISA, that’s great news. But what about something as simple as debug probes, if and when these cores actually make it into silicon?

Software vendors are going to have to hedge their bets when investing in this quickly evolving ecosystem, which will probably end up dictating the initial winners and losers of the RISC-V core wars. Even then, there’s the “custom core” issue mentioned earlier, which in many cases may mean that the core developer or customer will have to patch together specialized software support on their own.

And that too can be extremely expensive. For instance, a recent blog entitled “The Arm Ecosystem: More than Just an Ecosystem, it’s Oxygen for SoC Design Teams” estimates that software comprises roughly a quarter of SoC development costs.

“If you’re in it to make money, you’re in it for the wrong reasons” This summer I had a chance to visit several vendors in Texas, and met with Geoff Lees, the Senior Vice President and General Manager of Microcontrollers at NXP. He had some very strong opinions on the direction some companies were headed with RISC-V. Most notably, he stated that “If you’re in open source to make money, you’re in it for the wrong reasons.”

Of course, this is easier to say when you’re one of the largest semiconductor manufacturers in the world. NXP and others have the luxury of resources that other smaller companies do not, and they’re positioned in the supply chain such that they can replace small Cortex-M-class cores used for general housekeeping on larger SoCs with RISC-V IP and save on licensing costs.

In the world of open-source software, early pioneers like Red Hat were able to capitalize on Linux by being one of the first in the market, but Red Hat was more the exception than the rule. Hell, Linux itself is more the exception than the rule. It is a capitalist world, after all.

So is RISC-V too open to succeed commercially? Maybe. At least for now.

Embedded Computing Design RESOURCE GUIDE | Fall 2019

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IP & PROGRAMMABLE LOGIC

Arm Flexible Access Reflects the State Today’s Semiconductor Market

By Brandon Lewis, Editor-in-Chief

If you’ve been monitoring the semiconductor market over the past few years, you’ll know that it’s ripe for change.

T

chip designers to look elsewhere for improvements in performance, power consumption, and cost. The IoT is promoting the deployment of compute intelligence everywhere. The desire for custom, application-specific processors only continues to increase.

The momentum around open-source hardware is now palpable thanks to Raspberry Pi, Arduino, and BeagleBoard in the Maker community, and the RISC-V ISA in the academic, research, and commercial realms.

These trends are also leading to a world where engineers want – and need – access to lower cost, more accessible processor IP, if only just for evaluation and prototyping.

It also serves IP vendors to lower the barriers to entry for their technology. Doing so may cost them in the short term, but lead to more high-volume, highermargin business over the long haul.

All of these dynamics and more led Arm, the largest semiconductor IP provider in the world, to adjust its traditional IP licensing model to include Arm Flexible Access.

More “Flexible Access” Arm Flexible Access is a new way of allowing SoC design teams to access a broad set of Arm IP for initial evaluation and development. But more importantly, they only have to pay licensing fees on what is used in production.

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It’s not free, of course. Annual access fees start at $75,000, which includes one tapeout per year. They scale up to a $200,000-per-year option that allows for unlimited tape-outs, as well as additional tools, training, and design services.

Licensing fees are applied on a per-product basis, and standard royalty fees also apply.

But for established SoC engineering teams that want to tinker around with Arm technology and have the resources to spare, it sure beats the alternative (Figure 1).

Arm Flexible Access can be leveraged for a wide range of processor cores, interconnects, system controllers, security IP, and tools. These include, but are not limited to: › The majority of Arm Cortex-M, -R, and -A-class CPUs (which have accounted for 75 percent of all Cortex CPU licenses in the last two years) › Mali GPUs › Corstone foundation IP › Artisan Physical IP & Libraries › Arm DS Gold One › Arm Socrates › CoreSight Debug & Trace › Virtual System Models A full list of the technologies covered under Arm Flexible Access can be found at www.arm.com/why-arm/how-licensing-works.

Early participants in the Flexible Access program include Nordic Semiconductor, Invecas, and AlphaICs. Even more flexibility for research and academia Shortly after the Flexible Access launch in July, Arm continued to build on its new model with the unveiling of Arm Flexible Access for Research.

This sector-specific offering is, you guessed it, only available to members of the academic and research community. It offers the majority of Arm Cortex-M, -R, and -A CPU cores; complete RTL access; and other subsystems and tools for completely free. No fees or costs of any kind are associated with this flavor of the Flexible Access offering.

This is obviously designed to insert Arm IP into the hearts, minds, and early designs of advanced project developers. But it may also purchase the company some good will on the university circuit, where RISC-V has grown increasingly popular in recent years.

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IP & PROGRAMMABLE LOGIC

GIVEN ALL OF THE MARKET FORCES CURRENTLY AT PLAY, IT WAS INEVITABLE THAT THE WINDS OF CHANGE WOULD BEGIN BLOWING IN THE SEMICONDUCTOR INDUSTRY. To gain access users just have to complete a click-through end user license agreement (EULA) at www.arm.com/resources/ research/enablement/contact-us. Arm Research SoC Labs is also developing an online community that will help foster technology sharing, reuse, and peer review for Arm Flexible Access for Research participants.

Still get your “DesignStart” It’s important to note that Arm Flexible Access will have no impact on the popular Arm DesignStart program, which offers a $0 upfront access fee for Arm CortexM0, -M1, and -M3 CPUs and a $75,000 access fee for the Arm Cortex-A5. In fact, Dipti Vachani, Senior Vice President and General Manager of the Automotive and IoT business units at Arm says that “Arm Flexible Access complements DesignStart.”

“DesignStart will continue to be ideal for partners who want the lowest possible upfront costs,” she asserts. “Arm Flexible Access provides access to a wider set of technology and tools – all the essential IP to design an SoC. “They both also offer a portal to the world’s largest compute ecosystem, which helps enable lower SoC build costs, smaller risk profiles, and faster time-to-market.”

Semiconductor innovation or just a different way to pay?

Given all of the market forces currently at play, it was inevitable that the winds of change would begin blowing in the semiconductor industry. It’s a sector that’s been ready for some flux (or maybe some “flex”) for several years, at least.

But what do programs like Arm Flexible Access really accomplish? Are they truly going to foster semiconductor innovation?

Or are they just another way for a company that has domi-nated a market segment for nearly two decades to extract revenue earlier from small-to-medium-sized businesses that are on the fence about technology investments? And does it say anything that this announcement comes at a time when a somewhat viable alternative appears to be taking shape in the form of RISC-V? “It’s a convergence of multiple factors, with the biggest factor being a new wave of data-driven computing that is pushing more data processing to the edge,” says Vachani. “This, of course, has led to new computing models, specifically around machine learning and artificial intelligence. These new computing models have resulted in increased demand for custom silicon.

“The demand for custom silicon has prompted new entrants into the silicon market, such as startups, system providers, and OEMs seeking more agile development processes,” she continues. “And these new entrants want to work within a pricing model they are familiar with. That pricing model is similar to the SaaS and cloud computing pricing models that have become commonplace in the technology industry.”

I think the answer is a soft “yes” to all of the questions posed. But whatever the answer is, if it means things get better for semiconductor engineers, I’ll take it.

Standard Arm licensing terms Per unit royalty

Per product license

License fee due before access License any Arm IP Select IP

Access Licensed IP

Develop SoC

Tape out & manufacture

Ship

Licensing options for single or multiple designs

Arm Flexible Access Per unit royalty

Per product license

Access & design before license fee Unlimited access to included IP Access Package IP

FIGURE 1

Select, evaluate, experiment, design

Develop SoC

Tape out & manufacture

Ship

License due for each completed design

Arm Flexible Access departs from the traditional Arm licensing model by postponing up-front licensing fees until tape-out.

www.embedded-computing.com

Embedded Computing Design RESOURCE GUIDE | Fall 2019

7

FPGAs & Arduino drive motor control

By Brandon Lewis, Editor-in-Chief Any engineer who’s ever designed an electromechanical system that pushed, pulled, turned, or spun is intimately familiar with motor control. Its application is so widespread that even simple microcontrollers (MCUs) provide the clock speed and signal processing performance to drive complex motors with variable speeds and loads.

But how much is too much for these resourceful little MCUs? What if you’re using a high-resolution quadrature encoder to measure motor speed or direction? What if you need to drive more than one or two motors at a time?

RATHER THAN USING MULTIPLE

Meet Hexy the Hexapod (Figure 1). Hexy is a low-cost, Arduino-based robotics kit from ArcBotics. The robot contains three servo motors on each of its six legs, plus one on its head, for a total of 19 servo motors.

BOARDS, A SINGLE FPGA CAN

Since Hexy was designed for the Arduino community, it is compatible with a number of 8- to 32-bit MCUs. These MCUs perform admirably in simple tasks like sequentially driving the motors on each of Hexy’s legs. But when an interrupt service routine is introduced – as it would in any system using a quadrature encoder – the MCUs start to struggle.

One solution for these more complex use cases is an FPGA accelerator.

Avoid the pains of programming A primary advantage of FPGAs is that they can be reprogrammed, allowing them to meet the exact requirements of an application. FPGA fabric can be optimized to the precise determinism, control, and jitter requirements of PWM [pulse width modulator] signals that drive a motor. More FPGA logic blocks can be configured to support

PROCESSORS OR CONTROL DRIVE A NUMBER OF MOTORS AND READ AND PROCESS QUADRATURE DATA. THIS REDUCES DESIGN COST, POWER CONSUMPTION, AND SYSTEM SIZE. additional motors, providing a level of parallelism that isn’t available from other embedded processor architectures.

In fact, the ability to configure FPGAs to exact system requirements can make them more suitable than robust, highend motor control MCUs, DSPs, and ASICs for motor control applications.

The video (scan code in Figure 1, left, to watch) shows a motor control demo controlled by 8- and 32-bit MCUs on the Hexy robot. As you can see, the robot’s arms begin to twitch when 50 µs interrupts are introduced; there are simply too many concurrent tasks for the MCUs to compensate for jitter in the PWM signal that drives the servos.

FIGURE 1 8

ArcBotics’ Hexy the Hexapod DIY robotics kit contains 19 servo motors. A demonstration (scan code above to watch) shows its 8- and 32-bit MCUs struggling to execute concurrent tasks on the Hexy robot. (Source: Alorium Technology, ArcBotics.)

Embedded Computing Design RESOURCE GUIDE | Fall 2019

The video goes on to show how effective the parallelism and precision of an FPGA can be in complex, interrupt-based, multimotor drive use cases. Rather than using www.embedded-computing.com

Alorium Technology

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multiple processors or control boards, a single FPGA can drive a number of motors and read and process quadrature data. This reduces design cost, power consumption, and system size.

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FIGURE 2 The XLR8 development board.

(Source: Alorium Technology)

But FPGA programming has historically made engineers run for the hills. That’s because VHDL and Verilog – the two primary hardware description languages (HDL) used to describe the structure of FPGA fabric – are actually electronic design automation (EDA) paradigms.

These languages do not operate like typical software: Complex logic synthesis tools are needed to convert HDL code into a design implementation that defines logic gates, generates bitstreams, and so on.

For most engineering teams, the decision to use FPGAs comes after weighing the parallelism and performance gains against the pains of programming. One company designing custom BLDC motor control applications for unmanned aerial vehicles (UAVs) recently found itself at these crossroads.

To avoid making a tradeoff, it partnered with Alorium Technology, a developer of FPGA-accelerated embedded solutions.

Enhanced custom BLDC motor control The UAV company began designing the BLDC system around MCUs and was using the Arduino IDE to write and test its motor control software. The application required a processing element that could run the motors at extremely high, variable speeds, and also read sensor data. Eventually, the system became too complex to run on an MCU, and the decision was made to migrate to custom hardware.

The main problem with this decision was that the company’s entire codebase had been designed in and around the Arduino environment. This meant whatever compute architecture chosen for its motor control system had to efficiently run Arduino’s simplified C++ code. www.embedded-computing.com

FIGURE 3

Intel MAX 10 FPGAs accelerate applications like motor control. (Source: Intel Corp.)

The company arrived at Alorium Technology’s XLR8 development board (Figure 2).

XLR8 is an Arduino-programmable, FPGA-based prototyping platform with an embedded 8-bit AVR MCU. The board is a form factor- and pin-compatible replacement for the Arduino Uno. The UAV engineering firm was able to drop the board into its design and immediately start running existing code.

The XLR8 FPGA fabric is based on an Intel MAX® 10 FPGA with 8,000 logic elements (LEs) and 500 logic array blocks (LABs). With a maximum operating frequency of 450 MHz, it provides more than enough horsepower for even the most sophisticated motor control applications.

The MAX 10 also natively integrates flash memory, ADCs, digital and analog I/O, and other components that make it a cost-effective solution for deployment in industrial use cases (Figure 3).

But what made the XLR8 development board so attractive to the custom UAV BLDC design was the presence of function-specific “Xcelerator Blocks,” or XBs. XBs are integrated into the MAX 10 FPGA fabric to optimize the performance of certain functions, such as servo control, quadrature encoding, analog to digital conversion, floatingpoint math, and so on.

Embedded Computing Design RESOURCE GUIDE | Fall 2019

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XBs communicate with the AVR MCU via an addressable register interface (Figure 4).

And thanks to XB libraries from Alorium that can be installed in the Arduino IDE, users can access their functionality using standard API calls. No code modifications are required. It is even possible to update the FPGA image through the Arduino IDE. To support unique control algorithms used in the BLDC application, custom hardware was required. Alorium customers are able to create their own specialized XBs using a methodology called OpenXLR8. This does require VHDL or Verilog coding but provides a templated environment for users. It even generates Arduino-compatible RPD files.

In the case of the UAV project, Alorium assisted with the development of several custom hardware blocks. These included: › RC Input XB that interprets incoming signals from a radio control device › PWM XB that implements a configurable PWM along with a three-phase sinusoidal PWM

› Hall Sensor XB that provides static tuning of signals before sending them to the motor control XB › The ability to dynamically adjust the system based on motor speed › Proprietary blocks Because added BLDC functionality required more FPGA fabric, the UAV design eventually migrated to Alorium’s higherperformance Snō FPGA Module. Snō is production-grade, supporting an 8-bit MCU and Arduino compatibility. And it also upgrades the FPGA to a MAX 10 with 16k LEs. As the UAV system neared production, it needed protection against signal noise caused by high-voltage switching. To solve this problem, Alorium developed a noise-immune carrier board for the Snō module called the AT10 (Figure 5).

From maker to master The UAV BLDC case study provides an excellent example of how open-source, educational hardware has taken hold in the professional engineering community.

FIGURE 4

Xcelerator Blocks communicate with the AVR microcontroller.

(Source: Alorium Technology.)

FIGURE 5 The AT10 carrier board is a noise-immune carrier board for the Alorium Snō module.

(Source: Alorium Technology.)

Beyond this application, Alorium has customers in industries like test, measurement, and scientific instrumentation that require extremely high fidelity from data acquisition and signal processing systems. To scale while meeting many specific use case requirements, its hardware platforms must be flexible. And since the primary users of these systems are scientists or domain experts, novices must become technically proficient with the platform software quickly.

With high-performance, low-cost, Arduinocompatible FPGA solutions, the industry is democratizing programmable logic technology. In some cases, the availability of these solutions will lead to rapid innovation. In many others, it will yield a more efficient, affordable, and scalable way of addressing challenges that already exist.

To download XLR8 images, XBs, and application notes, visit Alorium Technology’s Github.

This article originally appeared on insight.tech.

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AUTOMOTIVE TEST, MEASUREMENT & COMPLIANCE

Achieving Effective Verification and Validation of Vehicle E/E Systems

By Lance Brooks, Mentor, a Siemens business

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Automotive market trends toward advanced driver assistance systems (ADAS), automated driving systems (ADS), and autonomous vehicles (AV) are fostering innovation and fueling a relentless increase in the amount of software content incorporated into advanced electronic control units (ECUs), sensors, actuators, and other onboard hardware. This increase has resulted in dramatic spikes in the amount of data flowing throughout vehicle electrical/ electronic (E/E) systems. Meanwhile, to meet the auto industry’s increasingly stringent requirements relative to time, budget, and quality, achieving effective verification and validation (V&V) has become paramount – especially in light of the mass adoption of these transportation technologies that many experts predict in the years and decades ahead.

s automated and autonomous drive technologies grow substantially more complex, developers face new challenges in verifying and validating the safety and security of next-generation E/E systems. In the process of addressing these challenges, engineers are bombarded with an expanding number of new, specialized software tools from different vendors, all of which must somehow work together.

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A common and quite significant challenge facing today’s automotive engineers is dealing with the massive number of V&V cycles now required, including testing that spans the many gaps in the tiered development ecosystem. The vast amount of software and mountains of data flowing within and between all system hardware creates very complex interactions. E/E systems are inherently multi-ECU distributed systems, which means that the ideal V&V infrastructure must support the ability to mix the level of accuracy (or fidelity) within the system model in order to realistically cover the amount of testing scenarios required.

While ECU hardware is quite accurate, and verification equipment allows engineers to test systems using actual ECU targets, cost and maintenance complexity factors limit

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AUTOMOTIVE TEST, MEASUREMENT & COMPLIANCE

Failing to effectively address these challenges can present a number of negative outcomes from a business and economic perspective. Insufficient safety and security test coverage has perhaps the largest potential business impact, because insufficient coverage means that potentially significant problems can go undetected. Failing to discover issues early in the project, when they are least expensive to fix, can explode development budgets. If not detected before deployment, technical errors can result in catastrophic consequences for businesses – or worse, for end users.

ELECTRICAL/ELECTRONIC SYSTEMS ARE INHERENTLY MULTI-ECU DISTRIBUTED SYSTEMS, WHICH MEANS THAT THE IDEAL VERIFICATION AND VALIDATION INFRASTRUCTURE MUST SUPPORT THE ABILITY TO MIX THE LEVEL OF ACCURACY (OR FIDELITY) WITHIN THE SYSTEM MODEL IN ORDER TO REALISTICALLY COVER THE AMOUNT OF TESTING SCENARIOS REQUIRED. the number of hardware-based verification systems available in a typical project.

Access to these systems is often scheduled, and not every software engineer on a project can use them, especially when they are most needed. Further, physical hardware has a limited ability to be predictably controlled, and visibility into the system’s signals for tracing and failure injections is not always possible. Perhaps even more limiting is the fact that actual ECU hardware requires environment models that execute in real-wall-clocktime. This constraint limits their fidelity on one end, and on the other end means that time cannot be accelerated for tests that must account for long-term effects within shortened verification cycles.

Test reuse throughout the development process is another substantial engineering challenge, most significantly in the areas of the various levels of test bench signal abstraction; the different means for controlling the growing array of available specialized tools; and the disparate modeling, test, and programming languages used across a project. www.embedded-computing.com

A major factor contributing to inadequate test coverage (and its associated inefficiencies and costs) relates to the inability of partners to exchange test artifacts between teams, groups, and organizations. Failure to follow V&V standards and best practices often means switching back and forth between incompatible testing technologies, which ultimately limits the kind of cross-organizational sharing of test artifacts required for optimal test coverage. It also prevents verification engineers from combining the best test automation software with the best test benches. The inability to share test artifacts can also contribute to the common problem wherein one partner cannot reproduce another’s reported issue. Further yet, training costs increase when engineers must learn proprietary details of each non-standard tool.

This article explores and outlines solutions to these critical V&V challenges in the AD/ADAS era. Among the solutions proposed are virtual ECUs with scalable fidelity; correct by design generative model-driven development (MDD) work flows; software architecture standards; test framework standards; modeling and tool interoperability standards; and architecture-aware verification.

Scalable-fidelity within XIL test benches With respect to the design of E/E systems, development methodologies and V&V tools have advanced significantly over the past few decades. Today, the model-driven development (MDD) methodology and “X”-in-the-loop (XIL) verification approaches are well established as effective means to develop safe and secure vehicle E/E systems.

The XIL apparatus represents the so-called “digital twin,” which is a model of a system that executes software functions on a network of electronic control units (ECUs) connected to environment models and tests. Two key industry standards that are commonly used to create the digital twin are Functional Mockup Interface (FMI) and AUTOSAR. Embedded Computing Design RESOURCE GUIDE | Fall 2019

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FMI is an open, tool-independent standard broadly supported by many tool vendors for use with both model exchange tasks (external solvers) and cosimulation (internal solvers) of dynamic models. FMI specifies a combination of XML files and compiled C ode, all of which is bundled into functional mockup units (FMUs) that represent the sensor, actuator, and plant environment surrounding a distributed E/E system. FMUs allow the fidelity of the environment model to scale to meet the verification intent without changing the test bench interfaces. FMUs can also represent the ECU itself within the system-level FMI-master simulation.

The AUTOSAR partnership is an alliance of OEM manufacturers, tier 1 automotive suppliers, semiconductor manufacturers, software suppliers, and tool suppliers.

Considering the different automotive E/E architectures in current and future markets, the partnership establishes an open, de facto industry standard for automotive software architectures. The significance of AUTOSAR within XIL test benches is that it provides formal platform concepts and hardware abstractions, enabling the digital

twin’s timing behavior and signal communications to be considered very early and continuously in the process as the fidelity of the ECU model scales.

In the MDD systems engineering process, a model of the ECU’s behavior is tested against a model of the vehicle system’s communication networks, sensors, actuators, and plant environment surrounding the ECU – and all of this comprises the so-called model-in-the-loop (MIL) level of abstraction. Once the MIL-level behavioral model is validated, it is automatically transformed into C/C++ code and then retested – all of this then represents the software-in-the-loop (SIL) level of abstraction. Eventually, the generated code is integrated into ECU hardware and platform software (also known as firmware) and again retested, giving us the hardware-in-the-loop (HIL) level of abstraction. The HIL-level testing can also be performed using models of the ECU hardware – giving us a virtual-hardwarein-the-loop (vHIL) level of abstraction.

To satisfy a test’s purpose, the accuracy of the XIL configuration must be sufficient for adequate coverage and confidence. The range of fidelity of the various XIL configurations can be quite wide. The vHIL configuration that leverages virtual ECU simulation technology covers the broadest range. With this configuration, the accuracy of the ECU hardware model can scale, whereas the platform and application software is the actual code that deploys in the final vehicle (similar to HIL). This facilitates the testing of final production software on a platform with optimal accuracy relative to verification intent. This concept is called “scalable-fidelity.”

Scalable-fidelity is important because the digital twin that is best for testing drivability may not be the same digital twin that is most effective for verifying whether embedded software meets certain safety or security requirements.

Determining whether a digital twin is sufficiently accurate requires a clear and specific statement of precisely what must be verified, so that the “right level” of fidelity required can be determined.

The right level of fidelity matters, because digital twins that are too simple

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cannot expose enough detail for every verification problem, and highly precise digital twins have other trade-offs such as long development cycles, higher costs, and possibly insufficient simulation performance. Typically, the fastest and least-expensive digital twin available that still offers sufficient fidelity to solve the problem is best.

To effectively complete the massive amount of testing required, teams cannot rely solely on hardware-based rigs, because there are usually too few of them available for every software developer or verification engineer on a project. In addition, hardware rigs can only execute at real-wall-clock-time. Alternatively, conducting tests at the MIL, SIL, or virtual HIL (vHIL) levels can substantially speed up testing cycles, making these models far more appropriate for many verification requirements. And since testing with models requires only a PC, cost efficiency can be maintained.

Also critical for efficiency is ensuring that the testing framework supports the ability to mix the XIL levels of abstraction within a single system-level simulation. This is key to the effective validation of the types of highly distributed, multicore, and multi-ECU E/E designs common in most modern ADAS, ADS, and AV vehicle systems. Not every ECU digital twin in a multi-ECU system simulation scenario needs to be of the highest-fidelity available for that particular ECU. Finally, ensuring scalable-fidelity within XIL test benches provides a number of cost-saving benefits: › Problems are found earlier in car projects, when they are least expensive to fix › Increased V&V coverage boosts safety, enhances security, and otherwise identifies problems before they are deployed into the field › Leveraging test benches of mixed fidelity supports the massive number of V&V cycles required for multi-ECU systems Test reuse throughout the process Testing a digital twin of a system begins at the test bench, which is an abstraction www.embedded-computing.com

FIGURE 1

Test cases developed using test automation software must have sufficient coverage to verify and validate all E/E system requirements.

that provides the ability to execute a system under test (SUT) and then access data within it. The digital twin of an electrical/electronic (E/E) system includes simulations of all its ECUs, networks, mechatronic hardware, and other parts. Each type of data or access requires a different interface and is configured and managed by different specialized tools. For E/E systems, the primary data include: › › › › ›

Signals and parameters in embedded software and simulation models Data from the diagnostic functionalities of ECUs Measurable variables and calibration data within automotive software Data controlling fault and error injection within the system Signals encoded into messages communicated over an automotive network

Test automation software supports the testing sequence (or test case) and utilizes the interfaces exposed by the test bench to access data and exercise the digital twin’s functionality. Overall, test cases must have enough coverage to verify and validate all aspects of the E/E system requirements (Figure 1).

If test automation software is directly coupled to the test bench using a rigid interface, test reuse is not possible across the development process, and large disconnects will remain between verification and validation (V&V) at the model level, and V&V at the implementation level. This is a significant issue because every test case will not be converted or back-adapted to each level of abstraction – and tool-dependent tests will be developed multiple times by different people with varying skill sets.

Factors that make test reuse difficult include: › Different levels of abstraction of the data and signals within the test benches › Multiple modeling and programming languages › Proprietary means to sequence and control the various specialized tools or otherwise stimulate and trace the digital twin Without standardization, test case reuse is unattainable because otherwise there is no consistent way to communicate between test cases and test benches; describe, configure, and initialize test benches; or map and access data within test benches.

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ASAM XIL is an API standard for the communication between test automation tools and test benches. It addresses the above challenges while promoting interoperability between solutions from different vendors.

The benefits of ASAM XIL are that it: › Supports test case reuse by decoupling test automation software from test hardware › Establishes interoperability between different vendors relative to test automation software and test benches › Provides a means for controlling test benches based on simulation tools › Significantly reduces testing effort › Supports long-term protection of testing investments › Establishes a common approach for test bench setup and initialization › Collects time-aligned trace data and specifies its data format › Supports injection of faults and errors into the SUT › Supports test events and triggering › Reduces training costs ASAM XIL is built into two major parts. The first is a test bench for the simulation models, ECU data (e.g., parameters, variables, and diagnostics), electrical error simulation, and automotive networks. This test bench provides interfaces to different types of tools via specific test bench ports; for their part, these ports offer standardized access to ECUs, including interfaces for calibration, measurement, model access, diagnostics, network signals, and electric error simulation.

The second major part of ASAM XIL is a framework for mapping units, data types, or variable identifiers and for configuring actions, measurement, logging, triggering, initialization, ordering, and sequencing.

The ASAM XIL mapping framework is key to addressing the particularly challenging task of decoupling test automation software from test benches. It does this by allowing data within a test bench to differ in value and type using mappings. By providing a new mapping for each test bench, the test case remains unchanged and can be reused against any XIL abstraction level within the digital twin and across engineering phases.

Port independence to test cases is achieved via object-oriented access to variables on the test bench, and an abstraction of ports within the framework layer. Based on these variable objects, the framework provides objects for signal recording, signal generation, and event watching and triggering.

ASAM XIL is also beneficial from a business perspective. It reduces training costs and supports testing early in the development process when issues are least expensive to

FIGURE 2 16

rectify. Test cases can be reused across the entire development process. OEMs and suppliers can exchange test cases and test benches very efficiently. And finally, verification engineers can switch between the best test automation software and the best test benches.

Generative model-driven development workflows A generative model-driven development (MDD) workflow is a systems-engineering process that uses software tools to automatically generate products using models as inputs, applying model transformation algorithms that capture engineering expertise that is otherwise applied manually. This technique allows developers to focus on their domain and create models using domain-specific modeling tools that are optimized for specific types of problems. After sufficient V&V of these models that prove that the system they represent meets requirements, the validated models drive subsequent automated production phases in a systematic manner. Generative MDD workflows ensure the best quality, performance, and compliance while also shrinking development time.

Generative model-driven development workflows can optimize quality, performance, and compliance while streamlining development cycles.

Standards such as ASAM XIL, FMI, and AUTOSAR provide formal ingredients to establish a comprehensive generative MDD workflow for E/E system development. ASAM XIL provides the standard test automation and test bench

Generative model-driven development (MDD) workflows reduce development time while improving quality, performance, and compliance.

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architecture, FMI provides the standard abstraction required to deploy domainspecific models into the workflow, and AUTOSAR standardizes on the software architecture aspects used to map formal E/E hardware and software concepts to the models and test data. AUTOSAR is also used as part of the produced implementation as an embedded software runtime. Using a set of rules, it is possible for tooling to take test case descriptions, functional models, environmental models, and architectural models that are produced during normal system design efforts, and generate the test benches, mappings, and configurations required for automatic V&V regression testing.

Today, generative MDD workflows exist that begin with AUTOSAR models of an E/E system’s architecture and FMI models of its software and environmental behavior, and then automatically configures and generates production quality embedded software images that are ready for V&V on a scalable XIL test bench. In these workflows, AUTOSAR is used to guide the domain-specific behavioral modeling activity because the model represents embedded software that will deploy in an AUTOSAR platform. By using the architecture model as an input to behavioral modeling, the model conforms to the structure needed by the C/C++ code generation tools that are specifically designed to produce AUTOSAR-compliant code. This saves an engineering adaptation step and helps focus the controls and function engineers on behavior and triggering semantics that surround the system.

Very little to no input is required by the ECU integrator to produce systems that are ready for V&V. The amount of input depends on the engineering phase (what aspect of the system is under test) and also any institutional rules and styles their organization employs at each engineering step. For example, if it is the application logic that is being tested, default configuration rules that generate “good enough” AUTOSAR firmware is sufficient for validating the function, because AUTOSAR-compliant platforms realize standard semantics independent from actual ECU hardware specifics. If timing, memory, and other hardware-dependent constraints must be www.embedded-computing.com

FIGURE 3 Symmetrical mapping can be used to correlate implementation and design models during system analysis.

considered, more rigorous rules must be applied. But even in this case, once the generation is configured, the generative workflow automatically produces the integrated ECU including the AUTOSAR firmware and runtime environment.

Using an AUTOSAR-aware MDD workflow, the model-in-the-loop (MIL) test bench generation is automated. In addition, its V&V efforts are performed in a more realistic embedded software context. In tool offerings that utilize scalable virtual ECUs that model ECU hardware, what is traditionally performed using software-in-the-loop (SIL) test benches can be skipped, and the V&V can be directly performed on virtual hardware-in-the-loop (vHIL) test benches that offer the convenience advantages of SIL test benches and the fidelity advantages of hardware-in-the-loop (HIL) test benches.

In short, generative MDD workflows provide value by leveraging implementation domain expertise that is captured in tools to increase quality and reduce problems, and manual or otherwise repetitious efforts are eliminated, thereby accelerating time-to-market.

Design-aware V&V Thus far, this series has addressed test reuse across workflows, the value of scalablefidelity in XIL test benches, and generative, model-driven development (MDD) workflow solutions to key V&V tasks relative to the development of E/E systems in vehicles.

Interestingly enough, the solutions to these challenges present another set of brandnew challenges, which in turn demand additional solutions.

Central to each V&V solution discussed herein is the concept of modeling, which raises the abstraction level to the domain of E/E systems, thereby allowing tools to produce optimal product realizations from design input bases. However, raising abstraction levels means that the expert designs of tooling-produced implementations are more or less foreign to vehicle function developers. This presents a V&V challenge, because verification tools are very good at extracting information and supporting stimulus at the technical implementation level – but not for the level at which the E/E system is designed, nor the level in which verification engineers understand the system. This is analogous to how a modern C++ compiler can produce very safe, high-performance code, but a C++ programmer trying to debug and analyze a system using a disassembler will inevitably face challenges.

Luckily, for the same reason that an automatic, generative MDD workflow is possible, an MDD verification environment that supports debugging and analysis at the design level is also possible. The solution lies in the metamodels to which the design input models conform and are otherwise described by. Generative tools use formal design model descriptions, along with a knowledge of the formal semantics embodied in their metamodel, in order to transform the design model (Figure 3) into a mapped Embedded Computing Design RESOURCE GUIDE | Fall 2019

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implementation model. This mapping is symmetrical, in the sense that it can also be used to cross-correlate information in the implementation model (and information within its execution trace) back into corresponding information in the design model.

This kind of referencing is used to create V&V tools that are “design-aware.” The notion of design awareness is general, and can be applied to different domain concepts with the design such as architecture, test, and/or language; and it can also be applied more or less deeper in the configuration of the implementation, such as in the MDDRTOS (kernel), platform services, or even in software interfaces.

As an example, “AUTOSAR-aware” V&V tools allow developers to debug and analyze E/E systems in the context of the AUTOSAR architectural model that describes the embedded software content within an ECU. For debugging, verification engineers can set breakpoints on AUTOSAR elements such as software components or port interfaces, which will halt the system when activity occurs in the context of these

elements, allowing verification engineers to inspect data within the ports and the component’s internals. For analysis, AUTOSAR-aware agents can present a system trace collected during the execution of the digital twin in the context of the AUTOSAR model and basic software (BSW) configuration elements such as tasks and network signals.

In summary, scalable-fidelity, test reuse, generative workflows, and design-aware V&V tool solutions combine to help verification engineers effectively verify and validate vehicle E/E systems, driven by rapidly advancing trends in the automotive market. The primary business values of effective V&V are: › Problems can be found earlier in the automotive design development processes, when they are least expensive to fix › Increased V&V coverage increases safety, enhances security, and otherwise finds problems before they are deployed into the field › Tests include test benches of mixed fidelity to support the massive number of V&V cycles required for multi-ECU systems › Test cases are reused across the entire development process › OEMs and suppliers efficiently exchange test cases and test benches › Training costs are decreased › Verification engineers can switch between the best test automation software and the best test benches › Implementation domain expertise captured in tools increases quality and reduces future issues › Manual or otherwise repetitious efforts can be removed to accelerate time-to-market › Verification and design engineers can generate product realizations at the domain level in which they are designed Lance Brooks is part of the Mentor embedded automotive product team.

Lance has over twenty-five years of experience creating embedded systems and related development tools with over ten years dedicated to automotive software development with a specific focus on AUTOSAR.

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Solid State Storage and Memory

SPARK security into your system software Interview with Franco Gasperoni and Cyrille Comar, AdaCore

Ubiquitous connectivity is transforming businesses in industries ranging from healthcare and automotive to aerospace and defense. Technology companies in these verticals now want to get new products, features, and services to market as quickly as possible.

Many of them are achieving this through software, by either adopting agile development practices, deploying remote device upgrades over the air, or both. However, more connectivity and the increased pace of software development mean that security vulnerabilities are now more common than ever. The best, and perhaps only, way to combat these risks is to integrate security at the programming level.

As AdaCore celebrates its 25th anniversary, the company’s cofounders Franco Gasperoni and Cyrille Comar share their thoughts on the changing technological landscape and the resulting cybersecurity challenges, how to address the next wave of security threats, and how AdaCore is proving that security in software is both achievable and affordable.

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ECD: How is the software engineering landscape changing as systems become more connected and security becomes more top of mind?

GASPERONI: Today, many security threats stem from software vulnerabilities. We use static analysis on existing pieces of software to uncover some of these vulnerabilities, and that improves the security of applications.

Then there are other techniques based on testing. An example is fuzz testing where you feed a large amount of random data into the application and try to crash it. When it crashes you learn that the software had holes, and thereby identify potential vulnerabilities.

These methods are mostly based on after-coding verification, and improve existing pieces of software. However, the stream of updates to our systems to fix security vulnerabilities demonstrates the limitations of this approach.

So, while analysis and testing will certainly remain adequate for some applications, for more critical use cases like navigation systems for autonomous vehicles, they’re not enough.

Why? Because we cannot just check or test our way to high levels of security since we’re fighting intelligent agents that obviously do not have benign intent. Whether this is humans or AI, these agents will find and exploit even the slightest hole.

Unfortunately, it is very costly and at times outright impossible to make a piece of code secure after you’ve written it – especially if the technology, the tools, or the programming or modeling languages that were used to build the software were not intended for security. We need to change the software development paradigm so that security is a fundamental requirement that is built in as part of the code.

ECD: Obviously, many of the systems we’re discussing are safety-critical in nature. Now security is also of the highest priority. Because traditional methods are now less effective, what options do safety- and security-critical software developers have?

GASPERONI: We’re coming from an aerospace and defense industry where they use a mix of programming languages, whether it’s Ada, C, C++, or models like Simulink and Stateflow.

Obviously the first constraint is that their system has to be safe. Now security is obviously impacting the safety of those systems. When you’re trying to implement a safe and secure system, you have to ask yourself, “How ambiguous is the code I’m writing?” because ambiguity is the death of security. When something is ambiguous, one way or the other it creates a hole in your system and a potential vulnerability. If you look at C, for instance, there are a number of ambiguities built in and that you inherit by using C. The next question, once you’ve identified those ambiguities, is “Can I subset my programming paradigm to remove all of those ambiguities?” www.embedded-computing.com

The ideal scenario is to use a programming paradigm that has no inherent ambiguities, whether that’s part of the language or thanks to a subset. That’s a good start but it’s not enough.

What you also need is a way to state the intended behavior of the system that is included as part of the implementation so that you can automatically check for consistency between the intention and the implementation.

WE NEED TO CHANGE THE SOFTWARE DEVELOPMENT PARADIGM SO THAT SECURITY IS A FUNDAMENTAL REQUIREMENT THAT IS BUILT IN AS PART OF THE CODE. Together with Altran, we have worked on this problem for over a decade at AdaCore and arrived at a programming paradigm called SPARK. SPARK is derived from the Ada programming language and is both unambiguous and allows for the specification and automatic checking of the code’s intent. The beauty of SPARK is that the intent of what the code is doing, or the “what,” is written using the same language as the implementation, or the “how.” Since these two things are done using the same programming technology, you’re basically programming all along.

By doing so, the contract of what the program should do and the program itself are one and the same and can be checked automatically at runtime or by static analyzers that verify your code as you develop. Most of the checks are OK’d automatically by the prover when the program is correct. When the program is known to be incorrect, the analyzer will provide a counterexample allowing developers to understand the weakness in their reasoning.

When the program is correct but the analyzer doesn’t succeed in proving it, the user can provide hints in the form of logical assertions (example of a hint: x>7 and y<100). These hints also help clarify the code to other developers. By supplying this additional information for the automatic checker, the checker can then prove or disprove contracts in the program.

To give you some examples, with SPARK you can check potential runtime errors like the use of uninitialized variables but do so in a more granular way. In some cases, it’s undesirable to initialize everything by default, so if you want to do conditional initialization for some reason, SPARK can check that.

Of course, it also checks for the absence of buffer overflows and tells you, “I guarantee that your program cannot crash,” or “Your program could possibly crash under this scenario.”

It also checks whether values are in the correct range, and so on. This is fundamentally different from static analysis of C/C++ programs where analyzers find some bugs but give no guarantee on remaining vulnerabilities.

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that a function should abide by or preserve. In the automotive domain, for instance, ISO 26262 speaks of Freedom from Interference. This is meant to prevent less safety-critical subsystems from interfering with more-critical subsystems. SPARK can also help you there.

COMAR: With testing we cannot be exhaustive in showing that a program does exactly what it is supposed to do. So rather than doing only testing, the SPARK language provides a technology that makes it relatively easy to develop mathematical proofs that demonstrate that your program is correct. In other words, you can 100-percent guarantee that your program does what it is supposed to do and doesn’t have any of the holes that could compromise security.

What you really want to prove in software development is that your program does what it is intended to do. As Franco explained, the ability to express both the intent and the implementation of the language allows you to check the validity of the program before the program even runs.

Getting to an executable with SPARK is going to take longer than it typically does, but the enormous advantage is that by the time you get to something that runs, you’re basically finished. The verification part of coding and implementation activities are basically complete.

We are also in the process of hardening our SPARK compiler to make the final executable more resilient against low-level object code attacks, such as glitching attacks and side channel attacks. An example of the latter is clearing internal structures that contain security-critical data as soon as they are not needed anymore in order to avoid their discovery through memory inspections.

ECD: This is great for new system builds. But what about the millions of legacy devices that were developed in other languages?

GASPERONI: For existing systems you can do surgical rewrites using SPARK. This means you would analyze your hundreds, thousands, or millions of lines of code for sensitive, securitycritical areas and rewrite that new module in SPARK to reach a higher level of security on your existing software.

SPARK is a technology that is very friendly to other languages and interfaces very well with them. So, after you’ve written the new code, you interface it with the existing code regardless of whether it’s C, C++, Java, Python, or whatever. This is much more cost-effective than rewriting and retesting your code, or the alternative of not doing anything at all.

But when you’re dealing with systems that interact with the physical world like a drone or vehicle, the technologies used to develop them are not “programming languages” in the conventional sense. They start with models, and control engineers and physicists develop their models using tools like Simulink and Stateflow. They are not programmers. So, what do we do when people have Simulink and Stateflow models from which code is automatically generated?

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COMAR: For these scenarios we have created a tunable code generator for Simulink and Stateflow called QGen that applies to the safest non-ambiguous parts of Simulink and generates source code for them. QGen is qualifiable to the highest levels of industry standards and is guaranteed to generate safe code that does not add security vulnerabilities.

Static analysis technologies supplement QGen, and a model verifier runs on top of these to provide added confidence that there are no security problems at the model level itself.

ECD: So, with SPARK, you can essentially avoid holes like those listed in the Common Weakness Enumeration?

GASPERONI: These databases look at the ambiguous parts of existing programming technologies or paradigms like C or C++ and identify ambiguities that can be exploited. They go on to describe the ambiguities and say, “Here’s an ambiguity and here’s what you can do to avoid it.”

But don’t forget that languages like C, C++, and Ada all came about before security was a big deal. These are existing technologies that started in the late ‘70s for C, and the ‘80s for Ada and C++.

Yes, all these languages have had several revisions since then, but there is a large installed base, and because we can’t change the past, the only weapon that we have is to look at the potential vulnerabilities in these languages and see how to address them. As a matter of fact, we have designed a static analyzer that checks for such vulnerabilities in Ada, called CodePeer.

SPARK was designed from the start not to have ambiguities.

This is by design.

One obvious benefit here is to lower software development costs, since the later you find a problem, the costlier it’s going to be to fix. And the relationship between when you find a bug and how expensive it is to remedy is not linear, it’s closer to exponential.

What we’re trying to do with SPARK is not only solve the issue where it is less costly, but also ensure that the issue never exists in the first place.

Franco Gasperoni is CEO and cofounder of AdaCore.

He has an engineering degree from Mines ParisTech and a PhD in computer science from New York University.

The thread that weaves itself throughout Franco’s work is the longstanding interest in social, economic, cybernetic, and engineering systems. Cyrille Comar is cofounder and president of AdaCore. After receiving a PhD in Computer Science in 1986, he began his career in academia as a Software Engineering Professor at Sup’Aero (Aeronautics Engineering School) in Toulouse, France. He joined the GNAT Project at New York University in 1993 and participated in the creation of the AdaCore offices first in the U.S. and then in Europe.

Adacore • www.adacore.com www.embedded-computing.com

AUTOMOTIVE TEST, MEASUREMENT & COMPLIANCE

The AUTOSAR C++ and MISRA C++ Integration and Adaptive Development: So Good, or So What?

By Mark Pitchford, LDRA

On January 29 of 2019, MISRA [Motor Industry Software Reliability Association] and the AUTOSAR partnership [AUTomotive Open System Architecture] announced that their two C++ language subsets are to be integrated together. The resulting guidelines will initially apply to versions up to and including ISO/IEC 14882 C++17, and will evolve on an ongoing basis to reflect the three-year release cycle for new versions of the C++ language.

G

uidelines adopted from AUTOSAR will be aligned with MISRA conventions and terminology, while the MISRA C++:2008 guidelines used as the base for the new document will benefit from improvements to their rationale and examples.

That sounds great on paper. But what will this new document offer in practice, and what will it mean for AUTOSAR application developers?

Language subsets The driving force for the adoption of language subsets (often referred to as “guidelines” or “coding standards”) arguably has less to do with AUTOSAR in particular than with functional safety and cybersecurity in general.

The functional safety standard “ISO 26262 Road vehicles – Functional safety” is considered obligatory across much of the modern automotive development world. The relationship between the system-wide ISO 26262-4:2011 and the software-specific subphases found in ISO 26262-6 can be represented in a V-model (Figure 1).

Both the new ISO 26262:2018 standard and the more familiar 2011 release collate hundreds of topics into dozens of tables to describe a process to follow in the creation of a functionally safe product.

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FIGURE 1 Softwaredevelopment V-model with cross-references to ISO 26262 and applicable development tools.

For today’s connected car, functional safety is only half the story. SAE J3061 provides guidance on best practices from a cybersecurity perspective, just as ISO 26262 provides guidance on practices to address functional safety. The recommendations in SAE J3061 are designed to complement the ISO 26262 process and call for broadly similar techniques with a cybersecurity focus.

Both ISO 26262 and SAE J3061 call for the use of language subsets because they help developers avoid troublesome parts of the language and make the resulting code more reliable, less prone to error, easier to test, and/or easier to maintain. Figure 2 shows just one example of how language subset violations can be presented.

A meeting of minds This newly announced language subset results from an agreement between the AUTOSAR partnership and the MISRA organization. The AUTOSAR partnership is a synergistic group of automotive OEMs and suppliers focusing on the continuous development of a reference architecture for vehicle ECU software.

Complementing the long-established Classic Platform for embedded systems with hard real-time and safety constraints, the Adaptive Platform is AUTOSAR’s solution

Embedded Computing Design RESOURCE GUIDE | Fall 2019

www.embedded-computing.com

Liverpool Data Research Associates (LDRA) www.ldra.com

LINKEDIN

www..linkedin.com/company/ ldra-limited/

YOU TUBE

www.youtube.com/channel/ UCMSwhp4rgyV8fo-0TlMeqqw

You CAN get it...

Hardware & software for CAN bus applications

AUTOMOTIVE TEST, MEASUREMENT & COMPLIANCE

FIGURE 2

Highlighting violated coding guidelines in the LDRA tool suite.

for high-performance computing ECUs to build safety-related systems for use cases such as highly automated and autonomous driving. Classic Platform applications are developed in C, while those for the Adaptive Platform are developed using C++.

MISRA is also a collaboration between manufacturers, component suppliers, and engineering consultancies, but is best known for its language subsets. Although MISRA was born out of the automotive sector, these days its guidelines are in common use across many safety and security sectors including medical devices, industrial, aerospace, and rail transportation.

PCAN-MicroMod FD Universal plug-in module with I/O functionality and CAN FD interface. Available with an evaluation board for the development of custom applications.

During the process of defining the environment for the Adaptive Platform, AUTOSAR needed a language subset to support C++14 and subsequent evolutions of the language. MISRA C++ was considered admirable but it was published in 2008 to support C++03 and so was not sufficiently up to date.

Unaware of MISRA’s existing commitment to update MISRA C++:2008, AUTOSAR supplemented MISRA C++:2008 with its own rules to create the AUTOSAR C++14 guidelines, leading to two parallel developments of roughly the same thing. The January 2019 announcement resolves that situation by amalgamating the latest efforts of the AUTOSAR partnership with those of MISRA.

PCAN-miniPCIe FD CAN FD interface for PCI Express Mini slots. Available as single-, dual-, and fourchannel version with drivers for Windows ® and Linux.

The impact on AUTOSAR application development The embedded development world in general is long overdue to get a de facto C++ language subset and for a commitment to its ongoing maintenance as the language evolves. The joint announcement is to be applauded just for that.

However, any simplification and streamlining of rules and regulations is particularly welcome for AUTOSAR application developers. There are already enough challenges in complying with the demands of the ISO 26262 functional safety standard, the SAE J3061 cybersecurity guidelines, and the protocols defined by the AUTOSAR standard itself without the selection of a language subset being needlessly complicated.

Commonality between the AUTOSAR Adaptive and Classic platforms is helpful – a fact already reflected in the AUTOSAR Foundation Standard, which contains requirements and technical specifications applicable to both. The adoption of MISRA conventions and terminology for the integrated C++ language subset to be used in Adaptive applications will align with the MISRA C guidelines already used for Classic developments. This helps simplify the lives of anyone involved with both platforms and making it very clear which is the “right” coding standard to use.

Mark Pitchford has over 25 years’ experience in software development for engineering applications. Since 2001, he has worked with development teams looking to achieve compliant software development in safety- and security-critical environments, working with standards such as DO-178, IEC 61508, ISO 26262, IIRA, and RAMI 4.0. www.embedded-computing.com

PCAN-Gateways Linux based product line for long distance connections between different CAN buses via IP networks.

Configuration with a comfortable web interface.

Available in different versions.

www.peak-system.com

Embedded Computing Design RESOURCE GUIDE | Fall 2019

25

ADVERTORIAL

EXECUTIVE SPEAKOUT

WIND RIVER’S TAKE ON SECURITY Embedded Computing Design (ECD) recently sat down with Wind River’s Chief Security Architect Arlen Baker to discuss the latest trends in security.

ECD: What is Wind River’s stance on security?

BAKER: For Wind River, security is protecting our customers’ digital assets. Security is embedded in everything that we do. Even with product support, security is always top of mind, and we ensure our software solutions can work in a variety of different critical infrastructure environments, where security is more important than ever.

ECD: What does that mean for your customers’ embedded devices and how do you protect those systems once they’re in the field?

BAKER: We’ve found that security means different things to different people. We’ve taken the industry standard Confidentiality, Integrity, and Availability (CIA Triad) model used to define security, which we’ve broken down into security related implementations. First, it helps educate our customers so they can understand what it means to secure their device, given they’re coming at security from different perspectives.

Second, we want to make sure that we are the customers’ trusted advisor and that we walk the journey with them from day one through design and develop through the time the device hits the field and is deployed. Using our Helix Security Framework, essentially the decomposition of the CIA Triad, becomes our systematic approach in working with customers to secure their devices.

ECD: Many vendors make the same claim that security is part of their DNA. If I’m a developer, why should I go with Wind River over a competitor?

BAKER: While security concerns are industry-, and even company-specific, Wind River products contain fundamental security features that span vertical markets. These features include encryption/decryption, digital signature generation and verification, Diffie-Hellman key establishment, and cryptographic attestation.

ECD: How does Wind River protect a product throughout its lifetime, not just at the time of development?

BAKER: We have a process in place where we monitor and triage the common vulnerabilities and exposures (CVEs) as they apply to the third-party components that are in our products. If we determine it applies to our products, we ensure that the applicable patches are integrated into our products, thoroughly tested, and released to our customers in the next iteration of our release cycle.

ECD: The Internet of Things (IoT) makes security a more difficult challenge because there are so many more points of vulnerability. How does Wind River handle that?

BAKER: With these different vulnerability issues, it comes down to how the device is fielded and how it’s used.

As we saw with the recent Urgent 11 vulnerability, what’s most important is having vendors like Wind River with a long track record of developing, delivering, and supporting secure development processes and products to ensure products are developed as securely as possible out of the gate and respond immediately when new vulnerabilities are discovered. We encourage and participate in responsible security research and disclosure as the best way to counter the threats to all types of devices, and to mitigate any threat to our customers when they are discovered.

ECD: How do the various Wind River products specifically enable security?

BAKER: Across our portfolio, we provide a comprehensive set of security features to efficiently and effectively safeguard devices, data, and intellectual property in the connected world, securing it while it is at rest inside devices and when it travels across the network and into cloud environments. Our built-in security features and services security offerings, along with our development processes, meet rigorous security requirements across industries.

ECD: How do you think the security landscape will be changing over the next 18 months?

BAKER: First, 5G is going to finally enable a massive proliferation of connected devices, which will generate/ drive massive amounts of data (where the bad guys can hide), posing significant security risks. The only way to solve this problem of finding and preventing malicious activity hiding in massive data sets is to apply machine learning techniques.

Second, the shift from on-prem development to public cloud, and in many cases multi-cloud, based on things like spot pricing, is requiring the application of security policies and in some cases just basic governance controls across predeployment cloud workloads (i.e., kubernetes, containers, serverless compute).

Maintaining consistent security and governance as workloads that move back and forth across different public cloud providers is an emerging area that we expect will continue to move up the stack in terms of priority for CISO’s and CIO’s.

And finally, we’re seeing changes in cryptography and quantum computing, which impact current cryptographic algorithms, both symmetric and asymmetric.

ADVERTORIAL

EXECUTIVE SPEAKOUT

MITYSOM-A10S:

ARRIA 10 SYSTEM ON MODULE AND DEVELOPMENT KITS CRITICAL LINK’S LATEST PRODUCTION-READY, INDUSTRIAL PERFORMANCE SOM Open Architecture for User-Programmability Critical Link’s MitySOM-A10S is an Intel/Altera Arria 10 SoC SOM (system on module) developed exclusively for industrial applications. It is a production-ready board-level solution that delivers industrial performance and includes a range of configurations to fit your requirements.

Why choose a Critical Link SOM? Critical Link’s support is unmatched in the industry, including our application engineering and online technical resources. We provide production-ready board-level solutions in a range of configurations. With Critical Link SOMs, it’s about time: Time to market, time to focus on company IP, and product lifetime.

The MitySOM-A10S has been designed to support several upgrade options including various speed grades, memory configurations, and operating temperature specifications (including commercial and industrial temperature ranges).

› Built for long term production, with 10-15+ year availability › Proven track record for product performance in the field › Base board design files and other resources available online at no cost › Lifetime product maintenance and support

Customers using the MitySOM-A10S receive free, lifetime access to Critical Link’s technical support site, as well as access to application engineering resources and other services. Critical Link will also provide developers the design files for our base boards, further accelerating design cycles and time to market.

Specifications › Up to 480KLE FPGA fabric › Dual-Core Cortex A9 processors › 4GB DDR4 HPS shared memory › 2GB DDR4 FPGA memory › 12 high speed transceiver pairs, up to 12.5Gbps › Max 138 Direct FPGA I/Os, 30 shared HPS/FPGA I/Os › Supports several high-level operating systems, including Linux out of the box › Designed for long life in the field with 24/7 operation (not a reference design) Flexible, Off-the-Shelf Board Level Solution for Industrial Applications Leverage the SoC’s dual core ARM and user-programmable FPGA fabric to do more embedded processing with 40% less power. 12 high speed transceiver pairs combined with Critical Link’s onboard memory subsystems make this SOM well-suited for the high-speed processing needs of the most cutting-edge industrial technology products. Example applications include: › › › › › › › ›

Test and Measurement Industrial Automation and Control Industrial Instrumentation Medical Instrumentation Embedded Imaging & Machine Vision Medical Imaging Broadcast Smart Cities / Smart Grid

Email us at info@criticallink.com or visit www.criticallink.com.

Embedded Computing Design Resource Guide

2019 Resource Guide AI & EDGE COMPUTING

INDUSTRIAL

Crystal Group

29

AI & MACHINE LEARNING

ACCES I/O Products

46

Apacer

47

Avnet

48

WDL Systems

30

congatec

49

Winmate

30

Dolphin ICS

47

Vector Electronics & Technology

45

COMS AND SOMS Technologic Systems

31

IOT WDL Systems

DEV TOOLS AND OSS Lauterbach

50, 51

Winmate

50

31, 32, 33

Quantum Leaps

32

PROCESSING Extreme Engineering Solutions (X-ES)

51

DEVELOPMENT KITS Digilent

34

SECURITY

Technologic

34

ADL Embedded Solutions

53

Wolf SSL

52

HARDWARE 35

Annapolis

35, 36, 37

Apacer

53

Dolphin ICS

38

Cervoz

55

EFCO Technology

38

Virtium

54

Enclustra

39

WDL Systems

55

MPL AG

40

Opal Kelly

40, 41

Pixus

42

Technologic Systems

44

VersaLogic

43

WDL Systems

28

STORAGE

AMTELCO

42, 44

Embedded Computing Design RESOURCE GUIDE | Fall 2019

www.embedded-computing.com

Edge Computing for IoT Crystal Group provides advanced connectivity kits for collecting and processing IoT data in the field, where office grade systems would fail. Designed for smart city, asset tracking, agriculture, smart grid, smart home, and transportation use cases, the system employs Ruckus E510 outdoor wireless access points (AP) which are connected to a Crystal Group ruggedized RCS7450 switch.

Behind this network is a Crystal Group FORCE™ RS2608 rugged scalable Xeon class server which can host GPUs. The Ruckus E510 is an 802.11ac Wave 2 wireless AP designed with a unique two element enclosure, which separates the RF components from the antenna module. This allows for flexible antenna placement when the AP must be placed inside a vehicle or other metal-shielded environment.

The Crystal Group RCS7450 switch family supports 24 and 48 copper or fiber ports, uses open standard protocols, and offers advanced stacking capabilities. The system can be configured with an IP-sec encryption module, which enables end-to-end encryption tunnels from the edge to the core, allowing customers to control network access, support multi-tenant networks, and protect data in flight.

The Crystal Group FORCE RS2608 is a rugged 2U server class platform designed for heavy industrial applications in uncon-

trolled environments. This high reliability system supports a Skylake 24 core Xeon CPU, 1TB of DDR4 RAM, and twelve 2.5" SSD drives.

The kit creates a capability for large IoT data ingress, reliable network connectivity, and advanced AI processing at the edge of the network. While cloud access is also possible, computing locally reduces latency, improves security, and eliminates cloud-based network throughput variations.

FEATURES ĄĄ ĄĄ

ĄĄ ĄĄ

ĄĄ

™

ĄĄ

High-speed data ingress and processing Ruckus BeamFlex+™ adaptive antennas to improve signal integrity Copper or fiber switch options Support for Wi-Fi and emerging IoT protocols in a single Access Point DoD certified, with IP-sec and AES 256 encryption for security GPU capable for DNN or CNN processing

crystalrugged.com/Edge-Computing-for-IoT/

Crystal Group, Inc. crystalrugged.com

www.embedded-computing.com



info@crystalrugged.com www.linkedin.com/company/crystal-group/

 800-378-1636 @CrystalGroup

Embedded Computing Design RESOURCE GUIDE | Fall 2019

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Embedded Computing Design Resource Guide

AI & Edge Computing

Embedded Computing Design Resource Guide

AI & Machine Learning Rogue Carrier for NVIDIA® Jetson AGX Xavier™ Connect Tech’s Rogue is a full featured Carrier Board for the NVIDIA® Jetson™ AGX Xavier™ module. This carrier board for Jetson AGX Xavier is specifically designed for commercially deployable platforms, and has an extremely small footprint of 92 x 105mm. The Rogue provides access to an impressive list of latest generation interfaces on the Jetson AGX Xavier while adding additional interfaces of 3x USB 3.1, 2x GbE, 2x HDMI and a locking Mini-Fit Jr. power input connector. Rugged camera add-on expansion boards will also be available for use with the Rogue to interface directly with the Jetson AGX Xavier high density MIPI CSI interfaces.

FEATURES Commercially deployable NVIDIA® Jetson™ AGX Xavier™ platform ĄĄ 6x 2-lane or 4x 4-lane MIPI CSI Camera Inputs ĄĄ 2x NVMe M.2 Key M Slots, 3x USB 3.1, 2x GbE ĄĄ Wide input power range 9-19V DC ĄĄ Dimensions: 92mm x 105mm (3.62"x 4.13")

ĄĄ

https://www.wdlsystems.com/wdlsystems-news-2019-pc104-sff-cti-xavier

WDL Systems



sales@wdlsystems.com

www.linkedin/company/wdl-systems

www.wdlsystems.com

 800.548.2319

@wdlsystems AI & Machine Learning

Embedded Computing System Box-IWAI Winmate Box-IWAI is a GPU v MXM 3.1 type A graphics module embedded computing system that comes with 4-CH PoE and AI Core XP4/XP8 PCIe x4 card, maximum to 8 Myriad X VPU’s for applications in machine vision, edge computing, traffic vision, deep learning, and AI of things. The Box-IWAI with enhanced GPU computing performance is powered by the 8th gen Intel® Core™ i7-8665UE Quad Core processor.

The fanless system is equipped with dual DDR4 ECC/non-ECC SO-DIMM slots for up to 32 GB of system memory. The Box-IWAI has four Gigabit 802.3 at (PoE, Power-over-Ethernet) compliant Ethernet ports with a total power budget of 60W, four USB 3.1 ports and Gigabit LAN to connect different devices or sensors. It comes with great expansion possibilities, including one internal PCIe x4 slot for Myriad X VPU AI card, one M.2 SATA III SSD or NVMe SSD. Supports M.2 Wireless LAN, M.2 WWAN/LTE and has built-in uBlox NEO M8N GPS module. The Box-IWAI has SATA HDD with a height of up to 9.5 mm and BIOS selectable RS-232/422/485. The Box-IWAI features a flexible window slot for incorporating application-oriented interfaces. Supports wall or DIN-rail mounting.

Winmate Box-IWAI – outstanding solution for edge computing application!

Winmate Inc.

www.winmate.com

30



FEATURES ĄĄ 8th Gen. Intel® Core™ i7-8665UE Whiskey Lake-U ĄĄ 4-CH PoE (IEEE802.3 at compliance) ĄĄ IEC 60068-2-64 Vibration, IEC 60068-2-27 Shock ĄĄ Supports HDMI ĄĄ 1 x 2.5" SATA HDD drive bay ĄĄ 1 x AI Core XP4/XP8 PCIe x4 card, maximum to 8 Myriad X

VPU’s (Optional)

ĄĄ Supports M.2 Wireless LAN, M.2 WWAN/ LTE and has built-in

uBlox NEO M8N GPS module

sales@winmate.com.tw

www.winmate.com/BoxPc/embedded_solution.asp

www.linkedin.com/company/winmate/

Embedded Computing Design RESOURCE GUIDE | Fall 2019

 886-2-8511-0288 @WinmateNews

www.embedded-computing.com

TS-4100 Computer on Module The TS-4100 is an extremely low power, high-performance Computer-onModule powered by NXP i.MX 6UltraLite ARM® Cortex®-A7 core operating up to 695 MHz. Typical power usage is about 300 mW, packed with up to 1 GB RAM, 4 GB eMMC flash, 32 bit programmable off-load engine, microSD with UHS support (up to 60 MB/s), WiFi and Bluetooth module with built-in antenna, and many industry-standard interfaces. It targets applications with strict power requirements, yet need a high-performance system with wireless connectivity, like industrial internet of things gateways, medical, automotive, industrial automation, smart energy, and many more.

The TS-4100 is Technologic Systems’ first CoM module that can also be a standalone micro Single Board Computer. When powered from the on-board micro USB connector, the TS-4100 does not require a baseboard to operate.

The system could be a processing node on a WiFi or Bluetooth network, or with the optional daughter card expansion connector, it could interact with other devices directly.

The TS-4100 FPGA includes a ZPU core implementation. The ZPU allows for offloading CPU tasks as well as harder real-time on I/O interactions. The ZPU is an open-source, 32-bit, stack-based CPU architecture that offers a full GCC tool suite.

Technologic Systems



www.embeddedARM.com

FEATURES ĄĄ

NXP i.MX 6UL (ARM Cortex-A7 @ 695MHz)

ĄĄ

4GB MLC eMMC

ĄĄ

Up to 1GB RAM

ĄĄ

MicroSD slot supporting Ultra High Speed bus interface

ĄĄ

WiFi 802.11 b/g/n; Bluetooth BLE www.embeddedarm.com/products/TS-4100

sales@embeddedarm.com

 480-837-5200

@ts_embedded Dev Tools and OSs

TRACE32 Multi Core Debugger for TriCore Aurix Lauterbach TriCore debug support at a glance: For more than 15 years Lauterbach has been supporting the latest TriCore microcontrollers. Our tool chain offers: • Single and multi core debugging for up to 6 TriCore cores • Debugging of all auxiliary controllers such as GTM, SCR, HSM and PCP • Multi core tracing via MCDS on-chip trace or via high-speed serial AGBT interface The Lauterbach Debugger for TriCore provides high-speed access to the target application via the JTAG or DAP protocol. Debug features range from simple Step/Go/Break up to AutoSAR OS-aware debugging. High speed flash programming performance of up to 340kB/sec on TriCore devices and intuitive access to all peripheral modules are included.

Lauterbach’s TRACE32 debugger allows concurrent debugging of all TriCore cores.

• Cores can be started and stopped synchronously.

• The state of all cores can be displayed side by side.

• All cores can be controlled by a single script.

Lauterbach, Inc.

www.lauterbach.com www.embedded-computing.com

FEATURES ĄĄ Debugging of all auxiliary controllers: PCP, GTM, HSM and SCR ĄĄ Debug Access via JTAG and DAP ĄĄ AGBT High-speed serial trace for Emulation Devices ĄĄ On-chip trace for Emulation Devices ĄĄ Debug and trace through Reset ĄĄ Multicore debugging and tracing ĄĄ Cache analysis

info_us@lauterbach.com  508-303-6812 www.lauterbach.com/pro/pro_tc3xx_aurix_as_alt1.php?chip=TC399XE%20A-STEP 

Embedded Computing Design RESOURCE GUIDE | Fall 2019

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Embedded Computing Design Resource Guide

COMs and SoMs

Embedded Computing Design Resource Guide

Dev Tools and OSs

Lauterbach Debugger for RH850 Lauterbach RH850 debug support at a glance: The Lauterbach Debugger for RH850 provides high-speed access to the target processor via the JTAG/LPD4/LPD1 interface. Debugging features range from simple Step/Go/Break to multi core debugging. Customers value the performance of high-speed flash programming and intuitive access to all of the peripheral modules.

TRACE32 allows concurrent debugging of all RH850 cores.

• The cores can be started and stopped synchronously.

• The state of all cores can be displayed side by side.

• All cores can be controlled by a single script.

All RH850 emulation devices include a Nexus trace module, which enables multi core tracing of program flow and data transactions. Depending on the device, trace data is routed to one of the following destinations: • An on-chip trace buffer (typically 32KB) • An off-chip parallel Nexus port for program flow and data tracing • A high bandwidth off-chip Aurora Nexus port for extensive data tracing The off-chip trace solutions can store up to 4GB of trace data and also provide the ability to stream the data to the host for long-term tracing, thus enabling effortless performance profiling and qualification (e.g. code coverage).

Lauterbach, Inc.

www.lauterbach.com

FEATURES ĄĄ AMP and SMP debugging for RH850, GTM and ICU-M cores ĄĄ Multicore tracing ĄĄ On-chip and off-chip trace support ĄĄ Statistical performance analysis ĄĄ Non intrusive trace based performance analysis ĄĄ Full support for all on-chip breakpoints and trigger features ĄĄ AUTOSAR debugging

 info_us@lauterbach.com  508-303-6812 www.lauterbach.com/pro/pro_r7f701325_alt1.php?chip=R7F701334A

Dev Tools and OSs QP™ Real-Time Embedded Frameworks Quantum Leaps’ QP™ real-time embedded frameworks (RTEFs) provide a reusable, modern software architecture based on event-driven active objects (actors) and hierarchical state machines, while our host-based tools support model-driven engineering, automatic code generation, software tracing and unit testing of embedded systems.

For over 15 years, our modern embedded software and development tools have been delivering competitive advantage to companies around the world in a wide variety of markets.

FEATURES ĄĄ Modern, event-driven QP™ real-time embedded frameworks

based on active objects (actors) and hierarchical state machines

ĄĄ Free, graphical QM™ modeling tool for designing UML

statecharts and automatic code generation based on QP™ frameworks

ĄĄ Comprehensive suite of tools for unit testing, software tracing,

monitoring and prototyping of deeply embedded systems.

Quantum Leaps, LLC

www.state-machine.com

32



info@state-machine.com

www.linkedin.com/company/quantum-leaps

Embedded Computing Design RESOURCE GUIDE | Fall 2019

 919-360-5668

www.embedded-computing.com

TRACE32 JTAG/ETM Debugger for ARMv8 Lauterbach ARMv8 support at a glance: More than 17 years of experience in ARM debugging enable Lauterbach to provide best-in-class debug and trace tools for ARMv8 based systems: • Multicore debugging and tracing for any mix of ARM and DSP cores • Support for all CoreSight components to debug and trace an entire SoC • Powerful code coverage and run-time analysis of functions and tasks • OS-aware debugging of kernel, libraries, tasks of all commonly used OSs Lauterbach debug tools for ARMv8 help developers throughout the whole development process, from the early pre-silicon phase by debugging on an instruction set simulator or a virtual prototype over board bring-up to quality and maintenance work on the final product.

FEATURES ĄĄ

Full support for all CoreSight components

ĄĄ

Full architectural debug support

ĄĄ

Support for 64-bit instruction set and 32-bit instruction sets ARM and THUMB

Debugger features range from simple step/go/break, programming of on-chip-flash, external NAND, eMMC, parallel and serial NOR flash devices, support for NEON and VFP units, to OS-aware debug and trace concepts for 32-bit and 64-bit multicore systems.

ĄĄ

32-bit and 64-bit peripherals displayed on logical level

ĄĄ

Support for 32-bit and 64-bit MMU formats

TRACE32 debuggers support simultaneous debugging and tracing of homogeneous multicore and multiprocessors systems with one debug tool.

ĄĄ

Ready-to-run FLASH programming scripts

ĄĄ

Multicore debugging

ĄĄ

On-chip trace support (ETB, ETF, ETR)

ĄĄ

Off-chip trace tools (ETMv4)

Start/Stop synchronization of all cores and a time-correlated display of code execution and data r/w information provides the developer with a global view of the system's state and the interplay of the cores.

High-tech company with long-term experience Technical know-how at the highest level Worldwide presence Time to market

Lauterbach, Inc.

www.lauterbach.com www.embedded-computing.com

ĄĄ

Auto-adaption of all display windows to AArch32/ AArch64 mode

AMP debugging with DSPs, GPUs and other accelerator cores

About our Products

Our Company Philosophy • • • •

ĄĄ

• • • • •

Everything from a single source Open system Open user interface for everything Long-term investment through modularity and compatibility The full array of architectures supported

info_us@lauterbach.com  508-303-6812 www.lauterbach.com/pro/pro_zynq-ultrascale_alt1.php?chip=ZYNQ-ULTRASCALE+



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Embedded Computing Design Resource Guide

Dev Tools and OSs

Embedded Computing Design Resource Guide

Development Kits

TS-7553-V2 Single Board Computer The TS-7553-V2 Single Board Computer hits on all the main points for low power, cost-effective, Internet-ofThings (IoT) capable, and ready-to-deploy OEM board with an emphasis on data integrity.

The TS-7553-V2 offers the ability to communicate seamlessly with several different networks simultaneously from a single device. Using the onboard peripherals the system can connect to Ethernet, WiFi, Bluetooth, USB, RS-232, RS-485, and CAN networks or devices. Built-in module interfaces like the XBee/NimbeLink socket and internal USB ports allow expansion to other networks like Cellular, DigiMesh, ZigBee, Lora, and other proprietary or industry-specific networks. This ability to communicate over a wide variety of wired and wireless interfaces puts the TS-7553-V2 in an excellent position to be an IoT node or gateway.

TS-7553-V2 with Nine-Axis Micro-Electro-Mechanical System (MEMS) motion tracking device containing a gyroscope, accelerometer, and compass is an on-board option for asset management, fleet management, and other applications which would require sensing motion or vibration in the environment.

The TS-7553-V2 is also well suited for applications that require a simple HMI interface. With an off-the-shelf, low-cost enclosure that can include a backlit monochrome 128x64px LCD and four-button keypad, it is easy to create interactive menus for the user.

Technologic Systems

www.embeddedARM.com



sales@embeddedarm.com

FEATURES ĄĄ

NXP i.MX6UL 696 MHz ARM Cortex-A7 CPU

ĄĄ

512 MB DDR3 RAM

ĄĄ

4 GB MLC eMMC Flash

ĄĄ

40 °C to 85 °C Temperature Range

ĄĄ

10+ Year Lifecycle Guarantee

www.embeddedarm.com/products/TS-7553-v2  480-837-5200

@ts_embedded Development Kits

ZedBoard Advanced Image Processing Kit The ZedBoard Advanced Image Processing Kit was built to use the video processing capabilities of the Zynq-7000 AP SoC’s tightly coupled ARM processing system and 7-series programmable logic. Included in the bundle is a Zedboard, an FMC Pcam Adapter and up to four Pcams to create the ultimate video streaming setup.

Users can take advantage of our project demonstrations to get started: • ZedBoard FMC Pcam Adapter: One to Four Camera Demo • ZedBoard FMC Pcam Adapter: Two Camera Demo

FEATURES ĄĄ ZedBoard is a complete development kit for Xilinx Zynq-7000 AP SoC ĄĄ FMC Pcam Adapter adds multiple cameras to your Zynq APSoC platform ĄĄ Pcam 5C, 5 MP Fixed Focus Color Camera Module, supports QSXGA@15Hz,

1080p@30Hz, 720p@60Hz, VGA@90Hz and QVGA@120Hz

Eventually, users can develop high speed engines for video processing, advanced video algorithms, video content analysis, processing digital video in real time, intelligent vision solutions, and any embedded vision application.

https://store.digilentinc.com/zedboard-advanced-image-processing-kit/

Digilent Inc, A National Instruments Company digilent.com

34



sales@digilentinc.com

www.linkedin.com/company/digilent-inc-

Embedded Computing Design RESOURCE GUIDE | Fall 2019

 509-334-6306 @DigilentInc

www.embedded-computing.com

AMTELCO Dual Span T1/E1 to VoIP Gateway Appliance The AMTELCO T1/E1 to VoIP Gateway Appliances provide a self contained Asterisk® LTS switching environment with an integrated T1/E1 dual span digital interface. Bidirectional connection of each B-channel on the digital spans to a corresponding SIP channel on the Ethernet interface is implemented through standard Asterisk dialplan entries. The gateway unit includes an internal web server allowing userprogrammable T1/E1 span settings and arrangement of the Asterisk dialplan through a custom designed web interface (accessible through any standard web browser).

Additional connectivity to the operating system for administration of the Linux environment or Asterisk utilities is available through SSH. External LED indicators provide visual confirmation of T1/E1 alarm states.

The AMTELCO Gateway Appliances can be powered from the network using Power over Ethernet (PoE), or using an included DC wall adapter.

An integrated fan provides for internal component cooling, and an external power switch is included for controlled shutdown and startup of the appliance.

Additional VoIP Gateway models are available including a 2-8 port FXO (Loop Start) to VoIP Gateway, as well as a 2-port or 4-port E&M to VoIP Gateway Appliance for reliable 4-wire Radio Interface applications.

FEATURES ĄĄ Direct configuration and administration is acccomplished using

any standard web browser.

ĄĄ A Linux operating system and a standard LTS Asterisk switching

environment provides core functionality.

ĄĄ Appliances are available in both ISDN single-span and dual-span

models.

ĄĄ High impedance line monitoring is available on dual-span models.

ĄĄ Flexible power options are supported including Power over Ethernet

(IEEE 802.3 PoE) or an optional AC wall adapter (included).

ĄĄ 32GB memory is provided, along with a 10/100/1000 Mbps

Ethernet interface.

ĄĄ Compact, convenient size for easy installations

[92mm x 160mm x 48mm]

AMTELCO



https://xds.amtelco.com/xds-telephony-gateway-appliances

xds@amtelco.com

 800-356-9224

www.linkedin.com/company/amtelco @AmtelcoXDS

Hardware

WILD100™ EcoSystem Brings 100GbE to OpenVPX In 2018, Annapolis was the first company to bring 100Gb bandwidth to OpenVPX. The WILD100 EcoSystem is 2.5X faster than existing technology, and enables PCIe Gen-4, 100 Gbps Ethernet, and InfiniBand high-speed bandwidths. This breakthrough capability is made possible by 25Gbps+ FPGA transceivers and high-density MULTIGIG RT3 interconnects. The WILD100 EcoSystem is a growing, interoperable portfolio of rugged high-performance OpenVPX COTS boards and systems that are used for the most challenging data acquisition, digital signal processing, and data storage applications. It is VITA 65 compliant and SOSA-aligned, MADE IN designed and built in USA, and ideallysuited for rugged embedded commercial U. S. A. and defense deployments.

Annapolis Micro Systems, Inc.

FEATURES Ą Higher ADC/DAC bandwidths (10+ GSps)

Ą Superior ADC/DAC density (1,000s of coherent synchronized channels Ą Ą Ą Ą Ą Ą

per system) 100Gb backplane, switches, and FPGA processing boards Storage capacity up to 64 TB per 6U slot Blind mate optical and/or RF connections (VITA 66/67), for systems that are easier to field and maintain Optional hot swappability Includes Open Project Builder™ – VHDL or GUI-based Aligns with SOSA™ technical standard

www.annapmicro.com wfinfo@annapmicro.com  410-841-2514 

www.annapmicro.com/product-category/openvpxsystems/ www.embedded-computing.com

WILD100 Systems are built for extreme environments, with Air, Conduction, AFT, and/or LFT cooling.

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WILD FMC+ GM60 ADC & DAC with RFSoC The WILD FMC+ GM60 ADC & DAC is the industry’s first COTS Mezzanine to feature the Xilinx® Zynq® UltraScale+™ RF System-on-Chip (RFSoC) technology (ZU25DR, ZU27DR, or ZU28DR).

This breakthrough RFSoC combines FPGA processing and A/D and D/A Converters in a single chip, giving the GM60 card remarkable density and performance.

For maximum performance, pair one GM60 with an Annapolis WILDSTAR 3U OpenVPX or PCIe Baseboard, or pair two GM60 with a 6U OpenVPX Baseboard. Annapolis WILDSTAR Baseboards utilize up to four high-performance FPGAs, in addition to the GM60’s RFSoC. Also designed for standalone use, the GM60 is ideal for applications limited by Size, Weight, Power, and Cost (SWaP-C). This small package option is readily-deployed in UAVs, backpacks, handheld devices, and custom-integrated applications.

GM60 shown mounted to 3U Baseboard with blindmate RF out the backplane (VITA 67.3)

FEATURES Ą

Ą

Ą

Ą

Ą

Ą

The GM60 is compatible with next generation Xilinx RFSoCs

ADC • Channels: 4 • Max Sample Rate: 4.0 GSps • Resolution: 12 bit • Other configurations available DAC • Channels: 4 • Max Sample Rate: 6.4 GSps • Resolution: 14 bit • Other configurations available I/O Connectors • Optional 50Ω SSMC or VITA 67 • Deliver superior analog performance Mechanical and Environmental • Air- or conduction-cooled Comprehensive and Flexible BSP • Utilize VHDL or CoreFire Next Application Design Suite • Software and firmware full examples • Manipulate existing IP and add your own • Latest Vivado (2019.1) support Clock Synchronization • Software-selectable external clock input or onboard PLL clock • All ADCs and DACs across multiple cards easily synchronized

MADE IN

U. S. A.

www.annapmicro.com/products/wild-fmc-gm60-adc-dac/

Annapolis Micro Systems, Inc. www.annapmicro.com

36



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wfinfo@annapmicro.com

 410-841-2514

www.embedded-computing.com

WILDSTAR UltraKVP ZP for PCIe combines an MPSoC with 1 or 2 UltraScale or UltraScale+ FPGAs

WILDSTAR™ FPGA Board for PCIe – WBPXUW

FEATURES ĄĄ General Features

The WILDSTAR UltraKVP ZP combines the latest Xilinx Kintex UltraScale or Virtex UltraScale+ FPGAs with a powerful quad core Zynq UltraScale+ MPSoC. This PCIe Baseboard is designed to tackle the most challenging data processing applications.

• Up to two Xilinx® Kintex® UltraScale™ XCKU115 or Virtex® UltraScale+™ XCVU5P / XCVU9P / XCVU13P FPGAs • – Up to 24,576 DSP Slices per board • – Up to 7,560,000 logic cells per board • – Hard 8x PCIe Gen3 endpoint for DMA and register access • – FPGAs programmable from attached flash or • Annapolis-provided software API • IOPE DDR4 DRAM ports on all FPGAs running up to 2400 MT/s • Xilinx Zynq® UltraScale+ MPSoC Motherboard Controller XCZU3EG • PLX PCI Express Gen3 Switch • System Management

High Density I/O WILD FMC+ (WFMC+™) next generation I/O site supports 32 HSS and 100 LVDS I/O for higher density ADC and DAC solutions. WFMC+ also supports card stacking, for maximum performance per slot.

Secure In addition to high performance, the Zynq+ is Xilinx’s most secure solution – it has multiple levels of hardware and software security.

Rugged & Reliable

ĄĄ Application Development

• Full Board Support Package for fast and easy application development • Develop in Open Project Builder™ GUI environment or create VHDL and use HDL environment • Board control and status monitoring can be local (stand-alone), remote (via Ethernet), or hybrid (both local and remote)

Annapolis FPGA boards are field-proven to perform at the highest levels in challenging environments.

Proven EcoSystem WILDSTAR boards are all part of the WILD100 EcoSystem™, an interoperable portfolio of rugged high-performance OpenVPX and PCIe COTS boards and systems.

ĄĄ Front Panel I/O

• • • • • •

Designed & Manufactured in USA All Annapolis products are engineered and manufactured under one roof in the United States. This co-location of engineering and manufacturing allows for more aggressive design, and better quality control and production flexibility.

WILD FMC+ (WFMC+) next generation I/O site – Accepts standard FMC and FMC+ cards (complies to FMC+ specification) – Supports stacking (2 I/O cards per site) – Up to 32 High Speed Serial and 100 LVDS pairs connections to FPGA

ĄĄ Mechanical and Environmental

MADE IN

• • • •

U. S. A.

10.5" length for wider chassis compatibility Does not require a “Full Length” slot Integrated heat sink and board stiffener External +12V power connector

www.annapmicro.com/product-category/fpga-boards-2/

Annapolis Micro Systems, Inc. www.annapmicro.com www.embedded-computing.com



wfinfo@annapmicro.com

 410-841-2514

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Hardware

MXH93X Gen4 Adapter card MXH93X Adapters come in various formats supporting transparent and non-transparent operations. Based on Microsemi Switchtec® Gen4 PCI Express bridging architecture, the MXH93X adapters include advanced features and clock isolation. The cards combine 256 Gbit/s performance with an application to application latency below 500 nanoseconds.

The MXH930 Gen4 PCIe Host Adapter is Dolphin’s clustering product that supports the full Dolphin eXpressWare™ software stack. Inter-processor communication benefits from the high throughput and low latency of Gen 4 PCI Express. Advanced DMA features enable fast data transfers to host and device memory. In addition, Dolphin’s SmartIO technology enables sharing of remote GPUs, FPGAs and NVMe drives. Using the latest SmartIO technology software GPU/Cuda applications can now stream data to remote GPUs at the same speed as to local GPUs. The MXH932 Gen4 PCIe is Dolphin’s Transparent Host/Target Adapter for connecting servers to external I/O subsystems. Based on Microsemi® Gen4.0 PCI Express bridging architecture, the MXH932 adapter enables reliable transparent PCIe cable connections and clock isolation. For high performance application, such as GPU farms, test and measurement equipment, medical equipment, and storage subsystem, the MXH932 delivers flexibility and performance with extremely high data quality.

Dolphin ICS



FEATURES ĄĄ PCI EXPRESS 4.0 SPECIFICATION COMPLIANT ĄĄ ONE X16 PCIe EDGE PORT AND FOUR X4 PCIe CABLE

PORTS

ĄĄ 256 GBIT/S PERFORMANCE WITH <0.5 MICROSECOND

LATENCY

ĄĄ QUAD SFF-8644 CONNECTOR SUPPORTING PCIe 4.0 OR

MINISAS-HD CABLES

ĄĄ NON-TRANSPARENT AND HOST/TARGET TRANSPARENT

BRIDGING

ĄĄ PCIe eXpressWare SOFTWARE SUPPORT

info@dolphinics.com

 603-747-4100

www.linkedin.com/company/dolphin-interconnect-solutions

www.dolphinics.com

Hardware

EverFine Group

Eagle Eyes

EFCO Eagle Eyes is a next-generation intelligent system for a variety of embedded applications. Equipped with state-of-the-art 6th/7th Generation Intel® Core™ i3/i5/i7 processor, Eagle Eyes supports up to twelve independent Gigabit PoE+ IEEE802.3at IP cameras.

Eagle Eyes is equipped with a proprietary artificial intelligence algorithm called eKit. The special software along with an ARM chip integrated in the device monitors the system parameters and evaluates its measured values.

The Dynamic Display Moule (DDM), a small OLED display on the front of the system, informs users about the device status and displays the measured values and/or error messages. With an API, user software can then be used to access the ARM controller or the display.

長豐科技集團

The compact design is ideal for machine vision, automation and spaceconstrained applications. The hardware design is also optimized so that customers do not need to purchase additional add-on cards for isolated DIO or PoE functions, design their own remote switches or power ignition system.

長豐智能科技

There are 6 different I/O module (IOM) options which can be added to fulfill customers’ needs without the extra effort and cost of customization. With the development of Industrial Internet of Things (IIoT), it opens up even more diverse possibilities for applications.

EFCO Technology

www.efcotec.com

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Embedded Computing Design RESOURCE GUIDE | Fall 2019



FEATURES ĄĄ Remote on/off power switch design ĄĄ Power ignition control design

ĄĄ Software control USB devices without plugging and unplugging

USB devices

ĄĄ USB security latch reserve designed for system security ĄĄ Option for isolated DIO or GPIO design

ĄĄ Easy maintenance for RTC battery tray, push-push SIM slot and

swappable 2.5" HDD

ĄĄ Flexible installation method: desktop, wall mount, DIN rail

sales-us@efcotec.com

 +1-702-848-5320

www.embedded-computing.com

Cut Your Time-to-Market Reducing the time-to-market is a multiplier: not only does it give you a competitive advantage, it also frees up engineering capacity to start the development of your next product earlier.

Enclustra's comprehensive ecosystem of SoC and FPGA modules, as well as IP cores and development services, all help to shorten development time.

How to reduce development time and risk Focusing on core competencies, reusing proven building blocks and consulting a domain specialist is an established practice to reduce development time and risk. As a vendor-independent solution provider, Enclustra can help solve the most complex FPGA design challenges whilst delivering a full solution including firmware, hardware, and software. By specializing in forward-looking FPGA technology, and with extremely broad application knowledge, Enclustra can offer ideal solutions at minimal expense in many areas, be it high-speed hardware, HDL firmware, embedded software, specification support, implementation, prototype production – or any combination of the above. Enclustra also develops and markets highly-integrated FPGA modules and FPGA-optimized IP cores, that further help reduce development time.

The compact Enclustra Mercury+ AA1 module, with Intel Arria 10 SoC, is ideally suited to demanding applications.

modules can be plugged into the same base board to easily adapt a system to changing requirements.

The newest family members are the extremely powerful Mercury+ XU8, built around the Xilinx Zynq UltraScale+ and the Mercury+ AA1, based on the Intel Arria 10 SoC. Both SoC modules combine features like fast SDRAM, eMMC flash, quad SPI flash, PCIe, Gigabit Ethernet, USB and power supply into a package of just 74 × 54 mm. All Enclustra modules are available in industrial temperature range, and with a planned availability of at least 10 years.

The Enclustra Mercury+ XU8 is built around Xilinx’s Zynq UltraScale+ MPSoC with features like fast DDR4 SDRAM, eMMC flash, quad SPI flash, Gigabit Ethernet and USB 3.0, making it a complete and powerful embedded processing system.

FPGA Design-in made easy Thanks to Enclustra’s FPGA and SoC modules, design-in of forward looking FPGA technology has never been easier. Enclustra offers 20 different module families and two different form factors: customers have a wide choice from a growing portfolio of different module variants, built around devices from Intel and Xilinx. Thanks to the modular and pin-compatible approach, more powerful or cheaper

Enclustra GmbH

www.enclustra.com www.embedded-computing.com

Enclustra also offers a comprehensive ecosystem for its SoC modules, offering all required hardware, software and support materials. The Enclustra Build Environment allows the end-user to get Linux up and running in minutes; with a few clicks, Linux can be compiled, generating the required U-Boot, Linux and BusyBox-based root file system binaries.

Enclustra’s proven IP Cores provide another way of shortening time to market; the meticulously-tested cores allow customers to fully concentrate their resources on their target application, making the most of their core competencies. Amongst others, Enclustra offers a Drive Controller IP core to control BLDC, DC or stepper motors, a Display Controller, which enables the easy addition of a display to any FPGA design, or the FPGA Manager IP solution, which allows for easy and efficient data transfer between a host and a FPGA over different interface standards like USB 3.0, Gigabit Ethernet and PCI-Express.



info@enclustra.com

 + 41 43 343 39 43

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Hardware

Embedded Computers up to 9th Gen. i7 Core & Xeon The PIP & MXCS Family are powerful, highly integrated, robust and fanless rugged embedded computers, based on Intel’s Mobile Technology, all out of the Embedded Roadmap for long-time availability. The Systems represent a unique solution for today’s demanding requirements and are available with basically unlimited options.

They are designed to operate under extreme and normal conditions without the need of fans. The MPL solutions are designed and produced in Switzerland and come with a long-term availability guarantee.

Outstanding is the extreme low power consumption. The systems have a complete set of standard PC features as well as industrial features like wide DC input power, reverse polarity protection, etc. Additional GPS, WLAN, CAN, Sound, and UPS modules are available.

FEATURES Ą Ą Ą Ą Ą Ą Ą

Soldered CPU and chipset Up to 128GB ECC DDR4 Up 5x Gigabit Ethernet & Fiber, up to 4 serial ports (RS232/485) Internal & external PCIe expansion Internal PMC/XMC expansion Fanless operation, optional -40°C up to 85°C Long term availability (10+ years)

www.mpl.ch

MPL AG Switzerland www.mpl.ch



T h i n k L o n g - Te r m – T h i n k M P L

info@mpl.ch

www.linkedin.com/company/mpl.ch

 +41 56 483 34 34

@MPL_AG

Hardware

XEM7310MT Reduce time and effort on product development by integrating the XEM7310MT into your next design. A production-ready module with a highly-capable Xilinx Artix-7 FPGA, 1 GiByte DDR3 SDRAM, and SuperSpeed USB 3.0 host interface utilizing Opal Kelly’s FrontPanel SDK, the XEM7310MT offers a small form factor for easy integration with your product.

With ample logic resources, 136 user I/O and three Samtec connectors for high-performance peripheral connectivity, the XEM7310MT is wellsuited to a wide variety of applications such as high-end data acquisition required for LIDAR, RADAR, advanced metrology, remote sensing, and software-defined radio.

Opal Kelly’s FrontPanel SDK provides real-world transfer rates in excess of 340 MiB/s. FrontPanel includes a multi-platform (Windows, Mac, Linux) API, binary firmware for USB controller, and lightweight atomic HDL modules to integrate into your FPGA logic. FrontPanel is the industry’s most full-featured, high-performance, turnkey solution for professional-grade USB connectivity. https://opalkelly.com/products/xem7310mt/

Opal Kelly Incorporated www.opalkelly.com

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Embedded Computing Design RESOURCE GUIDE | Fall 2019

FEATURES Xilinx Artix-7 (A75 and A200 densities available) ĄĄ 1-GiByte DDR3 SDRAM, 2x 16-MiB serial flash ĄĄ 136 user I/O including 5 MRCC pairs, 6 SRCC pairs, and 1 XADC pair ĄĄ 1 multi-gigabit transceiver quad ĄĄ Low-jitter 200 MHz clock oscillator ĄĄ Three 0.5mm Samtec board-to-board connectors ĄĄ Complete Application Programmer’s Interface (API) in C, C++, C#, Ruby, Python, and Java ĄĄ



sales@opalkelly.com

opal-kelly-incorporated

 217-391-3724

@opalkelly

www.embedded-computing.com

XEM7360 The XEM7360 Kintex-7 based FPGA module offers a turnkey SuperSpeed USB 3.0 host interface using Opal Kelly's FrontPanel SDK. System integrators can build fully-operational prototype and production designs quickly by integrating this device into their product. Manufacturers of high-speed devices such as JESD-204B data acquisition devices can launch fully-functional evaluation systems without the costly design and maintenance of an evaluation platform.

With ample logic resources, the Kintex-7 is well-suited for signal processing, image processing, and other logic-heavy acceleration tasks.

Memory-hungry applications enjoy access to 2 GiB of on-board DDR3 memory with a 32-bit wide data bus.

Celebrating over 10 years of USB FPGA connectivity, Opal Kelly’s FrontPanel SDK fully supports the XEM7360 for real-world transfer rates in excess of 340 MiB/s. FrontPanel includes a multi-platform (Windows, Mac, Linux) API, binary firmware for the on-board Cypress FX3 USB controller, and atomic HDL modules to integrate into your design. FrontPanel is the industry's most full-featured, high-performance, turnkey solution for professional-grade USB connectivity.

Opal Kelly Incorporated

FEATURES Xilinx Kintex-7 XC7K160T or XC7K410T ĄĄ 2 GiB DDR3, 2x 16 MiB serial flash ĄĄ Two Samtec QSH-090 expansion connectors ĄĄ Up to 193 user I/O + 8 Gigabit Transceivers ĄĄ Low-jitter 200 MHz and 100 MHz clock oscillators ĄĄ Integrated voltage, current, and temperature monitoring ĄĄ Small form-factor: 100mm x 70mm x 19.65mm ĄĄ

https://opalkelly.com/products/xem7360/ 

sales@opalkelly.com

 217-391-3724

opal-kelly-incorporated

www.opalkelly.com

@opalkelly

Hardware

XEM8350 The XEM8350 Kintex UltraScale based FPGA module offers a turnkey dual Super-Speed USB 3.0 host interface using Opal Kelly’s FrontPanel SDK. System integrators can build fully-operational prototype and production designs quickly by integrating this device into their product. Manufacturers of high-speed devices such as JESD-204B data acquisition devices can launch fully-functional evaluation systems without the costly design and maintenance of an evaluation platform.

As an industry first, the XEM8350 features two fully-independent SuperSpeed USB 3.0 ports for high-bandwidth applications requiring duplex operation or over 650 MB/s bandwidth. The FrontPanel SDK includes a multi-platform API (Windows, macOS, and Linux) and very low logic utilization on the FPGA.

FEATURES ĄĄ Dual SuperSpeed USB 3.0 ports for high-bandwidth data transfer ĄĄ Xilinx Kintex UltraScale XCKU060 or XCKU115

Memory-hungry applications enjoy access to 4 GiB of on-board DDR4 memory with a 64-bit wide data bus and ECC.

ĄĄ 4 GB DDR4 SDRAM with (64-bit with ECC)

Typical applications include ultra high-performance data acquisition such as: • Remote Sensing • LIDAR and RADAR • Photonics • Video / Image Capture • Advanced Metrology • Software-Defined Radio (SDR) • Data Ingestion Acceleration • 5G Systems

ĄĄ 28 multi-gigabit transceivers

Opal Kelly Incorporated www.opalkelly.com

www.embedded-computing.com

ĄĄ Over 330 I/O pins on three Samtec QTH connectors ĄĄ Small form-factor: 145mm x 85mm ĄĄ On-board programmable oscillator

https://opalkelly.com/products/xem8350/ 

sales@opalkelly.com

opal-kelly-incorporated

 217-391-3724

@opalkelly

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Embedded Computing Design Resource Guide

Hardware Handles, panels, card guides, and specialty components With a modular design based on the Rittal brand of eurocard components, Pixus can provide virtually unlimited configurations of enclosure solutions.

From rackmount, desktop, or rugged solutions, Pixus’ high reliability designs make your product stand out from the pack. Products include handle/panel sets, card guides, enclosure kits, rails, sidewalls, PCB covers, gasketing, filler panels, and more. Pixus also provides modifications to components that are tailored to your design requirements.

FEATURES High reliability handle/panel sets for embedded plug-in boards ĄĄ Virtually limitless enclosure configurations for backplane-based systems or for electronics devices ĄĄ Designs for OpenVPX, cPCI Serial, ATCA, MTCA, VME, cPCI & more ĄĄ Customization, cutouts, silkscreening, painting, & other options ĄĄ Extensive expertise in embedded computing solutions ĄĄ Ruggedized options in standard and customizable types ĄĄ

Enclosures

Cases

Subracks

Backplanes

Chassis

Integrated Systems

Components

 info@pixustechnologies.com @pixustech  519-885-5775 or West Coast Sales 916-297-0020

Pixus Technologies

www.pixustechnologies.com

Hardware ADLINK’s PC/104 Family of SBCs ADLINK’s PC/104 Family of Single Board Computers (SBCs) deliver optimized versatility and are designed in popular compact form factors with field-proven reliability, durability, and performance in applications for market verticals such as military, aerospace, medical, automation, and edge computing. ADLINK’s PC/104 family products provide unmatched fanless operation over temperature extremes, resistance to shock and vibration, conformal coating, embedded BIOS, and 15+ years of product longevity for a wide array of embedded computing applications and rugged systems.

FEATURES ADLINK’s PC/104 Family of Single Board Computers includes: ĄĄ PCI/104-Express Type 1 SBCs with 6th Gen. Intel® Xeon®: CM4-SL4, CM4-SL2 ĄĄ PC/104-Plus PCI-104 SBC with Intel® Atom™: CM3-BT4 ĄĄ PCI-104 SBC with Intel® Atom™: CM3-BT1 ĄĄ PC/104-Plus SBC with Intel® Atom™: CM2-BT2 ĄĄ PC/104 SBC with Intel® Atom™: CM1-BT1 ĄĄ PC/104 SBC with Vortex86DX3 SoC: CM1-86DX3 https://www.wdlsystems.com/wdlsystems-news-2019-ecd-adlink-pc104-sbcs

WDL Systems

www.wdlsystems.com

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

sales@wdlsystems.com

www.linkedin/company/wdl-systems

Embedded Computing Design RESOURCE GUIDE | Fall 2019

 800.548.2319

@wdlsystems www.embedded-computing.com

C

O

R

P

O

R

A

T

I

O

N

Grizzly (ESU-5070) The Grizzly is a rugged embedded server unit (ESU) featuring an Intel 16-core processor, two 10 Gigabit Ethernet SFP+ ports, four Gigabit Ethernet ports, and up to 128 GB of ECC memory. This combination makes it ideal for applications requiring very high performance processing and high data bandwidth. Additionally, two Mini PCIe sockets and a PCIe x4 M.2 site provide for on-board I/O expansion and high speed/high-capacity on-board storage. The Grizzly also contains additional interfaces including USB, serial and digital I/O, and SATA. The high performance capability of the Grizzly make it ideal for situations where data gathering and processing need to be kept local for security or latency reasons, or to provide local cloud capability. A 16-core processor coupled with up to 128 GB of ECC memory supports the use of hypervisors for the running of virtual machines.

The 10 Gigabit SFP+ ports permit very high speed connectivity. Networks can be created using plug-in copper, short-reach fiber, or long-reach fiber transceivers.

The Grizzly is based on the COM Express Extended form-factor, but it is delivered as an assembled and tested, production-ready embedded computer. Like all VersaLogic products, the Grizzly is engineered and tested to be rugged. It is fully validated for operation in unforgiving environments with extreme temperatures and mechanical shock and vibration. Each component has been carefully sourced, and the design optimized and validated, to ensure reliable operation in the field.

FEATURES ĄĄ ĄĄ

ĄĄ ĄĄ

ĄĄ

ĄĄ

ĄĄ ĄĄ

Intel® 16-core server-class processor High performance computing and I/O processing -40°C to +85°C Operation Operates over full industrial temperature range Four SO-DIMM support an industryleading 128 GB of ECC memory Industry leading capacity and eError correcting RAM safeguards critical applications Two 10 Gigabit Ethernet (SFP+) Supports two high speed copper or fiber connections

VersaLogic’s 10+ year product life support programs ensure long-term deployment in the field, free from expensive upgrades and migrations that come from short, disposable life cycle products.

https://promo.versalogic.com/grizzly-ecdguide

VersaLogic

versalogic.com www.embedded-computing.com



Sales@VersaLogic.com  503-747-2261 or 800-824-3163 www.linkedin.com/company/versalogic-corporation/ @versalogic

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Hardware

TS-7800-V2 Single Board Computer Powered by the Marvell Armada 385 Dual Core 1.3 GHz ARM CPU, the TS-7800-V2 industrial Single Board Computer stands out from the crowd with its high-performance components, connectivity options, and an unbelievable feature set packaged into a small footprint in both size and power. It's a general-purpose, low-power SBC ready to tackle demanding applications including data acquisition, IoT, industrial automation, and anything in between.

Data is reliably stored in the onboard eMMC flash. With the included heat sink, the fanless design of the TS-7800-V2 is able to withstand high vibration, and even with two CPU cores running at 1GHz and tasked to their max, the system can operate at a wide temperature range of -40 °C to 85 °C. Out-of-the-box experience includes pre-installed Linux OS, development tools, and utilities for controlling PC104 peripheral boards, DIO, CAN bus, a variety of serial interfaces and bringing in data from the analog ports, or monitoring the system temperature. The development kit makes sure you have all the necessary connections and cables to get off the ground quickly. The guaranteed 10+ year lifecycle ensures a long-term deployment in the field, free from expensive replacements that come from short, disposable lifecycles which are all too common.

Technologic Systems

www.embeddedARM.com



FEATURES ĄĄ

Marvell Armada 385 Dual Core 1.3 GHz ARM CPU

ĄĄ

1 GB RAM

ĄĄ

4 GB eMMC Flash

ĄĄ

20k LUT Cyclone FPGA (145 Various I/O Pins)

ĄĄ

110x GPIO

www.embeddedarm.com/products/TS-7800-v2

sales@embeddedarm.com

 480-837-5200

@ts_embedded Hardware

High Quality Modules for Embedded Designs TQ-Systems manufactures innovative embedded modules for optimized solutions in a wide range of architectures. TQ-Systems is known for its design and support services which are backed by deep application and vertical market expertise in Medical, Aerospace, Industrial Automation, Automotive, Energy, and Telecommunication. TQ’s product portfolio is unique in that they support three processor cores: ARM, x86, and PowerPC solutions from NXP, TI, and Intel. WDL Systems is an authorized distributor of TQ-Systems’ high quality COM Express (COMe) Modules, SMARC Modules and System On Modules (SOMs).

FEATURES TQ-Systems portfolio of modules includes: ĄĄ COMe (COM Express): featuring the latest Intel processors supporting Type 10 Mini, Type 6 Compact, and Type 6 Basic ĄĄ SMARC: featuring both x86 and ARM processors, including Intel's Atom and NXP's iMX8 processor families ĄĄ SOMs (System on Modules): featuring NXP and TI processors, including ARM Cortex and the high speed QorIQ processing platform https://www.wdlsystems.com/landing-ee-ic-tq-systems-modules

WDL Systems

www.wdlsystems.com

44



sales@wdlsystems.com

www.linkedin/company/wdl-systems

Embedded Computing Design RESOURCE GUIDE | Fall 2019

 800.548.2319

@wdlsystems www.embedded-computing.com

A FINE TECHNOLOGY GROUP

cPCI, PXI, VME, Custom Packaging Solutions VME and VME64x, CompactPCI, or PXI chassis are available in many configurations from 1U to 12U, 2 to 21 slots, with many power options up to 1,200 watts. Dual hot-swap is available in AC or DC versions. We have in-house design, manufacturing capabilities, and in-process controls. All Vector chassis and backplanes are manufactured in the USA and are available with custom modifications and the shortest lead times in the industry.

Series 2370 chassis offer the lowest profile per slot. Cards are inserted horizontally from the front, and 80mm rear I/O backplane slot configuration is also available. Chassis are available from 1U, 2 slots up to 7U, 12 slots for VME, CompactPCI, or PXI. All chassis are IEEE 1101.10/11 compliant with hot-swap, plug-in AC or DC power options.

FEATURES ĄĄ

Made in the USA

Our Series 400 enclosures feature side-filtered air intake and rear exhaust for up to 21 vertical cards. Options include hot-swap, plug-in AC or DC power, and system voltage/temperature monitor.

Embedded power supplies are available up to 1,200 watts.

ĄĄ

Most rack accessories ship from stock

Series 790 is MIL-STD-461D/E compliant and certified, economical, and lighter weight than most enclosures available today. It is available in 3U, 4U, and 5U models up to 7 horizontal slots.

ĄĄ

Card sizes from 3U x 160mm to 9U x 400mm

ĄĄ

System monitoring option (CMM)

ĄĄ

AC or DC power input

ĄĄ

Power options up to 1,200 watts

All Vector chassis are available for custom modification in the shortest time frame. Many factory paint colors are available and can be specified with Federal Standard or RAL numbers.

ĄĄ

Modified ‘standards’ and customization are our specialty

For more detailed product information,

VISIT OUR NEW WEBSITE!

please visit www.vectorelect.com

WWW.VECTORELECT.COM

or call 1-800-423-5659 and discuss your application with a Vector representative.

Made in the USA Since 1947

Q U A L I T Y S Y S T E M S PA C K A G I N G A N D P R O T O T Y P E P R O D U C T S

Vector Electronics & Technology, Inc. www.vectorelect.com

www.embedded-computing.com



inquire@vectorelect.com

 800-423-5659

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Embedded Computing Design Resource Guide

Industrial

mPCIe-ICM Family PCI Express Mini Cards The mPCIe-ICM Series isolated serial communication cards measure just 30 x 51 mm and feature a selection of 4 or 2 ports of isolated RS232/422/485 serial communications. 1.5kV isolation is provided port-to-computer and 500V isolation port-to-port on ALL signals at the I/O connectors. The mPCIe-ICM cards have been designed for use in harsh and rugged environments such as military and defense along with applications such as health and medical, point of sale systems, kiosk design, retail, hospitality, automation, and gaming.

The RS232 ports provided by the card are 100% compatible with every other industry-standard serial COM device, supporting TX, RX, RTS, and CTS. The card provides ±15kV ESD protection on all signal pins to protect against costly damage to sensitive electronic devices due to electrostatic discharge. In addition, they provide Tru-Iso™ port-to-port and port-to-PC isolation. The serial ports on the device are accessed using a low-profile, latching, 5-pin Hirose connector. Optional breakout cables are available, and bring each port connection to a panel-mountable DB9-M with an industry compatible RS232 pin-out.

The mPCIe-ICM cards were designed using type 16C950 UARTS and use 128-byte transmit/receive FIFO buffers to decrease CPU loading and protect against lost data in multitasking systems. New systems can continue to interface with legacy serial peripherals, yet benefit from the use of the high performance PCI Express bus. The cards are fully software compatible with current PCI 16550 type UART applications and allow for users to maintain backward compatibility.

ACCES I/O Products, Inc. www.accesio.com



FEATURES ĄĄ PCI Express Mini Card (mPCIe) type F1, with latching I/O connectors ĄĄ 4 or 2-port mPCIe RS232/422/485 serial communication cards ĄĄ Tru-Iso™ 1500V isolation port-to-computer and 500V isolation

port-to-port on ALL signals

ĄĄ High performance 16C950 class UARTs with 128-byte FIFO for each

TX and RX

ĄĄ Industrial operating temperature (-40°C to +85°C) and RoHS standard ĄĄ Supports data communication rates as high as 3Mbps – 12MHz with ĄĄ ĄĄ ĄĄ ĄĄ

custom crystal Custom baud rates easily configured ±15kV ESD protection on all signal pins 9-bit data mode fully supported Supports CTS and RTS handshaking

contactus@accesio.com

linkedin.com/company/acces-i-o-products-inc.

 858-550-9559 twitter.com/accesio

Industrial

USB3-104-HUB – Rugged, Industrial Grade, 4-Port USB 3.1 Hub Designed for the harshest environments, this small industrial/military grade 4-port USB 3.1 hub features extended temperature operation (-40°C to +85°C), locking USB and power connections, and an industrial steel enclosure for shock and vibration mitigation. The OEM version (board only) is PC/104-sized and can easily be installed in new or existing PC/104-based systems as well. The USB3-104-HUB makes it easy to add USB-based I/O to your embedded system or to connect peripherals such as external hard drives, keyboards, GPS, wireless, and more. Real-world markets include Industrial Automation, Security, Embedded OEM, Laboratory, Kiosk, Military/Mission Critical, Government, and Transportation/Automotive.

This versatile four-port hub can be bus powered or self (externally) powered. You may choose from two power inputs (power jack and terminal block) to provide a full 900mA source at 5V on each of the downstream ports. Additionally, a wide-input power option exists to accept from 7VDC to 28VDC. All type A and type B USB connections feature a locking, high-retention design.

ACCES I/O Products, Inc. www.accesio.com

46

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FEATURES ĄĄ Rugged, industrialized, four-port USB 3.1 hub ĄĄ USB 3.1 Gen 1 with data transfers up to 5Gbps (USB 2.0 and 1.1 compatible) ĄĄ Extended temperature (-40°C to +85°C) for industrial/military grade applications ĄĄ Locking upstream, downstream, and power connectors prevent accidental disconnects ĄĄ SuperSpeed (5Gbps), Hi-speed (480Mbps), Full-speed (12Mbps), and Low-speed (1.5Mbps) transfers supported ĄĄ Supports bus-powered and self-powered modes, accessible via DC power input jack or screw terminals ĄĄ LED for power, and per-port RGB LEDs to indicate overcurrent fault, High-Speed, and SuperSpeed ĄĄ Wide input external power option accepts from 7-28VDC ĄĄ OEM version (board only) features PC/104 module size and mounting compatibility

contactus@accesio.com

linkedin.com/company/acces-i-o-products-inc.

Embedded Computing Design RESOURCE GUIDE | Fall 2019

 858-550-9559 twitter.com/accesio

www.embedded-computing.com

XR-DIMM

FEATURES DDR4 ĄĄ On-DIMM thermal sensor ĄĄ 16 internal banks (4 Bank Groups) ĄĄ Support ECC error detection and correction ĄĄ Employs mounting holes to enhance shock resistance ĄĄ Dual anti-shock certifications: RTCA DO-160G, MIL-STD-810G ĄĄ

Apacer’s rugged memory XR-DIMM uses the innovative board-to-board connector design to fit tightly and securely onto the motherboard. In addition, it adopts the highly durable 300-pin connector and mounting holes to effectively prevent memory modules from dislocating or coming away due to vibration or strong impact. This greatly improves the reliability of memory signal transmissions, serving as the strongest support for applications working under severe environments.

The XR-DIMM’s sealed board-to-board connector is designed to cope with the severe environments, avoiding the traditional memory’s gold finger’s problem of possible oxidation when exposed to outdoor contaminating environments. Also, the XR-DIMM’s Underfill technology further strengthens its anti-vibration ability and thermal shock resistance.

Meanwhile, the Apacer XR-DIMM also supports the guaranteed industrial grade wide-temp chips and has a built-in thermal sensor to monitor the memory’s temperature, effectively preventing the memory module from overheating. Additionally, the Conformal Coating and AntiSulfuration technology ensures that the products can operate stably not only under humid and dusty environments but also environments where sulfur-containing gases pervade, providing a whole new option in industrial-grade memory. www.apacer.com

APACER

https://industrial.apacer.com/en-ww/DRAM-Specialty/XR-DIMM

 408-518-8699



ssdsales@apacerus.com

Industrial

PXH82X Gen 3 XMC Module PXH82X XMC Adapters come in various formats supporting transparent and non-transparent operations. PXH82X brings up to 128 GT/S connectivity and advanced connection features to embedded computers and carrier cards that support XMC mezzanine cards. The cards provide external connectivity with a quad SFF-8644 connector that supports standard MiniSAS-HD or PCIe 3.0 cables.

The PXH822 and PXH826 are Dolphin’s transparent host/target adapters. These quad SFF-8644 cable adapters support the new PCI SIG External Cabling Specification 3.0 enabling connections to compliant Dolphin products and third-party PCI Express cabled systems. The adapters can act as either hosts or targets when connecting to expansion chassis.

The PXH820 and PXH824 are Dolphin’s non-transparent host adapters. They come with Dolphin’s comprehensive PCIe NTB eXpressWare™ software suite that reduces time to market. eXpressWare™ software includes several components to support connecting systems, SOCs, FPGAs, and GPUs. It comes with a shared memory API (SISCI), sockets API, SuperSockets™, and a TCP/IP driver. These components create a robust and powerful programming environment for easy use of shared memory in multi host/root systems and removes the traditional network bottlenecks by taking advantage of high performance of the PCIe interconnect. eXpressWare™ delivers extremely low latency starting at 540 nanoseconds.

Dolphin ICS

www.dolphinics.com www.embedded-computing.com



FEATURES ĄĄ VITA 42.0 XMC 1.0/VITA 61.0 XMC 2.0 SUPPORT ĄĄ UP TO 128 GBIT/S PERFORMANCE ĄĄ X4, X8 OR X16 PCI EXPRESS HOST PORT ĄĄ QUAD SFF-8644 CONNECTOR FOR X4, X8 OR X16

PCIe CABLING

ĄĄ UP TO 9M COPPER AND 100M FIBER CABLES ĄĄ TRANSPARENT AND NON-TRANSPARENT BRIDGING ĄĄ PIO AND DMA RDMA SUPPORT

info@dolphinics.com

 603-747-4100

www.linkedin.com/company/dolphin-interconnect-solutions Embedded Computing Design RESOURCE GUIDE | Fall 2019

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Embedded Computing Design Resource Guide

Industrial

MSC SM2S-MB-EP5 with MSC SM2S-IMX8MINI SimpleFlex is the intelligent combination of a standard Computer-On-Module with a standard carrier board. It combines the advantages of Standard SBC and Custom SBC by choosing the COM from a huge portfolio of CPU and memory configuration.

The ready-to-use platform is cost-efficiently adapted with the selected interfaces and assembled in-house at fullautomatic production lines. For the customization, more than 30 pre-validated interface combinations are available.

SimpleFlex is therefore best suited for series production with large quantities.

For our application-ready Embedded Platform SMARC™ 2.0 choose the latest module: The MSC SM2S-IMX8MINI module features NXP’s i.MX 8M Mini processors that are based on the latest 14nm FinFET technology to allow high computing and graphics performance at very low power consumption combined with a high degree of functional integration.

MSC SM2S-IMX8MINI offers single-, dual- or quad-core ARM Cortex-A53 processors in combination with the ARM Cortex-M4 real-time processor and GC NanoUltra multimedia 2D/3D GPU. It provides fast LPDDR4 memory, up to 64GB eMMC Flash memory, Gigabit Ethernet, PCI Express, USB 2.0, an on-board Wireless Module as well as an extensive set of interfaces for embedded applications.

The module is compliant with the new SMARC 2.0 standard, allowing easy integration with SMARC baseboards. For evaluation and design-in of the SM2S-IMX8MINI module, Avnet Intergrated provides a development platform and a starter kit. Support for Linux is available (Android support on request). ™

MSC SM2S-IMX8MINI Features: • NXP™ i.MX 8M Mini ARM® Cortex™-A53 up to 1.8GHz • ARM Cortex-M4 Real Time Processor at 400MHz • Up to 4GB LPDDR4 SDRAM • Up to 64GB eMMC Flash • Up to 2x Gigabit Ethernet, 2 x CAN

FEATURES ĄĄ

SMARC™ 2.0 carrier board for short size modules

ĄĄ

Form Factor (146 x 80 mm)

ĄĄ

Input voltage 12 VDC to 36VDC

ĄĄ

LVDS/eDP/MIPI-DSI connector

ĄĄ

Up to two Gigabit Ethernet ports

ĄĄ

µHDMI/DisplayPort connector

ĄĄ

USB Type-C (with DisplayPort)

ĄĄ

Mini PCI Express Card slot

ĄĄ

M.2 key M slot

ĄĄ

ĄĄ

One USB 3.0 Type A, One USB 2.0 Type A, One USB 2.0 OTG port Two CAN (one CAN opt. galv. isolated) www.avnet.com/integrated

Avnet Integrated

www.avnet.com/integrated

48



Embedded Computing Design RESOURCE GUIDE | Fall 2019

integrated@avnet.com  +49 7249 910 0 www.linkedin.com/showcase/avnet-integrated/

www.embedded-computing.com

FEATURES The new conga-TC370 COM Express Type 6 modules, the conga-JC370 embedded 3.5 inch SBCs, and the conga-IC370 Thin Mini-ITX motherboards all feature:

Faster Innovation and time to market

ĄĄ The latest Intel® Core™ i7, Core™ i5, Core™ i3 and Celeron

With three optimized form factors for designers to choose from, congatec delivers a simpler, efficient way to harness the benefits of 8th Gen Intel® Core™ U-series processors for IoT. These products draw from congatec’s deep expertise in embedded and industrial design to offer an enriched feature set, along with long product availability, hardware and software customization, and value-added design support. As a result, OEMs and ODMs can build high-performing solutions with less development time and cost.

ĄĄ The memory is designed to match the demands of consolidating

embedded processors with a long-term availability of 10+ years. multi OS applications on a single platform: Two DDR4 SODIMM sockets with up to 2400 MT/s are available for a total of up to 64GB.

ĄĄ USB 3.1 Gen2 with transfer rates of 10 Gbps is supported

natively, which makes it possible to transfer even uncompressed UHD video from a USB camera or any other vision sensor.

ĄĄ Supports a total of 3 independent 60Hz UHD displays with up

Performance at the edge Specially designed for embedded use conditions in which space and power are limited, 8th Gen Intel Core U-series processors provide high performance for edge devices with up to four cores. This enables a wide range of designs at 15W TDP, configurable down to 12.5W.

to 4096x2304 pixels as well as 1x Gigabit Ethernet (1x with TSN support).

ĄĄ The new boards and modules offer all this and many more

interfaces with an economical 15W TDP that is scalable from 10W (800 MHz) to 25W (up to 4.6 GHz in Turbo Boost mode).

congatec products based on these processors deliver high-quality visual, audio, and compute capabilities with integrated graphics and high-definition media support.

• Ensure exceptional graphics performance while helping lower BOM costs with integrated Gen 9.5 Intel® Graphics with up to 24 execution units.

• Deliver on rising expectations for video

performance with 4K/UHD content support, plus accelerated 4K hardware media codecs. Designs can support up to three displays.

• Develop media and video applications

with the Intel® Media SDK, which provides tools and an API enabling hardware acceleration for fast video transcoding, image processing, and media workflows.

• Create better audio experiences with enhanced speech and audio

quality from microphones, voice activation and wake from standby, and enhanced playback with Intel® Smart Sound Technology and Intel’s programmable quad-core audio DSP, designed for low power consumption.

congatec products based on 8th Gen Intel Core U-series processors also help bring artificial intelligence (AI) to more places. With high processing and integrated graphics performance, combined with the optimized Intel® Distribution of OpenVINO™ toolkit, these processors improve inference capabilities like facial recognition, license plate recognition, people counting, and fast and accurate anomaly detection on manufacturing lines.

www.congatec.us

congatec

www.congatec.us www.embedded-computing.com



sales-us@congatec.com www.linkedin.com/company/congatec-ag

 858-457-2600 twitter.com/congatecAG

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Embedded Computing Design Resource Guide

IoT MultiConnect® Dragonfly™ & Dragonfly™ Nano MultiConnect® Dragonfly™ and Dragonfly™ Nano embedded cellular modems and SoMs are fully-certified and MNO approved, ready-to-integrate modules that offer developers the functionality of a programmable computing platform with the convenience of an onboard cellular radio all in one compact design. The Dragonfly Nano is over 50% smaller, maintains plug compatibility and uses the same 40-pin board-to-board connector or USB connector found in the standard sized Dragonfly.

FEATURES 4G-LTE Cat 1 and Cat M1 models ĄĄ Arm® Mbed™ OS enabled (SoM models) ĄĄ Integrated Cortex®-M4 processor on SoM models for hosting applications ĄĄ Low power modes extend life of battery-powered devices ĄĄ Multiple I/O interfaces for connecting almost any “Thing” ĄĄ

https://www.wdlsystems.com/wdlsystems-news-2019-ecd-multitech-dragonfly

WDL Systems



sales@wdlsystems.com

 800.548.2319

www.linkedin/company/wdl-systems

www.wdlsystems.com

@wdlsystems IoT

IoT Gateway EAC Mini EACIL20 Winmate EAC Mini EACIL20 is an industrial IoT gateway powered by energy efficient Intel® Apollo Lake N3350 processor with frequency 1.1 GHz, and has 4 GB LPDDR3 of system memory with 32 GB of eMMC storage by default that can be extended for up to 128 GB and optional mSATA up to 1 TB. In terms of connectivity the EACIL20 features two USB 3.0 ports, two RJ45 GigaLAN ports and HDMI port that supports 1920 x 1080 @60 Hz resolution. The EACIL20 can operate over a wide input voltage range of 9-36 V DC and has chassis ground for protection.

Designed as a variant of the modular gateway system, the EACIL20 is built to satisfy those that are value-oriented, with no compromises on the solid performance that our IoT gateway series provides. More than thirty expansion possibilities are available thanks to the expansion modules providing plentiful options for additional serial interfaces such as CANbus and digital I/O, or wireless connectivity options with 4G LTE. Wireless connectivity and all necessary connectors allow the EACIL20 to send data from manufacturing facilities directly to cloud servers, making it suitable for various IoT applications like smart factory or machine automation.

Connect everything, control everywhere!

FEATURES ĄĄ Certified for IoT – AWS IoT Greengrass, Microsoft Azure ĄĄ Intel® Apollo Lake N3350, 1.1 GHz ĄĄ Expansion module with 30+ combinations ĄĄ Wireless connectivity options with 4G LTE ĄĄ Onboard connectivity 2 x USB 3.0, 2 x RJ45 GigaLAN, 1 x HDMI ĄĄ Various mounting options: desk, wall, VESA, din-rail ĄĄ Compact size 100 x 70 x 31 mm

www.winmate.com/BoxPc/EmbeddedSpec.asp?Prod=05_0191&Typeid=B010807011802

Winmate Inc.

www.winmate.com

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sales@winmate.com.tw

www.linkedin.com/company/winmate/

Embedded Computing Design RESOURCE GUIDE | Fall 2019

 886-2-8511-0288 @WinmateNews

www.embedded-computing.com

MultiConnect® mDot™ & xDot® LoRa® Modules MultiConnect® mDot™ and xDot® are secure, CE/FCC/RCM/GITEKI certified, Arm® Mbed™ programmable, low-power RF modules, that provide long-range, low bit rate M2M data connectivity to sensors, industrial equipment and remote appliances. Both modules are LoRaWAN® 1.0.2 compliant, providing bi-directional data communication up to 10 miles/15 km line-of-sight and 1-3 miles/2 km into buildings, using sub-GHz ISM bands in North America, Europe, Australia and Asia Pacific (AS923). mDots and xDots bring intelligence, reduced complexity and a lower overall bill of material cost to the very edge of the network while supporting a variety of electronic interfaces to connect just about any “Thing” for years on battery power.

FEATURES Onboard flash and RAM reduces overall costs Unicast and Multicast message support ĄĄ Multiple I/O interfaces ĄĄ LoRaWAN Certified ĄĄ ĄĄ

https://www.wdlsystems.com/wdlsystems-news-2019-ecd-multitech-lora-modules

WDL Systems

www.wdlsystems.com



sales@wdlsystems.com

www.linkedin/company/wdl-systems

 800.548.2319

@wdlsystems Processing

XPedite7683 XPedite7683 is a secure, high-performance, 3U OpenVPX™, single board computer based on the Intel® Xeon® D-1500 family of processors. Providing up to 16 Xeon®-class cores, up to 32 GB of DDR4-2133 ECC SDRAM, and XMC support, the XPedite7683 is an optimal choice for computationally heavy applications requiring maximum data and information protection.

XPedite7683 integrates SecureCOTS™ technology with a Microsemi SmartFusion®2 security SoC for hosting custom functions to protect data from being modified or observed, and provides an ideal solution when stringent security capabilities are required. The Microsemi SmartFusion®2 can control, intercept, and monitor the Xeon® D subsystem, implement penalties, and interface to the system through GPIO directly connected to the VPX backplane. Circuit board enhancements and optimized Two-Level Maintenance (2LM) metalwork provide additional protection to the physical hardware.

XPedite7683 maximizes network performance with two 10 Gigabit Ethernet interfaces and two Gigabit Ethernet interfaces. It accommodates up to 32 GB of DDR42133 ECC SDRAM in two channels and up to 256 GB of onboard SATA NAND flash in addition to numerous I/O ports, including USB, SATA, and RS-232/422/485 through the backplane connectors. The XPedite7683 provides additional expansion capabilities with an integrated XMC site, which includes an x8 PCIe connection to the Intel® Xeon® D processor and X12d I/O mapped directly to the VPX backplane connectors.

Extreme Engineering Solutions (X-ES) www.xes-inc.com

www.embedded-computing.com



FEATURES ĄĄ Supports Intel® Xeon® D-1500 family processors (formerly

Broadwell-DE)

ĄĄ Up to 16 Xeon®-class cores in a single, power-efficient SoC

ĄĄ ĄĄ ĄĄ ĄĄ ĄĄ

sales@xes-inc.com

package. 4-, 8-, or 12-core SKUs available with native extended temperature support.

Up to 32 GB of DDR4-2133 ECC SDRAM in two channels Ruggedized Enhanced Design Implementation (REDI) per VITA 48 Designed with SecureCOTS™ technology to support enhanced security and trusted computing Microsemi SmartFusion®2 SoC with 1 GB DDR3-667 ECC SDRAM and 32 MB SPI flash Two 10 Gigabit Ethernet ports and two Gigabit Ethernet ports, four SATA ports, and two USB 2.0 ports www.xes-inc.com/products/sbcs/xpedite7683/

 608-833-1155

www.linkedin.com/company/extreme-engineering-solutions

@XES_INC

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Security

wolfSSL Embedded TLS Library wolfSSL provides embedded security solutions with an emphasis on

speed, size, portability, features, and standards compliance. wolfSSL is the #1 TLS and the first embedded TLS 1.3 implementation with TPM 2.0, MQTT, SSH, Secure Boot, hardware crypto acceleration, FIPS 140, and DO-178C certifications. wolfSSL is the most comprehensively tested and supported crypto available, securing more than 2 billion connections world wide! All products are backed by 24/7 support.

wolfCrypt

Embedded Crypto Engine written in ANSI C and targeted for embedded, RTOS, and resource-constrained environments. MISRA-C and DO-178 DAL A versions are available.

wolfCrypt FIPS

curl

Command-Line Tool & Library for transferring data with URLs, SSH, & TLS with Support for FIPS 140-2.

tinycurl

A version of curl that is capable of performing HTTPS and fits within 100K (including the wolfSSL library) on a typical 32 bit architecture.

It is approximately one-quarter of the size of the typical curl build on Debian-based Linux with an x86-64 architecture.

140-2 Cryptographic Module FIPS 140-2 Level 1 validated, with certificates #2425 & #3389. Federal departments and agencies using cryptographic-based security systems to protect sensitive (but unclassified) information are required by law to implement FIPS 140-2 cryptographic modules.

FEATURES

wolfTPM

ĄĄ Minimum footprint size of 20-100 kB, depending on build options

Portable TPM 2.0 Library Trusted Platform Module (TPM, also known as ISO/IEC 11889) is an international standard for a secure cryptoprocessor, a dedicated microcontroller designed to secure hardware through integrated cryptographic keys.

ĄĄ TLS versions 1.0, 1.1, 1.2, and 1.3 (client and server) ĄĄ DTLS 1.0, 1.2 support (client and server)

and operating environment

ĄĄ Runtime memory usage between 1-36 kB (depending on I/O

buffer sizes, public key algorithm, and key size)

ĄĄ OpenSSL compatibility layer ĄĄ OCSP, OCSP Stapling, and CRL support

wolfMQTT

Client implementation of the MQTT written in C for embedded use.

Built from the ground up to be multi-platform, small and extensible.

Supports all Packet Types, all Quality of Service(QoS) levels 0-2, and supports SSL/TLS using the wolfSSL library.

wolfSSH

Lightweight SSHv2 client and server library. Supports SCP and SFTP, the industry standard SSH v2, and offers progressive ciphers such as Poly1305, ChaCha20, NTRU, and SHA-3.

ĄĄ Hash Functions: MD2, MD4, MD5, SHA-1, SHA-224, SHA-256,

SHA-384, SHA-512, BLAKE2b, RIPEMD-160, Poly1305

ĄĄ Block, Stream, and Authenticated Ciphers: AES (CBC, CTR, GCM,

CCM, GMAC, CMAC), Camellia, DES, 3DES, IDEA, ARC4, RABBIT, HC-128, ChaCha20 ĄĄ Public Key Algorithms: RSA, DSS, DH, EDH, ECDH-ECDSA, ECDHE-ECDSA, ECDH-RSA, ECDHE-RSA, NTRU ĄĄ Password-based Key Derivation: HMAC, PBKDF2, PKCS#5

wolfBoot

Portable, OS-agnostic, secure bootloader solution for 32-bit microcontrollers, relying on wolfCrypt for firmware authentication, providing firmware update mechanisms.

wolfSSL INC

www.wolfssl.com

52



facts@wolfSSL.com

www.linkedin.com/company/wolfssl/

Embedded Computing Design RESOURCE GUIDE | Fall 2019

 425-245-8247

@wolfSSL

www.embedded-computing.com

Compact Embedded Computers Built with the latest rugged, industrial IoT and cyber security needs in mind, ADL Embedded Solutions’ family of fanless, industrial PC solutions meet the performance and size requirements of a multitude of IIoT applications. The heart of ADL’s compact embedded system designs are the Intel® Atom® E3800 or E3900-based SBCs as small as 75mm x 75mm.

These standalone SBCs are the building blocks for our compact systems as small as 1.3" x 3.4" x 3.2" and offer vertical or horizontal expansion possibilities using the Edge-Connect form factor to maintain a small footprint depending on your specific application uses. The expansion connector features a number of interfaces including PCIeX1, USB 2.0/3.0, SATA, SMBus and DisplayPort

FEATURES ĄĄ Ultra-small, compact footprint ĄĄ Intel® E3800 or E3900-Series

Atom processors ĄĄ Vertical or horizontal expansion

ADL offers a range of COTS peripheral modules that can easily be integrated for added I/O functions like CAN, Ethernet, GPIO, Serial COM, storage and much more. Customers can also define custom peripheral boards for special I/O or power supply requirements as well as the custom enclosures necessary for complete solutions.

www.adl-usa.com

ĄĄ Wide Temperature

ĄĄ Up to 15-year availability

ĄĄ Custom System Design Services available

Applications: Industrial IoT (IIoT) network and cloud computing, Cyber security edge devices for networks, ICS and SCADA threat security, Secure networking (routing, traffic monitoring and gateways), Intelligent machinery and equipment controllers, Unmanned or autonomous vehicle mission / payload computing, Traffic Engineering, Transportation mobile computing, Wind turbine datalogging and collision avoidance, Oil and Gas and Kiosk and ATM applications.

Custom PC Integration

ADL Embedded Solutions Inc.

ĄĄ Edge-Connect form factor

sales@adl-usa.com  855-727-4200 @ADLEmbedded www.linkedin.com/company/adl-embedded-solutions 

Storage

CFexpress PV130-CFX Apacer Industrial CFexpress PV130-CFX is the next generation Solid State Drive (SSD) with compact and removable storage to support larger, faster hosts deployed in a wide range of applications that require outstanding performance.

CFexpress is the merging of two standards: XQD 2.0 and CFast 2.0, into a new standard that uses the popular PCIe interface, and the NVM Express protocol. The combination of PCIe with flash memory is designed to meet future requirements for applications in various vertical markets.

PV130-CFX provides full compliance with the latest PCIe Gen3 x2 (two-lanes) and NVM Express 1.3 interface specifications, which allows the SSD to deliver exceptionally low latency and high performance, up to 1,550 MB/s read and 950 MB/s write. www.apacer.com

APACER

https://industrial.apacer.com/en-ww/SSD/PV130-CFX www.embedded-computing.com

FEATURES DataRAID™ ĄĄ CFX Type B Card ĄĄ 4K Page Mapping ĄĄ Supports LDPC ECC ĄĄ End-to-End Data Protection ĄĄ Thermal Management Technique ĄĄ Support HMB (Host Memory Buffer) ĄĄ

 408-518-8699



ssdsales@apacerus.com

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Embedded Computing Design Resource Guide

Security

Embedded Computing Design Resource Guide

Storage

®

Solid State Storage and Memory

Industrial-Grade Solid State Storage and Memory Virtium manufactures solid state storage and memory for the world’s top industrial embedded OEM customers. Our mission is to develop the most reliable storage and memory solutions with the greatest performance, consistency and longest product availability.

Classes include: MLC (1X), pSLC (7X) and SLC (30X) – where X = number of entire drive-writes-per-day for the 3/5-year warranty period.

Industry Solutions include: Communications, Networking, Energy, Transportation, Industrial Automation, Medical, Smart Cities and Video/Signage.

Memory Products include: All DDR, DIMM, SODIMM, Mini-DIMM, Standard and VLP/ULP. Features server-grade, monolithic components, best-in-class designs, and conformal coating/under-filled heat sink options.

Features

New! XR (Extra-Rugged) Product Line of SSDs and Memory:

• Broad product portfolio from latest technology to legacy designs • 22 years refined U.S. production and 100% testing • A+ quality – backed by verified yield, on-time delivery and field-defects-per-million reports • Extreme durability, iTemp -40º to 85º C • Industrial SSD Software for security, maximum life and qualification

• Leading innovator in small-form-factor, high-capacity, high-density, high-reliability designs

XR-DIMM Memory Modules have the same extra-rugged features as the SSDs, and include heatsink options and 30µ" gold connectors.

They also meet US RTCA DO-160G standards.

• Worldwide Sales, FAE support and industry distribution

Virtium



www.virtium.com

StorFly-XR SSDs enable multi-level protection in remote, extreme conditions that involve frequent shock and vibration, contaminating materials and/or extreme temperatures. Primary applications are battlefield technology, manned and unmanned aircraft, command and control, reconnaissance, satellite communications, and space programs. Also ideal for transportation and energy applications.

Currently available in 2.5" and Slim-SATA formats.

Include: custom ruggedization of key components, such as ultrarugged connectors and screw-down mounting, and when ordered with added BGA under-fill, can deliver unprecedented durability beyond that of standard MIL-810-compliant solutions.

• Longest product life cycles with cross-reference support for end-of-life competitive products

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StorFly® SSD Storage includes: M.2, 2.5", 1.8", Slim SATA, mSATA, CFast, eUSB, Key, PATA CF and SD.

sales@virtium.com www.linkedin.com/company/virtium

Embedded Computing Design RESOURCE GUIDE | Fall 2019

 949-888-2444 @virtium

www.embedded-computing.com

READY for 5G TECHNOLOGY With the coming generation of 5G technology, the volume of data will be explosive growth. Higher transmission, lower latency, and massive connectivity characteristics drive to develop Multi-access Edge Computing and accelerate IoT platforms to adopt faster data transfer speed and larger capacity storage and memory modules to handle data more efficiently.

Cervoz, as a leading Industrial Storage and DRAM module manufacturer, we launched a variety products to meet this aggressive challenge.

Visit Embedded World 2020 Hall 3-159 Cervoz Co., Ltd.

www.cervoz.com



FEATURES ĄĄ M.2 2280 NVMe SSD

• • • • •

Industrial Grade TLC NAND High IOPS End-to-End data protection Thermal throttling Capacity up to 1TB

ĄĄ DDR4 32GB 2666MHz DRAM Module

• High-Capacity • High-Performance (11% higher than DDR4 2400MHz) • Lower power consumption

sales@cervoz.com | info@cervoz.com

www.linkedin.com/company/cervoz/

 +886-2-2911-9599

Storage Swissbit's N-10m2 3D NAND-based Module WDL Systems proudly distributes Swissbit's new 2 lane PCIe M.2 3D NAND-based NVMe SSD module for embedded applications.

The N-10m2 PCIe module with M.2 form factor 2280 is an industrial grade PCIe 3.1, NVMe 1.2 M.2 module boasting a capacity range from 120 to 960 GB. The N-10m2 module is designed to work well in fanless, non-ventilated systems. The N-10m2 PCIe module works with just 2 PCIe lanes, rather than the typical 4 lanes, to deliver more than double the SATA speed with only half the power consumption.

FEATURES ĄĄ PCIe 3.1 NVMe 1.2, x2 lane M.2 2280 SSD module for

embedded and NetCom applications

ĄĄ True Industrial temperature grade 3D NAND (-40°C to 85°C) ĄĄ Up to 1600 MB/s read, 1000 MB/s write and 190 kIOPS

random operation

ĄĄ Low power consumption and high endurance ĄĄ Active and passive data care management

ĄĄ End-to-End (E2E) Data Protection, AES 256, TCG Opal 2.0

compliant

https://www.wdlsystems.com/wdlsystems-news-2019-ecd-swissbit-3d-nand-flash

WDL Systems

www.wdlsystems.com www.embedded-computing.com



sales@wdlsystems.com

www.linkedin/company/wdl-systems

 800.548.2319

@wdlsystems

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FLEX