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Embedded Computing Design | Spring 2020

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CONTENTS

Spring 2020 | Volume 18 | Number 1 opsy.st/ECDLinkedIn

FEATURES 6

@embedded_computing

2020 Embedded Processor Report: Back to the Future with Analog Computing

COVER

By Brandon Lewis, Editor-in-Chief

SIDEBAR: What’s Programmable Analog without Programming Tools?

By Perry Cohen, Associate Editor

12 The Buffer/Driver: What Is It, and Do I Need One?

By Bill Schweber, Contributing Author

14 Distributed Database Systems’ Relevance to the Internet of Things

@embedded_comp

14

In the Embedded World 2020 issue of Embedded Computing Design we examine the potential of analog computing technology for the low-power, high-performance workloads of the future. Embedded World Product & Company Profiles are also featured, starting on page 32.

By Steve Graves, McObject

18 5GBy CurtPrimer: RAN & Core Network Architectures Schwaderer, Technology Editor

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28 2020 DEVELOPMENT KIT ROUNDUP 32 2020 EMBEDDED WORLD PROFILES

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 Will 2020 Be the Year of LoRaNetworks?

By Majeed Ahmad, Contributing Author http://bit.ly/LoRaNetworks2020

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 IoT Device Security Conference March 26, 2020 Santa Clara, CA iotdevicesecurityconference.com

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COLUMNS 5

How smart is your car?

By Brandon Lewis, Editor-in-Chief

4

TRACKING TRENDS

Embedded Computing Design | Spring 2020

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TRACKING TRENDS

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How smart is your car?

By Brandon Lewis, Editor-in-Chief What an ambiguous, loaded question that has become?

These days, if someone asks you “How smart is your car?” it could mean almost anything. Is it a compact electric vehicle (recently discontinued in the U.S.)? Or, can your car drive itself? Does it speak to your equally-smart home? Or is it simply a shrewd investment?

Or, can your car determine who is driving based on how that person drives?

At CES 2020, the last question was answered for me by BlackBerry courtesy their CylancePERSONA technology.

CylancePERSONA is an AI-enabled endpoint analytics solution that performs continuous biometric analysis and user conduct monitoring. The technology was originally developed to help enterprises identify cyber criminals who had obtained valid user credentials and were using them to attack company networks. Only now, BlackBerry is deploying the tool to stop car thieves – or maybe just mischievous kids who took the family car when they weren’t supposed to.

Elsewhere at CES, Siemens was showcasing its PAVE360 digital twin environment, which uses high-fidelity modeling to simulate how vehicles perform in various operating environments. Through a partnership with Arm, the closed-loop solution is capable of running entire software stacks to verify not only vehicle dynamics, but electronic control units (ECUs) and sensors as well.

PAVE360 leverages multiple Siemens tools, including Simcenter Amesim and Simcenter Prescan. Amesim is the 1D modeling environment that houses highly accurate representations of components such as ECUs down to the RTL level. Prescan is a physics-based simulation environment that enables the testing and validation of advanced driver assistance systems (ADAS) under almost limitless conditions.

VIDEO 1

BlackBerry has integrated CylancePERSONA in its “Vehicle Operations Center” offering to ensure that drivers of a vehicle are known and trusted.

As demonstrated in Video 1, a fictional juvenile named Trevor takes his father Cedric’s key fob and starts driving the family car. Trevor takes Cedric’s key fob because predefined settings limit him to a certain speed when his own key fob is detected.

A short time later, CylancePERSONA recognizes that it is in fact Trevor, and not Cedric, who is driving, and relays this information to a Vehicle Operations Center. From there, several manual or automated actions can be taken, such as notifying Cedric via text message, calling the police, etc.

The integrated solution can even remotely manage the vehicle to restrict horsepower, prevent the engine from restarting, take a picture, or kill the engine altogether.

Obviously the solution is more applicable to enterprise fleet management than your average family, but it was a fun example.

CylancePERSONA is just one of several BlackBerry technologies that can be included in the Vehicle Operations Center solution. Others include the company’s QNX Hypervisor, the Jarvis binary code scanning tool, and of course the BlackBerry OTA Software Update Management Service.

How smart is your development?

CylancePERSONA is great for vehicle owners and fleet managers. But what about automotive engineers? www.embedded-computing.com

During a demonstration, Siemens engineers stepped through two driving scenarios. In the first scenario, an anti-lock braking system (ABS) ECU correctly deploys the brakes when a vehicle encounters a water spill, but the action results in the car colliding with oncoming traffic. Based on this outcome, the engineers modified the ADAS stack running on the Amesim twin so that the brakes were not applied in the second scenario, thus avoiding an accident.

The precision and accuracy of these physics-based representations is impressive to say the least. A full video recap of the Siemens demonstration is available on www.embedded-computing.com.

These were just two of many fascinating automotive technologies on display at CES 2020. And if they’re any indication, pretty soon no one will be asking how smart your car is.

They’ll all be very smart.

Embedded Computing Design | Spring 2020

5

EMBEDDED PROCESSING

2020 Embedded Processor Report: Back to the Future with Analog Computing

By Brandon Lewis, Editor-in-Chief

A

While studying at MIT, Claude Shannon, widely regarded as “the father of information theory,” worked extensively with the Differential Analyzer developed a decade earlier. The Differential Analyzer was essentially the first general-purpose analog computer, and Shannon’s experience with the machine would have a seminal influence on later works such as A Mathematical Theory of Communication.

bout the same time, Shannon’s contemporaries were making strides in digital computing systems that would be fully realized over the next two decades and culminate in the digital signal processing revolution of the 1970s and 80s.

new problems worth solving that digital solutions are not adequate for – specifically, the need for higher performance and at the same time the need for significantly lower power dissipation.”

But now, roughly 80 years after Shannon’s introduction to the Differential Analyzer, analog computing – and even analog signal processing – appear to be making a comeback.

As Moore’s law draws to a close, the need for lower power and higher performance will be felt in an increasing number of application areas. And it is already generating renewed interest in analog computation in tasks ranging from mixedsignal signal processing (MSSP) for neural network workloads to dynamic system simulation using differential equations.

Why? “There are two significant reasons,” said Gene Frantz, VP of Engineering at Octavo Systems and member of the design team responsible for the first digital signal processor, the Texas Instruments TMS5100.

“First, IC technology has advanced over the last five decades to make many of the things that were impossible or impractical now very doable,” Frantz continued. “Second, we are finding

6

Embedded Computing Design | Spring 2020

Back to basics with physical simulation To illustrate the most basic advantages of analog computing, consider processing analog signals that are described by a set of differential equations. Because continuous time doesn’t exist in a digital computing paradigm, a digital computer must sample the input every clock cycle to develop a sample signal.

This can result in many, many computations, which has the www.embedded-computing.com

EMBEDDED PROCESSING

cascading effect of higher latency, increased power consumption, and so on.

Compare this the massive parallelism of an analog computer.

Rather than deconstructing inputs into sequential tasks, analog computing circuitry can be configured as basic units (adders/ subtractors, multipliers, integrators, fanouts, nonlinear functions, etc.) to solve the differential equations in question, and then sample the entire input signal continuously (Figure 1).

Analog computing chips are capable of executing differential equations significantly faster and at much lower power than digital alternatives. And while one drawback of analog computers is that you have to scale the system linearly with the size of the equation you’re trying to solve, their massive parallelism means that the power and performance benefits scale as well.

FIGURE 1 Analog computers contain integrators, multipliers, function generators, and other circuit blocks.

Continuous-time circuitry forms blocks capable of creating arbitrary functions.

Limited benchmarks support these claims. Figure 2 compares the power consumption and time taken to solve the Van der Pol equation on Sendyne’s Apollo IC versus a 25 MHz Texas Instruments MSP430 MCU. The Sendyne Apollo IC is a 4 x 4 mm general-purpose analog computer fabricated on CMOS technology. The chip, originally developed by a team of researchers at Columbia University, contains 16 analog integrators and uses 1 V circuitry to generate outputs at the expense of only microjoules of energy. It also contains specialized ADCs that minimize conversion costs.

Van der Pol Equation Time to solve

Energy to solve 1 00,000

2

1 00,000 1 0,000

Energy (nJ)

Time ( µs)

1 0,000 1 ,000 1 00

“If you think about the complicated problems that require a lot of parallel operations and have to execute millions of times, then you can see a very significant benefit,” he added.

Neural networks mix it up with analog signal processing Beyond the realm of differential equations, analog-based arithmetic logic units (ALUs) are also gaining traction in the world of MSSP. “Each time we reduce the size of the multiplier in half – say from a 32-bit multiply to a 16-bit multiply – the performance increases roughly by an order of magnitude while the power dissipation is reduced for each multiply by the same ratio,” Frantz explained. “So going from a digital 32-bit multiplier to a 1-bit analog multiplier improves the performance by several orders of magnitude while reducing the power dissipation by the same several orders of magnitude.

“At the same time, the number of transistors necessary to do the multiply is reduced from tens of thousands to tens,” he said. www.embedded-computing.com

1

1 Apollo IC

FIGURE 2

1 00 10

10

“If you’re dealing with analog signals and can skip the step of converting from analog to digital and then back to analog, that is obviously the advantage,” said John Milios, CEO of Sendyne.

“There are special ADCs that basically don’t do any conversion or consume any power unless there is a change in the input signal, so you don’t have any significant power loss.

1 ,000

MSP430

Apollo IC

MSP430

Comparison of power consumption and latency when executing the Van der Pol equation on the Apollo analog computing IC and a Texas Instruments MSP430 MCU.

One application area that is starting to capitalize on analog signal processing is the nascent field of neural networking. Here, there are use cases like keyword recognition and certain types of image processing that can afford to trade the lower accuracy of analog for the power and performance improvements it provides.

“There is a growing recognition that machine learning workloads present a different type of workload than the applications that previous processors have been designed for,” said Jeremy Holleman, Ph.D., Chief Scientist at Syntiant. “It is computationally demanding, memory-centric, mostly deterministic, and can tolerate modest precision. All of those factors play to the strengths of analog computation.”

Syntiant is a Bosch-backed AI semiconductor startup out of Irvine, CA that focuses on processing deep learning algorithms in resource-constrained systems like wearables, earbuds, remote controls, and sensors.

“The whole idea is to stay in the analog domain from the sensor front end all the way until after the neural network processing,” Embedded Computing Design | Spring 2020

7

EMBEDDED PROCESSING

said Marcellino Gemelli, Director of Business Development at Bosch Sensortec. “Another way to see it is to imagine neural network processing before the signal conditioning that occurs in an ADC like a sigma-delta.”

The goal of the architecture Gemelli describes is simple: keep digital cores asleep at all costs. Aspinity, another AI startup based in Pittsburgh, PA, has developed a reconfigurable chip called RAMP that replicates digital signal processing tasks in analog for precisely this purpose (Figure 3).

“All sensed data is naturally analog, yet we take all of that data and we automatically digitize it, and process it downstream in a digital core,” said Tom Doyle, CEO of Aspinity. “But if you implement that in analog transistors, you can do it efficiently and accurately as well.

“What we’re able to do is be precise enough early in the signal chain to monitor very specific changes in frequency,” he continued. “So right after the sensor, you have Aspinity’s RAMP core that’s looking at all of the raw analog sensor data. When we detect something like voice or a glass break, we wake up the ADC and DSP to run an FFT to get all the gobs of data that one would need to determine what they want to do next.”

According to Doyle, applications like glass-break detection and voice activation have experienced power savings of 10x or more using RAMP technology.

TS-7553-V2

Industrial IoT Gateway NXP i.MX6UL 698MHz ARM Cortex-A7 CPU 4 GB MLC eMMC Flash

FIGURE 3

Aspinity’s Reconfigurable Analog Modular Processor (RAMP) resides between a sensor and digital system components to conserve considerable amounts of energy.

Are we back to the future? Not quite.

While the potential of analog as an alternative or complementary processing technology is clear, it suffers from an extended absence in the commercial market. For one, there is limited information on how analog circuitry responds to the effects of temperature and aging. Another consideration is simply the ubiquity of digital interfaces today.

“In order to take full advantage of the low power and small die size, the signals will need to be tapped at the analog level more upstream, which in turn requires the sensor vendors to introduce architecture changes,” Gemelli explained. “Currently it’s a hard sell because tapping in the analog domain requires a significant redesign of the sensors’ front ends.”

What could ultimately drive those redesigns is more widespread use of analog computing technology. Development tools that provide access to analog circuitry from digital environments would help in that regard, and progress is being made there now that analog hardware targets are becoming available (See Sidebar 1 on page 10).

Of course, I use “becoming available” in the most literal sense.

Sendyne’s chip is the product of academic research, and firstgeneration products from Aspinity, Syntiant, and others are just barely reaching the market.

However, our rapidly diminishing ability to advance speeds and densities in the digital domain is undeniable. And, at the same time, our demand for computing power is increasing exponentially.

What will it take to go back to the future with analog computing?

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Embedded Computing Design | Spring 2020

“It needs someone to invest in this high-risk opportunity and create the first solution,” Frantz said. “My estimate is that a new computer architecture costs in the range of $100 million up to $1 billion.

“The risk is great. The people who can do it are few. But the reward is great.” www.embedded-computing.com

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BY ENGINEERS, FOR ENGINEERS In the rapidly changing technology universe, embedded designers might be looking for an elusive component to eliminate noise, or they might want low-cost debugging tools to reduce the hours spent locating that last software bug. Embedded design is all about defining and controlling these details sufficiently to produce the desired result within budget and on schedule.

Embedded Computing Design (ECD) is the go-to, trusted property for information regarding embedded design and development.

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EMBEDDED PROCESSING

SIDEBAR

WHAT’S PROGRAMMABLE ANALOG WITHOUT PROGRAMMING TOOLS?

By Perry Cohen, Associate Editor Analog computing systems are exceptionally efficient when calculating differential equations associated with, for example, dynamical systems. However, mapping these equations to the analog circuitry embodies its own set of complications.

The biggest of these may be that a lack of programmable analog targets has prevented the emergence of analog computing tools that can automate or at least simplify the reconfiguration of analog ICs for new or different differential equations.

But that is beginning to change thanks to a collaboration between a Columbia University team led by Yannis Tsividis, the school’s Edwin Howard Armstrong Professor of Electrical Engineering, and Sara Achour, a PhD candidate at the Computer Science and Artificial Intelligence Laboratory at Massachusetts Institute of Technology (CSAIL MIT).

After Tsividis’ team completed its general-purpose analog computer, Achour developed Legno, a compiler that successfully targets the device through an on-chip USB interface. In fact, it is believed that the grad student’s Legno tool is the first compiler to successfully target programmable analog hardware. Period.

Legno accepts first-order differential equations written in Python, which allows users to define state variables, expressions, and which variables they would like to observe. The compiler uses these inputs to synthesize configurations for devices like the Sendyne Apollo chip and ensure that all physical restrictions of the target are honored (Figure 1).

“If I’m dropping a ball from 50 meters, if I can’t drive 50 microamps on a wire, I can’t run that simulation,” Achour said. “[The Legno] compiler automatically rescales the system. For example, say we’re going to scale it down by a factor of five, now you’ve mapped the position of the ball between zero and two microamps, which is something that device can represent.

“Maybe I define a velocity and a position [in the high-level language], and I want to observe the position,” she explained. “On output, the compiler will generate a set of configurations for each of the blocks on the analog device and it will also determine which wires to enable,” Achour continued (Figure 2). “It will make sure all of the operating ranges are respected on the device, account for manufacturing variations, respect any frequency limitations, and will try to scale up all of your signals so that you have a good signalto-noise ratio (SNR).

“All of these observable variables are accessible through pins that you can tap into on the chip, so [Legno] will make sure to route those connections outside of the device so that you can measure them,” Achour continued. “Basically, it does this automatic scaling problem. So, you can just give it your differential equations and boundary variables rescale everything.”

“It basically does the work of the electrical engineer for the highlevel ‘rich person’,” she added.

Legno is, of course, not the only tool available to embedded engineers that outputs differential equations, which turns out to be a very, very good thing for prospective analog computing developers.

Because so many other tools do output differential equations, it’s not difficult to imagine a pipeline in which these equations are just www.embedded-computing.com

AQM

ADS

Legno Compiler

Automated Scaling

Graph Synthesis Generate Trees

DSS

Assemble Graph

DQM

Place and Route

Generate USCP

Select Mode

Scaling Transform

ADP

Empirical Model Database

SIDEBAR FIGURE 1: The Legno compiler is thought to be the first analog compiler to successfully target physical analog computing devices.

MUL

P

-

V

MUL

set c=0.84 expr z=c*x

#2

INT

set c=0.22 expr z=c*x

#1

V

MUL

#2

#3

INT

MUL

#1

MUL

#1

-

INT

P

#1

V z0,z2=x z1=-x

z0,z2=x z1=-x

FAN #1

set x0=-2.0 expr z= integ(x,x0)

(a) generation

#2

FAN #2

COUT #1

Pos

(b) assembly

SIDEBAR FIGURE 2: The Legno compiler uses differential equations expressed in Python to appropriately configure analog circuitry. Shown here is a dynamical system specification (DSS) implemented for a dampened oscillator.

mapped directly to an analog computing target through a specialized compilation solution like Legno.

Fast-forwarding programmable analog Currently, Legno is open source and has been evaluated by members of the engineering community who have replicated Achour’s results. Obviously most of those users did not have access to programmable analog chips, so Archour provided 10 gigabytes of oscilloscope data that could be used for simulation.

While this first iteration of the Legno compiler is in the process of being finalized, the MIT student would like to continue refining the tool.

“It’s something I’m interested in developing in the near future because one of the things I do with this compiler is actually profile all of the analog blocks on the chip,” she said. “So, I have these math models that describe how each multiplier instance behaves.

“Something that would be interesting is creating random simulators so that people who do not have physical access to a programmable analog device can still play around with running their experiments on it.”

Achour and her team will present their work on Legno at the 2020 ASPLOS interdisciplinary systems research conference in Lausanne, Switzerland. To learn more about the Legno analog computing compiler, visit Sara’s academic profile page at http://people.csail.mit.edu/ sachour, read the research paper “Noise-Aware Dynamical System Compilation for Analog Devices with Legno,” or download the compiler from GitHub. Embedded Computing Design | Spring 2020

11

POWER ELECTRONICS

The Buffer/ Driver: What Is It, and Do I Need One?

By Bill Schweber, Contributing Author

L

The answers to that double question are simple: first, “it depends” and second, “almost certainly.”

et’s start with definitions: “buffer” has many definitions in electronics hardware and software. It can be a reserved software area; a set of internal IC registers; or it can be a circuit function interposed to interface between two sub-circuits.

We will look at the latter role. Although these buffers often handle digital signals consisting of idealized 1s and 0s, they are actually functioning in the real, analog world of voltage, current, time, and failures. As such, they are analog circuits handling realworld “digital” signals.

Buffer versus driver The difference between a buffer and a driver is largely a matter of perspective.

A buffer is usually an interposed element that keeps the signal source from being affected by the load attributes but delivers the same or nearly the same voltage and current it sees at its own input.

A driver, in contrast, often boosts the current source/sink level, or the voltage at which it delivers its output to its load, and often provide additional protection against circuit problems. However, the two functions often overlap and so does their naming in common use.

The buffer/driver symbol is simple, Figure 1, and does not begin to hint at their subtleties or internal complexities. In many ICs, the function is built into the source IC, but there are also many discrete buffer and driver ICs in use, depending how much current has to be delivered and at what voltage levels. (Note that buffers for analog signals usually use the same symbol as those for digital signals.)

12

Embedded Computing Design | Spring 2020

Functions A buffer or driver can serve many distinct functions, even though a basic buffer or driver has a single input which is connected to a source’s output, and a single output which is connected to (or drives) the load’s input. Among the many buffer or driver roles: ›› It can allow a sub-circuit with only low or modest current-source/sink capability to drive a load, which requires more current to operate. ›› It can provide protection for the source, in case the load has a fault, such as a short circuit or inadvertent connection to the power rail. ›› It can control and manage the timing between the source signal and the voltage/current as seen by the load (slew-rate control). ›› It can insulate the source from any changes in the nature of the load, so the source sees a fixed, unchanging load impedance. www.embedded-computing.com

›› It can simply invert the input signal to properly match the two sub-circuits. ›› It can provide impedance matching between components, a critical requirement in RF circuits for achieving maximum power transfer and minimum loss. ›› A MOSFET/IGBT driver takes the low-level digital signals from a processor or controller and delivers them with the high voltage and current that the MOSFET needs to be turned on, with the carefully managed slew rate and timing (Figure 2). ›› A programmable logic controller (PLC) state-machine processor needs to turn a relay on and off, and the relay needs 24V and 1 A to operate and also generates a high-voltage inductive “kick” when it is turned off. The driver not only translates between the two worlds, but also protects the processor output. ›› An IC with a 3V output needs to interface to an IC with a 5V input (or vice-versa), although the current levels are low. A buffer acts as the voltage translator. ›› An IC needs to drive multiple loads simultaneously, yet without involving an interaction between these loads; a single-input, multiple-output buffer (multiple fan-out) does this (Figure 3).

POWER ELECTRONICS

FIGURE 1

The symbol is used for a buffer/driver as it takes the signal at its input, enhances voltage and presents it as an output.

FIGURE 2 The MOSFET driver takes a low-level digital output and translates it to the voltage and current needed to turn the MOSFET on and off.

FIGURE 3 A fanout buffer takes a single input and provides multiple outputs; the load or status on each output does not affect the others.

Again, these are just a few of many possible examples.

Electrical isolation Sometimes, a buffer or driver provides more than just a basic electrical function.

There are situations were two sub-circuits must be electrically isolated from each other, meaning there is no ohmic (galvanic) path between the two, yet signal information must go from one to the other. This isolation may be needed for system protection, operator safety, or because the MOSFETs in a standard motor driver need to “float” without a ground connection.

An isolated buffer breaks the galvanic path by using an interposed path using an optocoupler (optoisolator), a transformer’s magnetic path, a capacitive coupling, or even an RF link. www.embedded-computing.com

Conclusion Despite the fact that buffers and drivers provide little or no added functionality or signal processing aspects, but primarily replicate their input at their output but with different attributes, they are essential components with key roles in a successful, viable design.

Deciding which specific device to select is sometimes a simple decision, but it can be a complicated one when there are subtle tradeoffs that must be addressed – for example, when driving a SiC MOSFET or RF front end.

The selection can “make or break” the reliable, successful performance of the circuit.

Bill Schweber is an electronics engineer who has written three textbooks on electronic communications systems, as well as hundreds of technical articles, opinion columns, and product features. He has an MSEE (Univ. of Mass) and BSEE (Columbia Univ.), is a Registered Professional Engineer, and holds an Advanced Class amateur radio license. Bill has also planned, written, and presented on-line courses on a variety of engineering topics, including MOSFET basics, ADC selection, and driving LEDs. www.linkedin.com/in/bill-schweber-155b836 Embedded Computing Design | Spring 2020

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INDUSTRY 4.0

Distributed Database Systems’ Relevance to the Internet of ThingS

By Steve Graves, McObject

A distributed database system is one in which the data belonging to a single logical database is distributed to two or more physical databases. Beyond that simple definition, there are a confusing number of possibilities for when, how, and why data is distributed. Some are applicable to edge and/or fog computing; some others are applicable to fog and/or cloud computing; and some are applicable across the entire spectrum of edge, fog, and cloud computing.

This paper will cover the types of distributed database systems in the context of edge, fog, and cloud computing, explain “when, how and why” the data is distributed, and why those details make certain distributed database systems applicable (or not) to specific needs in edge, fog and cloud computing.

W

ikipedia authors have taken a collective stab at defining a distributed database: “A distributed database is a database in which storage devices are not all attached to a common processor. It may be stored in multiple computers, located in the same physical location; or it may be dispersed over a network of interconnected computers. Unlike parallel systems, in which the processors are tightly coupled and constitute a single database system, a distributed database system consists of loosely coupled sites that share no physical components.”

That definition, itself, derives partly from the Institute for Telecommunications Sciences associated with the U.S. Department of Commerce. It is actually also actually pretty narrow. There are at least three other use cases that I get asked

14

about under the general heading of “distributed database”: High availability (HA), cluster database, and blockchain.

The Wikipedia definition, HA, and cluster all have applicability to the Internet of Things (IoT). Further, I contend that a distributed database’s shards can exist on the same physical computer. What makes a database distributed is that the various partitions are managed by separate instances of the database system, not the physical location of those partitions.

High availability For a database system to achieve HA, it needs to maintain, in real time, an identical copy of the physical database in a separate hardware instance. By maintain, I mean keep the copy consistent with the master.

In this scenario, there are (at least) two copies of the database that we call the master and the slave(s) (sometimes called replicas). Actions applied to the master database (i.e. insert, update, delete operations) must be replicated on the slave, and the slave must be ready to change its role to master at any time. This is called fail-over.

The master and replica are normally deployed on different physical systems, though in telecommunications a common HA set up is multiple boards within a chassis: a master controller board, a standby controller board, and some number of line cards that each serve some protocol (BGP, OSPF, etc.).

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in a two-phase commit protocol to assure that once they are committed, the changes are immediately reflected in every physical instance of the database. In other words, all the database instances are consistent, all the time. This architecture eliminates the potential for conflicts (or, rather, conflicts are resolved before a transaction can be successfully committed to the cluster).

With eventual consistency, changes are replicated asynchronously, possibly long after the originating node committed the change to the database. This implies some sort of reconciliation process to resolve conflicting changes originated by two or more nodes.

With eventual consistency, applications must be written to contend with the possibility of having stale data in the physical instance of the database to which they’re attached.

For example, consider a worldwide online bookseller. There may be one copy of a certain book in stock; buyers in New York and Sydney will both see that the book is available, and both can put the book in their shopping cart and check out. The system will have to sort out who really gets the book and whose order is backordered. Users have come to accept this.

Here, the master database is maintained by processes on the master controller board. The database system replicates changes to a slave database on the standby controller board, which has identical processes waiting to take over processing in the event that the master controller board fails (or is simply removed in a hot-swappable setup).

In the IoT, HA is desirable for missioncritical industrial systems, to maintain availability of gateways, and in the cloud to ensure that real-time analytics can continue to execute even in the face of hardware failures.

But, this model would never work for a cellular telephone network needing to verify that a subscriber has subscribed to a certain service, or has sufficient funds. This type of system requires a consistent database view.

Because of the nature of the synchronous replication required for the ACID implementation, horizontal scalability is limited, but the implementation is straightforward (no conflict resolution needed). Scalability of eventual consistency implementations is quite high, but so is the complexity.

Cluster implementations abound in the IoT. For example, IoT gateways can be clustered for improved scalability and reliability (Figure 1). The number of nodes in each gateway cluster is modest, so both the immediate and eventual consistency model are suitable. The cluster can handle more traffic from edge devices than a single gateway would be able to, and reliability/availability is improved (the inherent limits to scalability with the immediate consistency model don’t come in to play in small clusters).

Cluster database A cluster database is one in which there are multiple physical copies of the entire database that are kept synchronized. The difference with HA is that any physical instance of the database can be modified, and will replicate its modifications to the other database instances within the cluster. This is also known as a mastermaster configuration, in contrast to HA’s master-slave configuration.

This is where the similarities among database cluster implementations end.

Broadly speaking, there are two implementation models: ACID and eventual consistency. In ACID implementations, modifications are replicated synchronously www.embedded-computing.com

FIGURE 1

Clustering gateways can improve the scalability and reliability of an IoT deployment.

Embedded Computing Design | Spring 2020

15

INDUSTRY 4.0

Blockchain The term “distributed database” is often associated with Blockchain technologies (Bitcoin being the most well-known). It is used synonymously with “distributed ledger,” which is more apt (in this author’s opinion). My problem with using the term distributed database in the context of Blockchain technologies is that “distributed database” implies a distributed database management system. But there is rarely a database management system involved in Blockchain.

Not to belabor the point, but it is important to draw a distinction between a database and a database management system. A database is simply a collection of data, which might or might not be distributed. A database management system is the software that manages a database.

A Blockchain is, in fact, a distributed database. But, as previously mentioned, there is rarely a database management system involved in creating/maintaining the Blockchain distributed ledger.

Partitioned database The distributed (partitioned) database topology implied by the Wikipedia definition “... stored in multiple computers, located in the same physical location ...” is what is colloquially called “sharding” a database.

The key difference between sharding versus HA and cluster distributed databases is that each physical database instance (shard) houses just a fraction of all the data. All the shards together represent a single logical database, which is manifested in many physical shards.

I part company with the Wikipedia definition in that shards need not be stored in multiple computers to gain the benefits of sharding. Logically, the purpose is the same: scalability. Whether the shards are distributed across servers, or partitioned on a single server to leverage multiple CPUs or CPU cores is immaterial. In all cases, processing is parallel. How the shards are physically distributed is an unimportant artifact.

For example, in STAC-M3 published benchmarks we’ve conducted since 2012, we’ve utilized single servers with 24 cores, creating 72 shards, and we’ve utilized four to six servers each with 16 to 22 cores, creating 64 to 128 shards. In all cases, the goal is to saturate the I/O channels to get data into the CPU cores for processing. While STAC-M3 is a capital markets (tick database) benchmark, the principles apply equally to the IoT big data analytics. IoT data is overwhelmingly time-series data (e.g. sensor measurements), just like a tick database is time-series data.

Sharding a database implies support for distributed query processing. Each shard is managed by its own instance of a database server. Since each shard/server represents some fraction of the whole logical database, the potential exists that a query result returned by any shard is just a partial result set and needs to be merged with the partial result sets of every other shard/server and only then be presented to the client application as a complete result set. If the data is distributed among the shards in the most optimal way, then all of the data for a given query can be found on a single shard, and the query can be distributed to the specific server instance that manages that shard.

Often, both approaches must be supported. For example, consider a large smartbuilding IoT deployment that spans multiple campuses, each with multiple buildings.

We might choose to distribute (shard) information about each campus across multiple physical databases. If we want to calculate some metric for a specific building (e.g. power consumption in 15-minute windows), we only need to query the shard that contains the data for that building. But, if we want to calculate the same metric for multiple buildings and/or across campuses, then we need to distribute that query to many shards/servers, and this is where the parallelism comes in to play. Each server instance

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Embedded Computing Design | Spring 2020

works on its portion of the problem in parallel with every other server instance.

Database sharding also supports vertical scalability (i.e. being able to store tens or hundreds of terabytes, petabytes, and beyond). To create a single 100 TB logical database, I can create 50 instances of 2 TB physical databases.

Distributed database systems often support “elastic” scalability, allowing me to add shards, which could also mean adding servers to the distributed system so that the system is scalable in both the vertical and horizontal dimensions.

Vertical and horizontal scalability is essential for large IoT systems that generate very high volumes of data. You need vertical scalability to handle the ever-growing volume of data, and you need horizontal scalability to maintain the ability for timely processing/analytics of the data as it grows from 1 TB to 10 TB to 100 TB to petabytes and beyond.

IoT replication While, strictly speaking, not a distributed database implementation, we would be remiss if we didn’t talk about data distribution within an IoT system.

The IoT ecosystem usually consists of the “edge,” “gateway,” and “cloud,” and databases exist in all locations. IoT data is initially generated at the edge and needs to be distributed from there to gateways, and from gateways to the cloud. Data at the edge is often used to control some “thing” in real-time (e.g. to open or close a solenoid in an industrial IoT system).

At the enterprise level, in many (if not most) cases, one of the objectives of an IoT system is to capture and extract value from the data. Usually, that means some sort of “monetization” of the data.

That can come in the form of increased efficiency or reduction in maintenance costs or downtime in an industrial setting, or more intelligent interaction with customers leading to greater efficiency extracting dollars from their wallets.

Data distribution with an IoT system means moving the data from the edge through a gateway or gateways to a private or public cloud. This movement of data is fraught with its own issues: www.embedded-computing.com

›› Connectivity – Edge devices can be offline, either by design or because of faults in the communication infrastructure.

For example, battery-powered edge devices will be offline by design, and only connect to a gateway on a schedule. Or, they can be mobile devices that move in and out of range of gateways or cell towers. Or, the communication link can simply be broken.

In any case, the device must have the intelligence to queue data for later transport. ›› Security – Security is the top consideration for IoT systems in this decade, and likely into well into the next. Data in flight needs to be protected. This could be as simple as utilizing SSL/TLS. ›› Bandwidth – The communication channels available at edge devices can have extremely limited bandwidth. For example, Bluetooth Low Energy (BLE) is 1 or 2 Mbps. Zigbee ranges 20 to 250 kbps. This compares to the slowest Ethernet at 10 Mbps.

To maximize the available bandwidth, data should be compressed before it is put into the communication channel. ›› Scope – Some questions that IoT system designers need to consider: Will all data be pushed from the edge to the cloud? Or is some data only useful at the edge? Will data be aggregated before it is transmitted, or is only raw granular data transmitted?

Sharding partitions a logical database into multiple shards to facilitate parallel processing and horizontal scalability.

All of these capabilities are integral to the deployment of scalable and reliable IoT systems. These distributed database mechanisms are often used in combination.

Refer again to Figure 1, where we see clusters of gateways with each node in a cluster aggregating data from some number of devices. If a cluster node fails, the devices it was serving can connect

to another gateway in the cluster and maintain operations. At the server level, a sharded database is depicted, with each shard receiving data from one of the gateway clusters.

Collectively, the shards represent a single logical database. Each shard consists of a master/replica HA pair. This is desirable because without HA, if any shard failed, the logical database integrity is compromised.

Steve Graves is president, CEO, and co-founder of McObject.

In eXtremeDB, we’ve anticipated and addressed these concerns in the Active Replication Fabric.

In summary, the term “distributed database” encompasses three different database system arrangements for three distinct purposes: HA database systems distribute a master database to one or more replicas for the express purpose of preserving the availability of the system in the face of failure; Cluster database systems distribute a database for massive/ global scalability (eventual consistency) or for cooperative computing among a relatively small number of nodes (ACID); www.embedded-computing.com

Embedded Computing Design | Spring 2020

17

WIRELESS IOT STANDARDS

5G Primer: RAN & Core Network Architectures

By Curt Schwaderer, Technology Editor

All major mobile operators are actively promoting their 5G advancements – If you believe the commercials, 5G is being rolled out and turned up, enabling higher bandwidth applications and machineto-machine interactions.

W

hile it’s true that 5G rollout does appear to be underway, it’s not an “all or nothing” proposition. Like most innovations, rollout is a phased process.

The advanced 5G features and capabilities for IoT, intelligent edge, and AI/IVR are very real and attention should be paid to 5G network architecture in order to take advantage.

RAN importance in 5G The key driver of 5G is the Internet of Things (IoT). And of course, existing smart phone services and applications will get faster and more feature rich moving to 5G. Mobile industry and standards organizations have categorized these services as follows: ›› Enhanced Mobile Broadband (eMBB) – Current services being offered for LTE, but faster, higher resolution, and more feature-rich. Examples include high resolution or 3D video and augmented reality applications. 5G is specified to go to 10Gbps for broadband access. ›› Ultra-reliable and Low Latency Communications (uRLLC) – Services that require high reliability and some precision in real time processing and response on the order of a millisecond. Examples here include autonomous driving, smart city, smart grid, and industrial IoT applications. ›› Massive Machine Type Communications (mMTC) – Services with a very large number of sensors sending information through IoT gateways to cloud applications and AI. Examples involve retail, smart city, agricultural IoT

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Embedded Computing Design | Spring 2020

applications where many thousands of sensors (mMTC encompasses up to 1 million devices per square kilometer!) may be providing information to cloud AI and machine learning applications to optimize city and retail planning, power optimization, or application of weed killers or insecticides.

All this means is that the RAN must be faster, higher capacity, and smarter. 5G is a comprehensive digital transformation of the network infrastructure. However, incremental steps involving the rollout of 5G RAN is being largely adopted as the first step toward 5G. This incremental step is often referred to as “Non-Stand Alone” or 5G NSA. 5G NSA means that the antennas and base stations being deployed will provide 5G frequency ranges, but the RAN www.embedded-computing.com

WIRELESS IOT STANDARDS

FIGURE 1

A generalized diagram of a 5G NSA Radio Access Network.

straight-forward, easily programmable device or sensor, which is easily configurable to the spectrum allocations of the country or region it’s operating within.

Step 1: 5G NSA A generalized diagram of 5G NSA is shown in Figure 1. In this diagram, the LTE node serves as the Master (MeNB) and the 5G node serves as the secondary (En-gNB).

will work with the existing 4G LTE core network. This allows for the RAN to be upgraded without requiring much to change within the LTE core.

5G New Radio (NR) In “5G Primer Part 1: Basic Architecture” I covered the three radio bands being introduced to support 5G services and applications. In general, the lowband and mid-band frequency ranges described in that article overlap with and extend 4G LTE frequency ranges for compatibility. This will provide increased bandwidth required to support eMBB applications. This frequency band is sometimes referred to as 5G “New Radio” or 5G NR. The second range operates between 24 GHz and 52 GHz. This range is called “millimeter wave” or mmWave.

The mmWave spectrum will support uRLLC and mMTC applications. This is not without its challenges, however.

Available frequency ranges are expected to be different between countries, which makes device manufacturing difficult. Smartphone and IoT device manufacturers could struggle, making a www.embedded-computing.com

The master LTE and secondary 5G node both have direct interface with the Evolved Packet Core (S-GW/P-GW). However, only the master LTE node has a control plane connection to the MME. Using the 5G NSA architecture, a 5G-enabled device can leverage the bandwidth of the 5G RAN for user plane traffic, but the control plane (bearer channel setup/ teardown) remains the responsibility of the LTE master node. There may also be cases where user plane traffic passes from the 5G RAN node to the LTE master node for fallback scenarios.

Over time, as the next-generation core is deployed, the MeNB and EPC components will be removed, which will result in the 5G Stand Alone (5G SA) architecture.

The role of Cloud RAN (C-RAN) In order to support things like uRLLC, you need real-time intelligence close to the edge. This means that micro data centers will be integrated with the RAN to provide these features. In fact, as in the discussion of network slicing in “5G Primer Part 1: Basic Architecture”, RAN intelligence also has a concept of slices. RAN real-time functions include network scheduling, link adaptation, power control, interference coordination, retransmission, modulation, and coding. This means RAN sites will include dedicated hardware with high performance and low latency in order to effectively execute services requiring close proximity.

The RAN non-real-time functions include cell selection and hand-off, encryption, and multi-connection convergence. These non-real-time functions can be performed at a centralized location with standard processors and servers. The result is an architecture where there are micro data centers deployed within the RAN that contain specialized hardware to perform latency- and real-time-sensitive tasks. These micro data centers cascade into “central office” data centers at aggregation locations that perform a number of the non-real-time tasks for the environment. These, in turn, cascade into a regional data center where AI and Big Data analysis processing is deployed.

Embedded Computing Design | Spring 2020

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WIRELESS IOT STANDARDS

The result is a distributed data center architecture that spans RAN, Core, and Internet.

5G RAN in summary The 5G RAN architecture and evolution is key to meeting a number of service requirements around low latency, higher bandwidth, and higher capacity. But this isn’t just about deploying newer antennas. The splitting of spectrums for enhancing existing services and introducing new ones presents challenge and opportunity to mobile operators and device manufacturers alike. The micro-data centers that accompany RAN locations will be critical to supporting uRLLC applications. New business and cost models need to be addressed – micro-data centers mean servers and power so space and power costs associated with these new sites will be critical to the ability to cost-effectively support these new services.

5G RAN will be largely deployed in three phases. The first phase involving 5G NonStand Alone mode will use the existing 4G LTE core and antennas where the LTE base station will continue to manage the control plane while the 5G secondary nodes will provide the increased bandwidth and capacity for enhanced services. The second phase involves adding micro data centers for increased intelligence and low latency processing. The third phase involves completing the digital transformation by deploying the 5G core and removing the LTE RAN and core components.

The transformation at the RAN has already started and its evolution from a technical and business model perspective will be critical to the success of IoT in the future.

5G Core Network foundations As with all new technologies, there are a large number of new mnemonics that are introduced in the 5G core network architecture

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5G foundational technologies involve network functions virtualization (NFV) and software-defined networking (SDN). NFV virtualizes network functions to provide dramatic increases in the ability to scale a network depending on traffic load and service types. SDN provides the mechanism by which traffic partitioning, quality of service, and network management can be effectively and efficiently performed.

5G is defined by the 3GPP Working Group using a service-based architecture. Each network function (NF) is defined by what services the NF provides. A reference point representation is also defined that shows the interaction between any two network functions. The architecture is governed by the ETSI Technical Specification 23.501 “System Architecture for the 5G System.”

5G Core Network architecture Figure 2 shows the 5G non-roaming service-­ b ased system architecture.

Figure 3 shows how the network functions interact with each other. The user equipment (UE) block is the 5G device using the network.

The Network Slice Selection Function (NSSF) selects the Network Slice Instance (NSI) based on information provided during UE attach. A set of Access and Mobility Management Functions (AMFs) are provided to the UE based on which slices the UE has access to.

The Network Exposure Function (NEF) exposes the overall 5G core network services and capabilities.

The Network Repository Function (NRF) maintains the network function profile and performs service discovery within a slice.

The three primary network functions of the core network (CN) are the AMF, Session Management Function (SMF), and User Plane Function (UPF). These functions handle the mobility management, application session management, and application content flows through the core network.

Creating slices in 5G A network slice is defined as an end-toend logical communications network within a mobile network and includes

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the core network, control plane, user plane functions, and 5G access network.

Mobile operators intend to use these network slices to house isolated service applications for tenants much like cloud providers sell their compute, storage, and memory resources.

The idea is a customer will provide their bandwidth, capacity, and latency requirements for the application they want to run on a network slice. The mobile operator does a requirements analysis based on current network status and load, creates a service-level agreement (SLA), and allocates the necessary capacity and bandwidth for the slice.

Once the slice is created, the tenant runs their application using the network slice and they can be assured the network slice will adhere to the SLA. 5G Core operation Network operation starts with the UE connection management with the network. An AMF is selected by the access network to receive the UE registration request. The UE request message includes Network Slice Selection Assist­ ance Information (NSSAI), which helps the core network determine the serving AMF or if a default AMF should be used.

The AMF serving the request may query the Unified Data Management (UDM) to get the UE subscription information that includes the network slices available to them. If the UE context in the AMF does not have slice access information corresponding to the type of access being requested, the AMF queries the NSSF to get access to slices information for the UE. Once the UE connection has been completed, the same AMF may be used or the UE may be handed off to a different AMF. Once connected, the UE uses the N1 interface to perform application sessions establishment with the SMF within the accessible slices. The 5G architecture completely separates the control plane function from the user plane function.

The SMF uses N4 to perform user plane session establishment. When the session establishment is completed in the control plane, the AMF uses the N2 interface to prompt the RAN to perform the access network resource setup with the UE. Once the access network resources www.embedded-computing.com

FIGURE 2

A simplified 5G system architecture.

FIGURE 3

A representation of 5G reference points.

are established, the RAN sends the session an establish response back to the AMF over N2. This causes the AMF to send the SMF a PDU session update message, which causes a session update exchange between the SMF and UPF. Add to this the complications of mobility. As a UE travels, a hand-over from one antenna to another may occur. In order to support the ability to make sure the new RAN location has the slice information, the NSSAI is part of the mobility signaling as well. This gives the new RAN node the ability to seamlessly support the active slices in which the UE is communicating.

For example, let’s say our UE is active and has two active slices with sessions running on each. The current RAN node handover preparation starts. This RAN node sends a “handover required” message to the AMF. The AMF sends a handover request to the new RAN node with the PDU session information and the information for the network slices. The new RAN node then responds with a list of accepted and failed PDU sessions. Once received, the AMF sends the handover command to the old RAN node, which makes the transition.

Note that the handover doesn’t guarantee that all the active sessions will be maintained – that is a function of the capabilities and access of the new RAN node.

Final thoughts The evolution to 5G is arguably the biggest undertaking mobile operators have ever attempted. As you are now aware, all the services and messaging interfaces need to be slice-aware and new functions within the core network architecture are needed to manage and secure network slices. It won’t come overnight, but when the 5G core networks begin to roll out, it will be a huge catalyst for the digital transformation and our new IoT-everywhere world.

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Rugged and secure because failure is not an option

By Jim Shaw, executive vice president of Engineering, Crystal Group

As the convergence of IoT technologies and artificial intelligence (AI) accelerates, so does the need for heightened performance, safety and security. This is enabled primarily by the transition to a 5G ecosystem. With its lightning-fast speed and data transfer capacity, the opportunities to quench our extensive cravings for faster, more accessible connectivity and situational awareness will be fed through new IoT opportunities. But with all opportunities come risks.

The increased power of 5G will generate greater congestion as more devices are added into the mix. This includes more of those that already exist, as well as new devices crossing into the world of wireless functionality. Given that many of these devices will live at the edge, the designs will require rugged hardware to protect and sustain consistent operations under any conditions.

Similarly, with each new connected device is a new security risk; a fresh point of entry for bad actors to slip into the data expanse and attempt to breach or capture private, sensitive data.

Everyone from autonomous developers to critical infrastructure companies to the military are exponentially driving demand for computing solutions like Crystal Group’s portfolio of rugged, scalable and secure computer hardware to achieve these unprecedented levels of data processing power, transmission, storage capacities and cybersecurity.

With proven reliability and fail-safe performance in the most extreme, unpredictable manned and unmanned environments, Crystal Group integrates these critical competencies into smart solutions where traditional computers fail. That’s why engineers and developers depend on Crystal Group computer and electronics solutions to bring reliable IoT and AI processing to the edge, where safety, accuracy and efficiency are paramount.

Power Equipped with the latest Intel® Xeon® scalable processors to fuse massive amounts of data in real time, Crystal Group embedded systems enable near-zero latency at the edge. In addition to providing critical communications data transmission, this supports efficient intelligent data storage and deep learning applications. AI data is prioritized to maximize accuracy in applications like facial recognition, video analytics and geospatial modeling. www.embedded-computing.com

Crystal Group www.crystalrugged.com An important, but often overlooked, side effect of extreme processing power is the amount of heat it generates. Using innovative liquid, fan and fanless sealed chassis cooling techniques, Crystal Group specializes in optimizing thermal performance to extend reliability and operational life.

Performance Engineered for seamless performance in the most extreme, unpredictable and remote conditions, Crystal Group rugged and industrial computer hardware are built and tested to meet or exceed demanding environmental requirements and military specifications. Combining their rugged chassis design with proprietary ruggedization processes, both equipment and data are protected against EMI, dust, sand, salt, fog, shock, vibration and extreme thermal conditions. Furthermore, these smart solutions are designed and built to ISO 9001:2015 quality management standards so products meet or exceed strict military, IEEE and IEC industrial standards.

Security While security factors become increasingly complex, the solutions to prevent unauthorized access need to include effective, yet simple encryption measures. Crystal Group works closely with trusted partners to design in vital end-to-end security measures from the start. This enables them to meticulously integrate leading-edge, platform-agnostic data protection with critical hardware. With a foundation of essential features, like Trusted Performance Modules (TPM 2.0), conformal-coated SAS solid state drives, NIAP-certified IPsec encryption, intrusion detection, tamper evidence and instant data destruction, confidential data is secure from attempted breaches.

In the highly competitive arena of maximizing the reach and benefits of our connected lives and battlefields with the right combination of performance, reliability and security, engineers and system integrators turn to Crystal Group to push boundaries and execute flawlessly – because failure is not an option.

Embedded Computing Design | Spring 2020

25

ADVERTORIAL

EXECUTIVE SPEAKOUT

Migrating to the Intelligent Edge The Intelligent Edge is gaining momentum in the embedded development community and beyond. To get a better understanding of what that means, Embedded Computing Design spent some time with Wind River’s Gareth Noyes, the company’s Chief Strategy Officer.

ECD: The Intelligent Edge is something that’s getting a lot of attention these days. Explain what that term means.

NOYES: The simple answer is that an Intelligent Edge is a place that spans from the device edge to the infrastructure edge where data is both collected and analyzed. This means that data is processed, analyzed and acted on before it is sent to the cloud. The result of the Intelligent Edge is that costs are lower, network impact and latencies are minimized, and security risks are reduced.

ECD: Why would traditional enterprise-based vendors want to create an Intelligent Edge?

NOYES: Companies that rely on highly centralized cloud and hybrid-cloud infrastructures realize the importance of the edge and the value it offers. Growing quantities of raw data now originate from IoT devices and sensors, and new classes of devices – from autonomous vehicles to industrial robots – require real-time access to operational data. In other words, data is being both generated and consumed at the edge, far from the centralized computing power of cloud-scale infrastructure. For all that data to make round trips to the cloud would devour too much bandwidth and take too much time for the operational needs of the edge devices.

ECD: Today, embedded systems and cloud computing represent two different worlds. How do we make them intersect?

NOYES: The border between things (the edge) and the cloud is not easy to cross. Software development in the two worlds requires different skillsets, and largely uses different tools, languages, and methods. And, cloud solutions don’t transport easily to the edge. Companies run into unfamiliar and incompatible environments when they try to move processing closer to the data at the edge. The reasons for this are that edge computing resources are more limited, physical access and security present new challenges, and virtualization is not the norm.

ECD: What challenges can a developer expect to confront when migrating intelligence to the edge?

NOYES: Edge computing devices that interact with real-time embedded systems can have specific requirements that are unfamiliar to cloud computing. Determinism is a good example.

The deterministic model at the root of embedded systems is the expectation that a device will always complete the same task in the same way and in the same amount of time. Anything less than 100% determinism can result in catastrophic failure.

This is foreign territory to the data center, which is all about parallel processes that typically complete their tasks within the target timeframe. In the data center, you expect and accept a certain amount of jitter, a long tail of latency with outliers that

miss the target. Deterministic embedded devices at the edge don’t have this tolerance.

ECD: What other differences are there between what’s traditionally found at the edge versus the cloud?

NOYES: Embedded systems have historically been about fixedfunction, monolithic, cost-sensitive, compute-limited physical devices with long development cycles and long lifecycles.

Embedded device builders struggle with how to accelerate development, scale production, and reimagine edge devices more broadly to be relevant and valuable to the world of cloudscale infrastructure.

The pressure for device original equipment manufacturers (OEMs) to change comes both from “above” and “below.”

Below are the hardware platforms that devices are built on. The availability and affordability of powerful new processing and storage options challenges device makers to take advantage of these capabilities. The pressure from above comes from customers who want flexible, multipurpose, interchangeable edge devices that are compatible with their cloud-like infrastructures.

ECD: Wind River refers to a concept called the landing zone.

Can you describe how that works?

NOYES: Sure. We look at the landing zone concept as enabling the development of applications that can be deployed anywhere in the intelligent edge, irrespective of whether it’s a physical (embedded) edge device or part of the virtualized cloud-scale infrastructure. Wind River understands embedded systems that make up the intelligent edge, we have experience deploying robust cloud-scale edge infrastructure, and we know how they can become more compatible with cloud-native applications. To create a landing zone architecture, OEMs will need to build new kinds of edge devices, consisting of a few critical, yet standard, building blocks enabling them to leverage the same modern application development processes to deploy new services at the edge.

ECD: With all that said, why should a developer choose Wind River over competitive offerings?

NOYES: Wind River has the robust and comprehensive embedded software portfolio to deliver this vision. We can help bring embedded OEMs and cloud-native industries together to architect a new intelligent edge infrastructure. This would be accomplished through a variety of software and tools already in the Wind River portfolio, including the VxWorks RTOS, Wind River Linux, the Helix Virtualization Platform that allows VxWorks and Linux to run concurrently with or without containers, Wind River Cloud Platform, Wind River’s family of products for cloud-scale infrastructure, and Simics for system simulation.

ADVERTORIAL

EXECUTIVE SPEAKOUT

Tyan Tempest EX Motherboards Scale IoT Analytics from the Data Center to the Network Edge

By Charles Chen, TYAN Computer Corporation Director, Tyan Product Planning and Marketing Division Data analysis tasks are moving towards the edge of networks to provide shorter response time and better IoT user experience. To support such fast-growing needs, Tyan Computer’s Tempest EX motherboards are the ideal choice to build up edge systems that bridge compute, storage, and networking resources with compact form factors, a wide range of operating temperatures, and long product supply lifetime. Based on Intel® Atom®, Core™, and Xeon® processor technologies, the Tyan’s portfolio of Tempest EX motherboards provides various options of on-premises servers, local gateways, and edge devices for IoT implementation.

Tyan’s Tempest EX S5550-EX is a single-socket server motherboard that is targeted at on-premises server appliance development and supports the Intel® Xeon® E-2200 series processor with up to 8 multi-threaded cores and 95 watt power consumption to provide outstanding performance in a 9.6" x 9.6" microATX form factor. The motherboard is also equipped with four 1000Base-T LAN ports, three standard PCIe slots, eight SATA 6G ports, as well as audio and display port interfaces.

The Tempest EX S5550-EX server motherboard supports up to 128GB unbuffered ECC DDR4 2666/2400 memory for intensive data analytics operations. The platform provides a sevenyear supply lifecycle and wide operating temperature range of 0-55 ºC which are highly required for most embedded IoT applications.

The Tempest EX S5555-EX single-socket embedded workstation motherboard, based on 9th generation Intel® Core™ i3, i5, or i7 processor technology, is designed for embedded appliances. The Tempest EX S5555-EX benefits from the energy efficiency enabled by Intel Core™ processors with integration of multiple video outputs (two display ports and one DVI-D port), 7.1 channel high definition audio, and onboard storage options (two SATA DOM and NVMe M.2) in a Micro-ATX form factor, the server motherboard is an ideal platform for embedded workstation applications.

In addition to the seven-year supply lifecycle and wide operating temperature range of 0-55 ºC, Tyan’s Tempest S5555-EX motherboard has also been certified with EMC Class B which allows embedded systems based on the motherboard to be deployed in office environments.

Intel’s Xeon processors integrate a suite of technologies that optimize data analytics in mixed-criticality environments like the Industrial IoT edge. Intel® Virtualization Technology (Intel® VT-x), Intel® VT-x with Extended Page Tables (EPT), and Intel® Virtualization Technology for Directed I/O (Intel® VT-d). These features help partition data analytics workloads from other missioncritical functions, while also ensuring the security, reliability and performance of memory and peripherals.

Tyan’s scalable Tempest product line demonstrates how standards-based platforms powered by robust processors efficiently meet the demands of enterprise analytics compute at the IoT edge. These products also highlight how x86-based embedded systems provide the flexibility to run high-performance analytics and conventional software elements on a single processor.

Leveraging embedded platforms, the Tyan Tempest line also allows developers to efficiently reuse hardware and software components from edge to cloud, thus reducing costs and minimizing time to market. For more information, visit Tyan’s website at www.tyan.com.

Dev Kit Weekly: 2020 Kit Roundup Ayla Networks

Ayla Development Kit v2.0

Based on a production-ready Wi-Fi module from Murata that leverages a Cypress chipset, the kit comes pre-loaded with a no-codingrequired network stack. TLS-encrypted connections to the Ayla IoT Cloud provide access to Ayla APIs that handle Wi-Fi provisioning and mobile app integration.

Available from Ayla Networks for FREE

BeagleBoard.org

BeagleBone AI

Dual TI C66x floating-point DSPs, four Embedded Vision Engines, a dual-core PowerVR 3D GPU, a Vivante 2D graphics accelerator, dual Arm Cortex-A15 cores, and two programmable real-time units headline the Texas Instruments' Sitara AM5729 tucked beneath a heatsink on this powerful maker-friendly AI platform.

Available from Mouser Electronics, Inc. for $125

Bitcraze.io

Crazyflie 2.0 Drone Development Kit

The Crazyflie 2.0 incorporates a 10 degree-of-freedom accelerometer/magnetometer/gyroscope, pressure sensor, Bluetooth Low Energy SoC, and companion mobile app. The kit comes with a ­battery, motor, and propellers so you can take to the skies in no time.

Available from Bitcraze Store for $195 (Crazyflie 2.1)

Electric Imp

impC001 Cellular Breakout Board Kit

The certified C001 module supports LTE Category 1 and 3G HSPA operation over AT&T, T-Mobile, and Verizon networks, as well as concurrent cellular, 10/100 Ethernet, and Wi-Fi connections. The board is also outfitted with a Mikrobus socket and two Grove connectors.

Available from Electric Imp for $129

Helix Semiconductors

MxC 274 PoE to USB DC-to-DC Power Conversion Kit

48V to 24V inputs pass into an isolation barrier formed by the Helix 2I_048_010A and 2D_024_010A DC-DC converters, which sample the current down to 6V. Then, through the magic of buck regulators, that is refined down to a 5V output.

Available from Digi-Key Electronics for $93.75

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www.embedded-computing.com

Dev Kit Weekly: 2020 Kit Roundup Infineon Technologies AG

iMOTION Modular Application Design Kit (MADK)

The MADK is a three-phase motor drive evaluation platform that includes a controller and the ability to interface with intelligent power modules over an M1/M3 interface. Compatible power modules enable prototyping over a 20W to 1.5kW range, which you can accomplish inside an hour.

Available from Digi-Key Electronics for $67.56

Maxim Integrated

MAX86150EVSYS Mobile Health Monitoring Kit

You actually get two boards with the MAX86150EVSYS mobile health monitoring evaluation platform: The MAX86150 electrocardiogram and photoplethysmogram bio-sensor module and the MAX32630FTHR microcontroller board. The MAX86150 optical sensor boasts an ultra-low shutdown current of 0.7 ÂľA.

Available from Digi-Key Electronics for $131.25

Microchip Technology Inc.

MPLAB Snap In-Circuit Debugger/Programmer

The Snap is designed for fast debug and programming of PIC, dsPIC, AVR, SAM, and other flash-based MCUs using the MPLAB X IDE. Despite its low cost, it delivers essentially the same speed, debug performance, and complex breakpoint functionality of higher end solutions.

Available from Microchip Direct for $14.95

Microchip Technology Inc.

PIC-IoT WG Development Board

You can connect straight to the cloud on this 16-bit MCU-based kit thanks to the ATWINC1510 network controller, an 802.11b/g/n Wi-Fi device with 8 MB of Flash. Microchip even included an ATECC608A CryptoAuthentication IC to secure your communications channel.

Available from Microchip Direct for $29

NVIDIA

NVIDIA Jetson Nano

The Jetson Nano is an 80 mm x 100 mm developer kit based on a Tegra SoC. This gives the Nano a reported 472 GFLOPS of compute horsepower, which can be harnessed within configurable power modes of 5W or 10W.

Available from Arrow Electronics for $89 www.embedded-computing.com

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Dev Kit Weekly: 2020 Kit Roundup ON Semiconductor

RSL10 Sensor Development Kit

The RSL10 Sensor Development Kit from ON Semiconductor boasts the industry’s lowest-power BLE/Bluetooth 5 SoC, comes pre-certified to FCC, CE, IC, KC, and MIC wireless regulations, and supports a host of sensors to help you get prototyping in no time.

Available from Arrow Electronics for $49.43

PowerFilm Solar Inc.

Indoor Solar Development Kit

The Indoor Solar Development Kit features two indoor-rated solar panels that operate in low-light environments down to 200 lux. This can be turned into several hundred microwatts of harvested energy and extracted via an energy harvesting IC with boost charging technology.

Available from PowerFilm Solar for $99.99

Qualcomm Technologies Inc.

Qualcomm QCA4020 Product Development Kit

The QC4020 Kit is unique in that it provides simultaneous “tri-mode” Bluetooth, Wi-Fi, and 802.15.14 connectivity. In addition to multiple radios and discrete processors and memory for each connectivity type, the QCA4020 host offers a sensor hub, security accelerators, and Arm Cortex-M4F core.

Available from Digi-Key Electronics for $75

Renesas Electronics Corporation

EK-RA6M3G Graphics Evaluation Kit

The Renesas EK-RA6M3G is headlined by the company’s RA microcontroller family. This new series of 32-bit Arm Cortex-M4-based devices integrate Secure Crypto Engine IP and are all certified to level 1 of Arm’s Platform Security Architecture. They also support tons of connectivity options.

Available from Avnet, Inc. for $152.94

Renesas Electronics Corporation

Synergy SK-S7G2 Starter Kit

The performance of the S7G2 MCU drives an on-board 2.4" QVGA TFT LCD and supports IEEE 1588 Ethernet PTP, CAN, and RS-232/485. This makes the SK-S7G2 starter kit a great place to start for applications that require an intuitive HMI and deterministic connectivity.

Available from Digi-Key Electronics for $83.75

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www.embedded-computing.com

Dev Kit Weekly: 2020 Kit Roundup SECO SPA

UDOO X86 II ULTRA

This kit features all sorts of multimedia-centric interfaces that pair with the on-board Pentium processor to drive multiple simultaneous displays in applications like digital signage. Ethernet and wireless slots also allow you to interface this gateway-class device with the rest of the world.

Available from the UDOO Shop for $267

Silicon Laboratories

Bluetooth Xpress BGX13P Evaluation Kit

Based on the BGX13P Bluetooth module with programmable output power, the Bluetooth Xpress BGX13P Evaluation Kit includes a radio and all of the PHYs required by the Bluetooth 5 spec a for line-of-sight wireless transmission range of up to 200 m.

Available from Verical, an Arrow Company for $19.99

Texas Instruments Incorporated

AWR1642BOOST mmWave Radar Eval Module

The AWR1642BOOST mmWave radar sensor scans 4 GHz simultaneously in the 76 to 81 GHz bands, delivering twice the bandwidth of alternatives. It also integrates an Arm Cortex-R4F and TI C674X DSP so that baseband and FMCW algorithm processing can be performed locally.

Available from Digi-Key Electronics for $310.48

Texas Instruments Incorporated

TI-RSLK MAX Robotics Learning Kit

The RSLK MAX is TI’s second-generation robotics system learning kit, only this one uses a completely solderless design. It includes a SimpleLink LaunchPad development kit driven by an MSP432 MCU, a 5V DC-DC regulator, 3.3V linear regulator, dual built-in motor drivers, radars, and more.

Available from Texas Instruments Incorporated for $109

Thundercomm Technology Co., Ltd.

TurboX AI Kit

The Thundercomm TurboX module is based on the Qualcomm SDA845 heterogeneous SoC, which integrates 8 Kyro CPUs, an Adreno 630 GPU, a Hexagon 685 DSP, and a dual 14-bit Qualcomm Spectra 280 ISP. All of that compute delivers 450 GigaFlops of performance.

Available from the Thundercomm Store for $799 www.embedded-computing.com

Embedded Computing Design | Spring 2020

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Embedded Computing Design

2020 EMBEDDED WORLD

The 2020 Embedded Computing Design embedded world issue showcases embedded tools and solutions for those designing in the areas of industrial control, edge computing, autonomous machines, and more.

AI & MACHINE LEARNING

INDUSTRIAL

Diamond Systems

32

AI DEVELOPMENT KITS

Premio, Inc.

37

IOT

ADLINK Technology Inc

33

Foundries.io 38

HARDWARE

PROCESSING

Acromag 33 Avnet Integrated 34 Digilent Inc 35 Technologic Systems 36

Diamond Systems

38

STORAGE Virtium 39

AI & Machine Learning

STEVIE CARRIER SOLUTION FOR NVIDIA® JETSON® AGX XAVIER® STEVIE carrier board for the NVIDIA® Jetson™ AGX Xavier computer module offers a compact, low-cost, feature-packed solution. STEVIE measures 92 x 105mm (~3.6 x 4.1"), just slightly larger than the module (87 x 100mm). This small outline maximizes feature density in the smallest amount of space.

STEVIE utilizes the module to deliver unmatched performance for AI, machine learning, image processing, and other compute-intensive tasks. It delivers up to 30 TeraOps in performance (3 x 1013 operations per second) at a maximum power dissipation of 30 watts. The module’s 512-core Volta GPU with Tensor Cores and accelerators enable high-performance AI-powered autonomous machines.

The most popular I/O is located along the front edge of the board using commercial style I/O connectors, simplifying integration into enclosures. Additional I/O is available via latching connectors. A camera module socket enables connection to a wide range of high-resolution cameras.

A built-in data acquisition subsystem with analog and digital I/O enables the monitoring and control of real-world events and devices. M.2 (2280 NVMe) and PCIe Minicard sockets enable the installation of flashdisk and I/O expansion modules to customize STEVIE. STEVIE is ideal for applications in commercial/industrial environments requiring low cost, compact size, and rich I/O. DIAMOND & MARK: Futura Medium PMS 526 C and PMS 1665 C

SYSTEM: Futura Heavy 80% tint of Black

Diamond Systems Corporation www.diamondsystems.com

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Embedded Computing Design | Spring 2020

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FEATURES Ą Compact, I/O-rich board at 92 x 105mm (~3.6 x 4.1") just slightly

larger than the AGX Xavier module

Ą I/O breakout includes: 2x USB3.1, 2x USB2.0, 2x Gigabit Ethernet,

2x HDMI, 4x RS-232/422/485, 2x CAN, Audio, Data acquisition

Ą Camera module socket with 4x4 CSI lanes supporting up to 8x

2-lane CSI cameras

Ą Mass storage: M.2 2280 NVME PCIe x4 socket,

UFS flash socket + Micro SD socket

Ą I/O expansion: 1 PCIe minicard socket Ą Most popular I/O is located along the front edge of the board using

commercial style panel I/O connectors for simplified installation

Ą Semi custom and full custom carriers available

www.diamondsystems.com/products/stevie

sales@diamondsystems.com

 www.linkedin.com/in/diamondsystems/

 +1 (650) 810-2500

 @diamondsystems www.embedded-computing.com

Vizi-AI – Industrial Machine Vision AI Developer Kit The Vizi-AI starter devkit combines plug and play hardware and software enabling a faster, easier and scalable starting point for machine vision AI deployments at the edge.

It includes an Intel Atom® based SMARC computer module with Intel® Distribution of OpenVINO™ toolkit and ADLINK Edge™ software.

Developers can easily connect Vizi-AI to different image capture devices and then deploy and improve machine learning models to harness insight from vision data to optimize operational decisionmaking. Vizi-AI has a range of pre-built OpenVINO compatible machine learning models that can be used straight out of the box.

The Vizi-AI devkit includes:

• ADLINK Edge™ software which provides enhanced functionality of

OpenVINO to connect to the ADLINK Data River™ which enables data to flow freely and securely

• ADLINK Edge™ Profile builder which provides a simple, intuitive user experience to manage devices and applications

• Intel Atom based SMARC computer module with Intel® Movidius™

• ADLINK Edge™ Model Manager which enables which users to add

• Intel Distribution of OpenVINO toolkit, which optimizes deep learn-

• Vizi-AI is also supported by its own community, www.goto50.ai

Myriad™ X VPU and 40 pin connector

ing workloads across Intel® architecture – including accelerators – and streamlines deployments from the edge to the cloud

ADLINK Technology GmbH www.adlinktech.com



their own models to a pre-loaded selection for easy deployment

where users can find support, pre-built scenarios and other useful resources

info@adlinktech.com

 +44 (0) 191-4979900

 www.linkedin.com/company/adlink-technology

 @ADLINK_Tech

Hardware

APZU: User-Configurable Zynq® UltraScale+TM APZU: MPSoC I/O Module The APZU series provides a Xilinx Zynq UltraScale+ multiprocessor system on a chip (MPSoC). This MPSoC integrates a feature-rich ARM-based processing system and programmable logic in a single device. Two dual-core ARM Cortex CPUs (A53 application processor and R5 real-time processor) deliver high-performance computation capability. Additional resources include onchip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. The integrated ASIC-class programmable logic is ideal for compute-intensive tasks and offloading critical applications.

The real value of the Zynq UltraScale+ MPSoC architecture lies in the tight integration of its programmable logic with the processing system. Its high throughput interface eliminates bottlenecks that plague two-chip ASSPFPGA solutions and allows designers to easily extend the processing system capabilities.

Now designers can build their own custom design by adding peripherals in the programmable logic and increase overall system performance by partitioning HW and SW functions with custom accelerators.

Designed for COTS applications these FPGA based digital I/O modules deliver economical user-customizable I/O in a high-density and very rugged form factor.

Acromag, Inc.

www.acromag.com www.embedded-computing.com



FEATURES Ą PCI Express Generation 1 interface Ą 64Mb quad serial flash memory Ą 2 GB (512M x32) LPDDR4 memory Ą DMA transfer support to move data between module

memory and PCIe bus Ą Bootable MicroSD Socket Ą Power up and system reset is failsafe Ą Conduction-cooled options

solutions@acromag.com

https://www.acromag.com/apzu

 www.linkedin.com/company/acromag

 877-295-7088 @Acromag



Embedded Computing Design | Spring 2020

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Embedded Computing Design

AI Development Kits

Embedded Computing Design

Hardware

/MSC HCC-CFLS Avnet Integrated introduces its new line of COM-HPC products starting with the MSC HCC-CFLS, a COM-HPC Client module and complement carrier board, the MSC HC-MB-EV. The module features a PICMG COM-HPC Client interface and comes in size C format (160mm x 120mm). The COM-HPC Client interface supports a total of 32 PCI Express lanes, 1G and NBASE-T (up to 10G) Ethernet ports, and DDI/eDP graphic interfaces. Designed for the 9th Generation Intel® Core™ S-Series Processor family, the module enables the greatest scalability from cost efficient Celeron up to powerful Xeon with eight cores. The versatile carrier board in microATX format enables designers a quick path to COM-HPC based product development.

FEATURES Ą 32x PCIe Ą 1 x NBASE-T (up to 10Gb) Ą 2x SoundWire/DMIC Ą 4x USB 3.1 / 4x USB 2.0 Ą 3x DDI Ą 1x eDP Ą 1x 1000BASE-T Ą 9th Generation Intel® Core™ S-Series Processor

www.avnet.com/wps/portal/integrated/products/embedded-boards/

Avnet Integrated

www.avnet.com/integrated





integrated@avnet.com  See website https://www.linkedin.com/showcase/18980630/

OpenSystems Media works with industry leaders to develop and publish content that educates our readers.

C and C++ Software Testing – Am I Covered?

By QA Systems This Whitepaper looks at the various applications of the term ‘coverage’ in the software development industry for software written in C and C++.

We look at the industry definitions of the terms, applications of the techniques in various software standards and some challenges for measuring coverage you may not have considered. We highlight how modern software testing tools (such as QA Systems, Cantata) can help speed up and monitor your testing progress with coverage. www.embedded-computing.com/white-paper-library/c-and-c-software-testing-am-i-covere

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Check out our white papers at www.embedded-computing.com/ white-paper-library www.embedded-computing.com

Eclypse Z7: Zynq-7000 SoC Development Board The Eclypse Z7 is a new open and customizable hardware and software ecosystem aimed at productivity through accelerating design flow. It's the first host board of the new Eclypse platform, showcasing modular functionality, high-speed I/O, and an FPGA SoC that blends power and flexibility for instrumentation applications.

In addition to a Zynq 7020 FPGA SoC from Xilinx, the Eclypse Z7 features two high-speed connectors using Opal Kelly’s new SYZYGY standard, which pairs with Digilent’s new Zmod family to allow for high performance I/O. The hardware, however, is only part of the story of the Eclypse Platform. It's more than a standard development board – it's a new way to streamline and accelerate design flow combined with a newly developed software architecture to create a powerful research and prototyping platform optimized for productivity and flexibility. Petalinux is supported out of the box, and prebuilt Linux images are accompanied

by a software API for bulk data transfer. This system allows new users to get started without touching the hardware until desired, and with support from a built-in high-level API, users can enjoy the benefits of hardware acceleration without having to directly interface with the FPGA.

Features

• Pre-built Linux images accompanied by a software API for bulk data transfer

• 2x SYZYGY standard interface connectors for Zmod

expansion supporting rates up to 500 MHz • Zynq 7020 SoC with 667 MHz dual core ARM Cortex-A9 processor and 13,300 logic slices • Ethernet connector with 10/100/1000 Ethernet PHY • Micro USB port for USBUART and JTAG programming (and JTAG programming header) • 1GB DDR3L with 32-bit bus @ 1866 MHz

For more information on the Eclypse Z7: http://bit.ly/2T0V80F

Digilent, Inc.

www.digilentinc.com www.embedded-computing.com





sales@digilentinc.com www.linkedin.com/company/digilent-inc-/

 214-552-5559 @digilentinc



Embedded Computing Design | Spring 2020

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Embedded Computing Design

Hardware

Embedded Computing Design

Hardware

TS-7800-V2 Single Board Computer Powered by the Marvell Armada 385 Dual Core 1.3 GHz ARM CPU, the TS-7800-V2 industrial Single Board Computer (SBC) stands out from the crowd with its high-performance components, connectivity options, and an unbelievable feature set packaged into a small footprint in both size and power. It’s a general-purpose, low-power SBC ready to tackle demanding applications including data acquisition, IoT, industrial automation, and anything in between.

Industry-standard interfaces, such as SuperSpeed USB 3.0 host, Gigabit Ethernet, RS-232 serial ports, and more are included. Additional storage or boot image is possible through the microSD socket.

A battery-backed real-time clock (BBRTC) keeps accurate time for the system and a watchdog timer is there to help when a system becomes unresponsive in the field.

Each component on the TS-7800-V2 has been carefully chosen to ensure reliable operation in the field. Data is reliably stored in the onboard eMMC flash. With the included heat sink the fanless design of the TS-7800-V2 is able to withstand high vibration, and even with two CPU cores running at 1GHz and tasked to their max the system can operate at a wide temperature range of -40 °C to 85 °C. A productive out-of-the-box experience includes pre-installed Linux OS, development tools, and utilities for controlling PC104 peripheral boards, DIO, CAN bus, a variety of serial interfaces and bringing in data from the analog ports, or monitoring the system temperature. The development kit makes sure you have all the necessary

connections and cables to get off the ground quickly. The guaranteed 10+ year lifecycle ensures a long-term deployment in the field, free from expensive replacements that come from short, disposable lifecycles which are all too common.

The TS-7800-V2 is a replacement for the original TS-7800 product while maintaining compatibility in electrical, mechanical, and software at the driver API level. The TS-7800-V2 provides a straightforward, low-risk upgrade for users of previous TS-7800, bringing enhanced processor performance, enhanced flash storage, and improved protection against obsolescence, all at no additional cost.

Industry-standard interfaces, such as SuperSpeed USB 3.0 host, Gigabit Ethernet, RS-232 serial ports, and more are included. Additional storage or boot image is possible through the microSD socket.

A battery-backed real-time clock (BBRTC) keeps accurate time for the system and a watchdog timer is there to help when a system becomes unresponsive in the field.

FEATURES Marvell Armada 385 Dual Core 1.3 GHz ARM CPU 1.3 GHz Dual Core CPU Ą 4 GB MLC eMMC Flash Ą 1 DDR3 RAM Ą 20k LUT Cyclone FPGA (145 Various I/O Pins) Ą Ą

www.embeddedarm.com/products/TS-7800-V2

Technologic Systems

www.embeddedarm.com

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Embedded Computing Design | Spring 2020

sales@embeddedarm.com

 480-837-5200

 @ts_embedded

www.embedded-computing.com

RCO-6100 Industrial Edge Computer Premio’s RCO-6100 Industrial Computer is a powerful edge machine dedicated for compute-intensive deployments in embedded IoT applications. This industrial computer is configurable with Intel’s 9th (Coffee Lake Refresh) Generation Core i3, i5, and i7 processors and delivers powerful edge computing performance in its new eight core design. The RCO-6100 also features a rugged fanless design and flaunts a sleek heatsink chassis that encompasses a variety of industrial features to perform in harsh environments from wide operating temperatures, wide voltage inputs, and tolerance for shock and vibrations. Premio’s RCO-6100 Industrial Computer is scalable in markets such as factory automation, testing equipment and metrology, kiosks, security and surveillance, and intelligent transportation.

The new RCO-6100 Series Industrial Computer features:

• Intel® Q370 chipset • 2x DDR4 2400/2666Hz SODIMM. Max. up to 64GB • Triple Independent Display by 1x DVI-I and 2x DisplayPort • 2x Intel® GbE supporting Wake-on-LAN and PXE • 6x RS-232/422/485 (w/2x internal), 4x USB 3.2 Gen 2, 5x USB 3.2 Gen 1 • 8x DI + 8x DO with isolation

Premio Inc.

https://premioinc.com

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Additional Features Ą Support 8th / 9th Gen. Intel® CFL-R S Processor

(LGA 1151, 65W/35W TDP)

Ą Wide Operating Temperature (-25°C to 70°C)

Ą 9 to 48VDC Wide Range Power Input Supporting AT/ATX Mode

Ą 2x Full-size mini PCIe for communication or expansion modules,

2x SIM socket

Ą 4x 2.5" SATA HDD Bay and 1x mSATA with RAID 0, 1, 5, 10 support Ą 1x M.2 (M Key, NVMe PCIe x4, 2280); 1x M.2 (E Key, PCIe x2,

USB 2.0, 2230)

Ą TPM 2.0 Supported https://premioinc.com/products/rco-6100?variant=31385875284033

sales@premioinc.com

 www.linkedin.com/company/premio-inc-

 626-839-3136

Industrial

WIO-W221C IP65 Waterproof Touchscreen Computer Premio’s WIO-W221C Industrial-grade panel PC features a certified IP65 waterproof and dustproof stainless steel enclosure that leverages lockable M12 connectors to protect against ingress of wide temperatures and high pressure water. It’s operating temperature between -10°C to 60°C is ideal for harsh remote deployments that require mission critical reliability. The main benefits of this panel pc is its rugged exterior chassis, fanless design, and the lockable waterproof connectors that makes the WIO-W221C suitable for many outdoor applications. This rugged touchscreen computer features Intel’s 7th (Kaby Lake) Generation Core i5/i3 mobile-u processor that is designed for space-Constrained, HighPerformance, Low-Power IoT Designs. Premio’s WIO-W221C Waterproof Panel PC is scalable in outdoor and harsh environments such underground mining and heavy equipment, factory automation, food and beverage manufacturing, outdoor kiosks, and intelligent public transportation.

The WIO-W221C Series IP65 Waterproof Touchscreen Computer features: • 8GB DDR4 Wide-temp SODIMM • 1x 256GB Wide-temp mSATA, 2x internal SIM socket • 2x LAN by M12 X-Code 8-pin • Multi-language OSD built-in

Premio Inc.

https://premioinc.com www.embedded-computing.com

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Additional Features Ą 21.5" TFT FHD 16:9 LCD with Projected Capacitive Touch Screen Ą Intel® Core™ Processor i5-7300U, up to 3.5GHz / i3-7100U, 2.4GHz Ą Full system IP65 compliant Ą Single display supported by 1x VGA (waterproof connector) Ą 2x USB 3.0 (waterproof connector) Ą 9 to 50VDC wide range power input Ą -10°C to 60°C extended operating temperature Ą Two 10W internal speakers built-in (Optional for IP65 Configuration) https://premioinc.com/products/wio-w221c?variant=31385780813889

sales@premioinc.com

 www.linkedin.com/company/premio-inc-

 626-839-3136

Embedded Computing Design | Spring 2020

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Embedded Computing Design

Industrial

Embedded Computing Design

IoT

Develop deploy & maintain secure IoT with Foundries.io Foundries.io is helping customers bring IoT/Edge devices to market faster, increasing their data security and substantially reducing the costs of developing, testing and deploying devices across their installed lifetime. We believe the latest software is the most secure.

The FoundriesFactory solution is a cloud subscription service offering a customizable open source firmware and OS software platform, built to ensure that IoT and Edge devices are secure, updatable and maintained throughout their lifetime.

FoundriesFactory offers businesses the ability to fully customize their product firmware and OS software, based on a supported and maintained Linux platform designed for IoT and Edge devices. FoundriesFactory offers cross architecture support (Arm, x86, RISC-V) giving customers a wide choice of hardware approaches to meet their end use needs.

FoundriesFactory supports platform and application software updates, build and test infrastructure, supported by the latest software and security patches. Automation enables devices to be continuously and remotely tested and updated, ensuring proactive management of device fleets. We provide security and functionality updates to the core platform through a customer’s product lifetime. Enabling secure lifetime maintenance of your entire product software stack.

FEATURES Ą Embedded firmware and distribution that is tailored to the needs of

your hardware, software and cloud services

Ą We create and host a unique customized CI and test infrastructure for

each product enabling customers to add their own product tests

Ą Continuous build integration and test infrastructure customized for

your product to keep your software up to date

Ą Choose your cloud providers including Alibaba, Amazon, Arm, Google,

IBM, Microsoft or private cloud

Ą Provide continuous updates to combine with your own IP, ensuring

you always deploy the latest software

Ą Rollout of security updates and or new functionality as needed over a

product’s lifetime

Ą Deliver Over-the-Air (OTA) updates for your product software, from

firmware to application and Docker containers

hello@foundries.io  @FoundriesIO  www.linkedin.com/company/foundriesio/

Foundries.io



https://foundries.io/products/

Processing

GEMINI CARRIER FOR COM EXPRESS with PCIe/104 EXPANSION GEMINI is a rugged COM Express Compact Type 6 carrier board/COM-based SBC with PCI/104-Express I/O expansion. It is available as a complete SBC with integrated Core i7 8th Generation “Whiskey Lake” processor or as a carrier board to be used with your own choice of COM. The feature-rich GEMINI offers high performance in a compact, rugged board. It is designed to support a variety of Type 6 95x95mm modules, from Bay Trail and Apollo Lake up to Core i7 and Xeon. With a Xeon COM, the PCIe/104 x16 lanes are supported for high performance graphics applications.

GEMINI provides key benefits of quick time to market for the latest processors, extended product life, rugged performance, rich I/O, and easy I/O expansion. The COM enables easy upgrade and replacement for product life extension.

The COM mounts on the bottom side, while the PCI/104-Express sockets are on top. Dimensions are 4.0" x 4.0", affording more PCB coastline for the rich selection of I/O features. A thicker PCB and -40/+85°C operation make GEMINI ideal for vehicle and rugged applications. Other notable features are M.2 and PCIe minicard sockets, TPM, and dual HDMI displays. Windows 10 and Ubuntu Linux 64-bit OS are supported.

DIAMOND & MARK: Futura Medium PMS 526 C and PMS 1665 C

SYSTEM: Futura Heavy 80% tint of Black

Diamond Systems Corporation www.diamondsystems.com

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Embedded Computing Design | Spring 2020

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FEATURES Ą COM Express Module mounts on bottom of board, PCI/104-Express Ą Ą Ą Ą Ą Ą

expansion sockets are on the top I/O breakout includes: 2x USB3.0, 4x USB2.0, 8x GPIO, 2x Gigabit Ethernet, 2x HDMI, LVDS 4 serial ports, software configurable RS-232/RS-422/RS-485 TPM 2.0 support PCI/104-Express Expansion: 4x PCIe x 1 ports, 1x PCIe x16 (Xeon only), 1x USB2.0, and 4-slot PCI support Storage expansion: 1x PCIe MiniCard socket with optional USB support, M.2 2242 SATA socket, 1 SATA connector Rugged design: thicker PCB (.090"/2.3mm), latching connectors, full -40°/+85°C operating temperature www.diamondsystems.com/products/gemini

sales@diamondsystems.com

 www.linkedin.com/in/diamondsystems/

 +1 (650) 810-2500

 @diamondsystems www.embedded-computing.com

®

Solid State Storage and Memory

Industrial-Grade Solid State Storage and Memory Virtium manufactures solid state storage and memory for the world’s top industrial embedded OEM customers. Our mission is to develop the most reliable storage and memory solutions with the greatest performance, consistency and longest product availability.

StorFly® SSD Storage includes: M.2, 2.5", 1.8", Slim SATA, mSATA, CFast, eUSB, Key, PATA CF and SD. Classes include: MLC (1X), pSLC (7X) and SLC (30X) – where X = number of entire drive-writes-per-day for the 3/5-year warranty period.

Industry Solutions include: Communications, Networking, Energy, Transportation, Industrial Automation, Medical, Smart Cities and Video/Signage.

Memory Products include: All DDR, DIMM, SODIMM, Mini-DIMM, Standard and VLP/ULP. Features server-grade, monolithic components, best-in-class designs, and conformal coating/under-filled heat sink options.

Features

New! XR (Extra-Rugged) Product Line of SSDs and Memory:

• Broad product portfolio from latest technology to legacy designs • 22 years refined U.S. production and 100% testing • A+ quality – backed by verified yield, on-time delivery and field-defects-per-million reports • Extreme durability, iTemp -40º to 85º C • Industrial SSD Software for security, maximum life and qualification • Longest product life cycles with cross-reference support for end-of-life competitive products • Leading innovator in small-form-factor, high-capacity, high-density, high-reliability designs • Worldwide Sales, FAE support and industry distribution

Virtium

www.virtium.com www.embedded-computing.com

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StorFly-XR SSDs enable multi-level protection in remote, extreme conditions that involve frequent shock and vibration, contaminating materials and/or extreme temperatures. Primary applications are battlefield technology, manned and unmanned aircraft, command and control, reconnaissance, satellite communications, and space programs. Also ideal for transportation and energy applications.

Currently available in 2.5" and Slim-SATA formats.

Include: custom ruggedization of key components, such as ultrarugged connectors and screw-down mounting, and when ordered with added BGA under-fill, can deliver unprecedented durability beyond that of standard MIL-810-compliant solutions.

XR-DIMM Memory Modules have the same extra-rugged features as the SSDs, and include heatsink options and 30μ" gold connectors.

They also meet US RTCA DO-160G standards.

sales@virtium.com www.linkedin.com/company/virtium

 949-888-2444 @virtium

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Embedded Computing Design | Spring 2020

39

Embedded Computing Design

Storage

ÂŽ

Solid State Storage and Memory