Embedded Computing Design Spring 2021 with Embedded World Profiles

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Development Kit Selector SPRING 2021 | VOLUME 19 | 1 | EMBEDDED-COMPUTING.COM

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EMBEDDED WORLD Profiles PG 30

The Security Challenges of a Connected World Interview with Mike Balow, Infineon Technologies

PG 16 INFINEON TECHNOLOGIES OPTIGA™ Connect IoT for Easy and Secure Cellular IoT Connectivity

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ChipWhisperer®-Pro (CW1200) Power Analysis & Fault Injection for Security Testing PG 36

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Embedded Computing Design EMBEDDED WORLD | Spring 2021

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CONTENTS

Spring 2021 | Volume 19 | Number 1

FEATURES 6

Just CPUs Were Never Enough

By Prasant Agarwal, Softnautics

10 Embedded Multicore and OpenAMP

By Colin Walls, Siemens Embedded 12 Compare MISRA C with SPARK for Safe and Secure Programming

12

By Yannick Moy, AdaCore

18 Fundamentals of IoT Security

By Eric Heiser, u-blox

bit.ly/ECDYouTubeChannel

Security threats are evolving as rapidly as the IoT itself. This means that electronic system developers must constantly reposition themselves to defend connected systems.

On page 16 of this issue, Mike Balow, Vice President of Connected Systems for the Americas at Infineon Technologies, discusses how technology organizations can be proactive amidst this constantly-changing landscape.

Show profiles from the virtual embedded world 2021 tradeshow and conference begin on page 30.

 Poor Software Quality Costs Trillions. Yes, Trillions.

By Andrew Phillips, TDK-Micronas

By Thomas Brand, Analog Devices

@embedded_comp

WEB EXTRAS

22 How to Overcome the Power Versus Heat Dissipation Challenge 28 Controlling Output Modules with Full Isolation from the Microcontroller

@Embedded.Computing.Design

COVER

Beyond Moore’s Law: Parallel Processing in Heterogeneous SoCs

By Brandon Lewis, Editor-in-Chief

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opsy.st/ECDLinkedIn

By Perry Cohen, Associate Editor

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www.embeddedcomputing.com/technology/ software-and-os/os-filesystems-libraries/poorsoftware-quality-costs-trillions-yes-trillions

 Embedded Toolbox: Prove It! Proofs Start Where Static Analysis Stops

30 2021 EMBEDDED WORLD PROFILES

By Brandon Lewis, Editor-in-Chief www.embeddedcomputing.com/technology/debugand-test/code-analysis-tools/embedded-toolboxprove-it-proofs-start-where-static-analysis-stops

 Designing an Automatic Bicycle Wheel Light PCB

By Jeremy Cook, Contributing Editor www.embeddedcomputing.com/technology/ analog-and-power/pcbs-components/designing-anautomatic-bicycle-wheel-light-pcb

Published by:

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COLUMNS 5

TRACKING TRENDS

By Brandon Lewis, Editor-in-Chief

4

Three Ways to Tenfold Embedded Memory for Heterogeneous Multicore Embedded Computing Design EMBEDDED WORLD | Spring 2021

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TRACKING TRENDS

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Three Ways to Tenfold Embedded Memory for Heterogeneous Multicore

By Brandon Lewis, Editor-in-Chief In theory, a heterogeneous multicore device can equip a compute block optimized for any type of operation a given use case can throw at it. A GPU for video processing, a neural network processor for object recognition, a CPU to run the OS, and so on. The different fit-for-purpose cores provide an SoC with more flexibility, and therefore greater performance and lower power consumption across a wider range of workloads, than a homogeneous processor of the same class.

But as you start considering the requirements of applications like edge-based AI, computer vision, etc., the truth is that I/O and memory become just as restrictive as raw processing performance, if not moreso.

“Memory speed is only going up so fast, right?” poses Deepu Talla, Vice President and General Manager of Embedded & Edge Computing at Nvidia. “It’s not growing exponentially. The bit width is approximately the same because of the size: It’s either 16-, 32-, 64-, 128-bit, whatever. And most of the embedded processors typically have 32-bit or maybe even 16-bit interfaces, again because of cost and size reasons.

“The speed of memory is only growing 2x generationover-generation, and that typically happens every three years,” he continues. “However, the compute requirements within the SoC have gone up probably 10x or 20x.”

How do you reconcile this disproportionate increase in compute performance against comparatively minor advances in memory technology? Particularly as processors evolve into unique collections of logic that all require their own access to resources like memory.

According to Talla, you give it to them. Here are three ways embedded memory architectures are advancing to meet the demands of next-generation heterogenous multicore processors. #1. Core-Specific SRAM “If you look at a lot of these embedded processors, they’ve always had SRAM in the past,” Talla says. “Now, for each specific unit, we have local SRAM, which gets data from DRAM, stores it locally and processes it, and then sends back the final output.”

Core-specific SRAM offers a couple advantages, starting with memory performance gains that result from not having to write temporary data back to off-chip DRAM. www.embedded-computing.com

This architecture also has the added benefit of reducing power consumption, because the very-low-voltage SRAM blocks reside nearby or adjacent to the corresponding logic IP within the SoC. “If you go to DRAM, that’s probably an order of magnitude more power, so you’re actually saving power by using those techniques,” Talla explains. #2. Increased System Memory Embedded processors today feature as much as 4 MB to 8 MB of system memory. This system memory is not dedicated to any one specific core, and can be shared between elements like a CPU, GPU, and accelerator.

Similar to the dedicated SRAM, the primary benefit of more shared system memory is fewer DRAM accesses.

For example, where a traditional video encoding sequence would look like this: DRAM -> Video Encoder -> DRAM -> Additional Compute -> DRAM Using shared system memory enables this: DRAM -> Video Encoder -> System Memory -> Additional Compute -> DRAM As stated, the difference being that separate cores don’t have to continually fetch data from an off-chip DRAM because the large system memory eliminates the need for that intermediate step. #3. Increased Cache Sizes Finally, as newer process technologies make higher capacity memory more affordable, cache sizes will inevitably increase. Larger caches for CPUs, GPUs, DSPs, and other core architectures found on a heterogeneous SoC will also mitigate the amount of DRAM traffic.

And pairing increased cache sizes with the previous two advancements starts yielding some serious gains.

“More SRAM, system memory that’s common across, and then more high-capacity caches allows you to increase performance by 10x to 100x over the next three-to-five years even though the memory bandwidth has probably only doubled or quadrupled,” Talla points out.

Hopefully that will buy us some breathing room.

Embedded Computing Design EMBEDDED WORLD | Spring 2021

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MOORE’S LAW VERSUS PARALLELISM

Beyond Moore’s Law: Parallel Processing in Heterogeneous SoCs

By Brandon Lewis, Editor-in-Chief With the dependable performance-per-watt gains of transistor scaling drawing to a close, how will future generations of processors access the compute necessary to efficiently execute demanding workloads?

The answer my come via parallel processing on heterogeneous SoCs.

“We’ve been working on 7 nm for a long time, and during that time we not only saw the end of Moore’s law, but we also saw the end of Amdahl’s law and Dennard scaling,” says Manuel Uhm, Director of Silicon Marketing at Xilinx.

“What that means is, if all we did was take an FPGA and just shrink those transistors to 7 nm from our previous node, which was 16 nm, and just call it a day, many customers trying to move over the exact same design might quite possibly end up with a design that quite frankly does not have any increase in performance and may, in fact, increase power consumption.

may be our best option in high-performance computing (HPC) and other demanding use cases.

“And clearly that’s going totally the wrong way.”

According to Mandell, a key driver of general-purpose heterogeneous computing platforms in the embedded market “is a lot of hesitancy among OEMs and others today about committing to a hardware architecture.” The hesitation, he says, is a product of rapid evolutions in specialized accelerated silicon, as well as uncertainty in the frameworks and workloads that will be produced by the edge software and AI ecosystems in the coming years.

To be clear, it’s not impossible to shrink silicon transistors below 7 nm; 5 nm devices are already in production. It’s that the underlying metal isn’t running any faster, and current leakage is on the rise.

Meanwhile, in the other direction, traditional multicore devices have hit scaling limitations of their own. Of course, those parallel processors have historically been homogeneous, “and the reality is there is no single processor archiecture that can do every task optimally,” Uhm contests. “Not an FPGA, not a CPU, not a GPU.” This isn’t to say parallelism can’t be advantageous in tackling the complex processing tasks presented by modern applications. Indeed, beyond Moore’s law and Dennard scaling, parallel computing

6

Yes, we still need parallel processing. But of the heterogeneous variety.

Heterogeneous Processing: Not Just for Data Center As mentioned, the bleeding edge of heterogeneous parallel processing technology is a response to performance walls in high-end applications. But these architectures are also becoming more commonplace in embedded computing environments.

Dan Mandell, Senior Analyst at VDC Research, points out that while “it is true that many heterogeneous processing architectures have been focused on high-end applications, particularly for the datacenter and HPC … miniaturization of FPGA SoCs and other heterogeneous accelerated silicon is top of mind for companies like Microsemi and Xilinx to bring more of these devices into intelligent edge infrastructure like edge/ industrial servers and IoT gateways.”

He expects all of these circumstances to “have a great influence in future semiconductor sourcing,” as well as how chip suppliers approach their processor roadmaps.

“The price and power envelope of most of these FPGA SoCs today will force suppliers to initially focus on relatively high-end, high-resource embedded and edge applications,” Mandell posits. “However, there is an active effort to make FPGA SoCs ‘size agnostic’ to eventually support even battery-powered connectivity devices.”

So as heterogenous parallel processing becomes more commonplace, should embedded engineers prepare for a paradigm shift in system design? Deepu Talla, Vice President and General Manager of Embedded & Edge Computing at Nvidia, doesn’t think so.

“If you think about it, embedded processors have always used accelerators,” Talla says. “Even 20 years ago, there was an Arm CPU, there was a DSP, and then there was video encode/decode done in specific hardware, right? They’re fixed-function in some sense, but they’re all processing things in parallel.

Embedded Computing Design EMBEDDED WORLD | Spring 2021

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MOORE’S LAW VERSUS PARALLELISM

“The reason you needed to do that was cost, power, size,” he continues. “The efficiency of the parallel processor is orders of magnitude more than just the CPU.” Nvidia’s Xavier SoC, the device at the heart of their Jetson Xavier embedded platform, as well as the company’s next-generation Orin architecture that will be available in late 2021 or 2022, both equip GPUs, Arm CPUs, deep learning accelerators, vision accelerators, encoders/decoders, and other specialized processing blocks.

However, one change embedded developers can expect as advanced heterogeneous SoCs become more prevalent is the use of network-on-chip (NoC) interconnects, which have progressed over the last decade from traditional on-chip buses like the AMBA interface. This provides “control over how you connect the CPU, GPU, your video encoder, deep learning accelerator, the display processor, the camera processor, the security processor, all those things,” Talla says.

NoCs help accelerate and optimize the flow of data from block to block across the SoC, which aids in the most efficient workload execution possible. For example, NXP has leveraged both NoCs and traditional bus architectures in their versatile line of i.MX SoCs. Recently, the company announced the i.MX9.

“Heterogeneous compute is something that we’ve actually been implementing for many years. I believe now is where we are really starting to hit that sweet spot of how we’re using it,” says Dr. Gowrishankar Chindalore, Head of Business & Technology Strategy for Edge Processing at NXP Semiconductors, Inc. “The same is happening with machine learning, because we’re using a CPU, GPU, DSPs, and neural processing unit (NPU) today.

“But part of the optimization, it’s not just the compute elements, it’s everything around the system that needs to happen,” he continues. “So where we’re focusing on improving efficiency, in addition to the heterogeneous compute, is looking at wastage through the whole flow in the chip division pipeline, the video pipeline, the graphics pipeline.

“Because the more that we can do that, the more efficiency we get in performance and, clearly, the less energy that’s used to do the same function,” he adds.

Heading Towards a Heterogeneous World Citing VDC Research’s 2020 IoT, Embedded & Mobile Processors technology report, Mandell expects the global market for embedded SoCs to “continue outgrowing the merchant markets for discrete semiconductors such as MPUs, MCUs, GPUs, etc. for the next several years,” as OEMs look to consolidate computing resources and multichip implementations. Over the long term, the demand for workload acceleration and processor optimization will only “drive a further uptick,” he says.

In the mean time, the way we measure performance and power consumptiton will have to change. As Mike Demler, Senior Analyst at The Linley Group addresses in his firm’s Guide to Processors for Deep Learning asserts, even new AI-centtric benchmarks like TOPS/W are “misleading, because the real AI workloads never achieve close to 100 percent utilization.”

We will have to measure things like power efficiency with “a real workload, such as Bert NLP models, rather than a theoretical, architecture-based specification,” he says.

But does it even make sense to measure the processor complex in isolation anymore?

Did it ever really matter? As it always has, the focus will be on what it delivers in the context of your system. www.embedded-computing.com

“WE REALIZED THAT WE’RE GOING TO BE ABLE TO OFFER INCREASED PERFORMANCE OR DECREASE POWER CONSUMPTION, AND IN SOME CASES IT’S EITHER/OR. IT’S NOT ALWAYS A GIVEN THAT YOU’RE GOING TO GET BOTH.” “Before with every process node, it’s like, ‘Oh great. I get double the performance at half the power consumption!’

Uhm says. “Those days are gone. Those days are absolutely gone for everybody.

At 7 nm, those transistors start getting leaky now. And you just run into other kinds of problems that are, in many cases, we believe, insurmountable.

“And so, having come to that realization, we’re looking now at system-level problems,” he continues “We’re putting all these things together and understanding all those trade-offs and making sure that we’re able to encompass as much of the processing as possible in a way that allows the performance and power budgets to be met. And again, those aren’t easy things anymore. We realized that we’re going to be able to offer increased performance or decrease power consumption, and in some cases it’s either/or. It’s not always a given that you’re going to get both.

“Again, no processor is optimal for everything. You can’t always increase performance and lower power consumption,” Uhm continues. “But focusing on this new architecture, a heterogeneous processor, essentially that allows them to do that.”

Embedded Computing Design EMBEDDED WORLD | Spring 2021

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MOORE’S LAW VERSUS PARALLELISM

Just CPUs Were Never Enough

By Prasant Agarwal, Softnautics

2020 was a landmark year for the graphics cards market. AMD and Nvidia were joined by Intel, who re-entered the GPU market nearly 22 years after it launched the i740 in 1998. The buzz is also growing around a fourth player, Huawei, potentially joining the GPU market with big plans in the data center.

I

t’s important to understand why it became necessary for Intel to revamp its GPU line (along with its visual identity) although it was already a leader in the PC market. AMD has made up significant ground in the desktop space over the last 12 quarters (the typical timeframe to develop a new chip), making it clear that Intel needed to offer a full range of compute solutions and expand beyond CPUs (Figure 1).

In fact, this process began in 2018 when Intel started making serious changes to its roadmap and reemphasizing FPGAs and GPUs. While many thought that the acquisition of Altera was to kill competition, it actually proved to be a testing ground for the much broader strategy of developing a high-performance GPU solution that went well beyond the company’s integrated graphics offerings.

Intel’s desire to increase GPU market share was accelerated by the emergence of artificial intelligence and machine learning technologies that are likely to drive demand for more compute performance as adoption increases. With Moore’s law already failing, CPU performance alone is not going to be enough to support the excessive demands of evolving deep learning algorithms over the long term.

The need to accelerate the performance of entire systems has been apparent, and FPGAs/GPUs are the de facto choice for supplementing CPUs.

Softnautics Inc.

www. softnautics.com

8

TWITTER

@softnautics

FIGURE 1

AMD has closed the gap in desktop market share between itself and Intel over the last 12 quarters.

As a result, CPUs have been commoditized and the real game is now being played in accelerators, where Intel has historically had a weak hand. To support this endeavor, Intel created a powerful team to support the recently-launched Intel Xe graphics portfolio. This team includes Raja Koduri, formerly the head of AMD’s Radeon unit, and Jim Keller, a famed chip designer and Lead Architect at AMD. Could it be that the third time is a charm for Intel after its brief attempt to re-enter the graphics space with Larrabee and Xeon Phi in 2009? Only time will tell. But this certainly emphasizes the importance of GPUs in the next wave of AI and machine learning computation.

Charles Darwin is back. This time it’s to demand the survival of the fittest in the embedded processing market.

Prasant Agarwal is Marketing Director at Softnautics. He has 15-plus years of experience in developing cutting-edge multimedia and connectivity products for STMicroelectronics, Samsung, and Solarflare Communications (Now Xilinx), and led corporate rebranding for Persistent Systems.

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Embedded Multicore and OpenAMP

By Colin Walls, Siemens Embedded

Every embedded system is different. And so, as multicore designs become increasingly common, almost to the point of being mainstream, different hardware and software architectures are evolving.

F

rom the software perspective, there are broadly two options: symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP).

to be identical. Each OS may be selected according to the intended functionality of the core and does not need to be a special, “multicore-enabled” version.

Inside SMP The objective of SMP is to increase available processing performance in a power-efficient manner, and it is very commonly found on desktop and laptop computers.

Unlike SMP, AMP does not require all the cores to be identical – it may be implemented on a heterogeneous multicore platform – which is advantageous because most multicore SoC devices include a variety of core architectures as different core architectures may be suitable for different parts of the application.

An SMP system can only be implemented on a homogeneous multicore platform (i.e., all the cores are identical). A single instance of an operating system (OS) runs across all the cores, and this OS needs to be a specific variant that supports SMP operations. Today, SMP is supported by Linux and a number of real-time OS products.

With SMP, tasks are distributed across the cores automatically.

However, there may be an option to lock tasks to specific cores if that is required for a particular application.

AMP and Embedded Systems For embedded applications, AMP provides more flexibility and is, hence, much more common.

In an AMP system, each core runs its own OS (or may run bare metal with no OS at all). There is no requirement for the OSs

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However, there are two matters that need to be resolved in an AMP design: lifecycle management (boot sequence, etc.) and inter-core communications. These issues do not arise in an SMP system, as the OS has control over which tasks run where and when and inter-task communication uses the standard OS APIs because the tasks do not need to “know” they are running in a multicore context. In an AMP system, each OS is unaware of the existence of the others, so specific provisions must be made.

OpenAMP: A Multiprocessing Framework The best way to configure an AMP system is to use some kind of multicore framework to address the control and communication requirements. OpenAMP1 is a standard that defines the architecture of such a framework; implementations of OpenAMP are available from a number of vendors.

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requirement that all CPUs are identical and, hence, it can only be used on a homogeneous multicore platform. However, in a complex multicore system, there may be groups of identical cores that can be managed using an SMP OS or a hypervisor, linked to the rest of the system using a multicore framework.

FIGURE 1

OpenAMP provides an architectural framework for asymmetric multiprocessing in multicore embedded systems.

An instance of the framework runs on each core. Lifecycle management is provided by using the Remoteproc framework2, where one core is designated as the “master”. Inter-core communication is managed using RPMsg3, which provides a channel-based, bi-directional communication link between cores.

An alternative to using a multicore framework is to deploy a hypervisor. This is a powerful option but is limited by its

Colin Walls is currently an embedded software technologist at Siemens, and has more than 40 years’ experience in the electronics industry (largely involved with embedded software – very much a pioneer in this specialty). Colin has authored a great many technical articles and one of the first books on embedded software, Programming Dedicated Microprocessors (Macmillan Education, 1986). His most recent publication is Embedded Software: The Works (2nd edition; Newnes, 2012), which addresses a wide range of embedded software topics.

References:

1. The openamp project. Retrieved from www.openampproject.org.

2. Remote Processor Framework. Retrieved from www.kernel.org/doc/Documentation/remoteproc.txt.

3. Remote Processor Messaging (rpmsg) Framework. Retrieved from www.kernel.org/doc/Documentation/rpmsg.txt.

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SAFETY & SECURITY STANDARDS

Compare MISRA C With SPARK For Safe and Secure Programming

By Yannick Moy, AdaCore

As part of the Linux Security Summit Europe last October, I participated in a panel around the question, “Would Abandoning the C Language Really Help?” C, which is the main language used in the Linux kernel, is notorious for having an endless source of vulnerabilities. Just look at the long list of open bugs automatically reported by the fuzzing robot syzbot that are still waiting for a fix.1

T

he panel discussion revolved around alternative, safer languages that are suitable for kernel development like Ada and Rust, as well as the need for formal verification to go beyond the guarantees that a compiler can provide. Indeed, many memory and safety vulnerabilities currently reported on the Linux kernel would stop the program altogether in Ada or Rust, which is only slightly better.

Looking at kernel patches reveals that many issues could be detected by specifying simple properties on the code, like what calls are legal in which mode, the types of data invariants that should be preserved, and how to verify them statically using appropriate tools.

Surprisingly, MISRA C was not mentioned at all during the discussion, even though

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it has established itself as a must-have in a number of industries to protect against fallibilities of the C language. MISRA C appeared in 1998 as a coding standard for C, initially for the automotive industry, and has been revised twice. The current version is MISRA C:2012. It focuses on avoiding error-prone features of the C programming language rather than enforcing a particular programming style. A study of coding standards for C, written by Les Hatton, found that, compared to ten typical coding standards for C, MISRA C was the only one to focus exclusively on error avoidance rather than style enforcement, and by a very large margin.2 The popularity of the C programming language, as well as its many traps and pitfalls, have led to the huge success of MISRA C in domains where C is used for high-integrity software. This success has driven tool vendors to propose many competing implementations of MISRA C checkers.3 Tools compete, in particular, on the coverage of MISRA C guidelines that they help enforce, as it is impossible to enforce all of the 16 directives and 143 rules (collectively referred to as guidelines) of MISRA C. In particular, 27 rules out of 143 are not decidable, so no tool can always detect all violations of these rules without, at the same time, reporting “false alarms” on code that does not constitute a violation. An example of an undecidable rule is rule 1.3: “There shall be no occurrence of undefined or critical unspecified behavior.”

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Toward implementation guidance Platinum: Full functional requirements

Effort & Skills

Gold: Key integrity properties

Only for a subset of the code subject to specific key integrity properties (functional safety, security)

Silver: Runtime errors & CWE

Bronze: Flow constraints

Stone: Safer, analyzable analysable language subset

FIGURE 1

The default target for critical software (subject to costs and limitations) For the largest part of the code as possible An intermediate level during adoption

The five levels of SPARK adoption.

› The static analysis tools work mostly at the granularity of an individual function, making the analysis more precise and minimizing the possibility of false alarms. › The static analysis tools are interactive, allowing users to guide the analysis if necessary or desired, and providing counter-examples when user-supplied contracts cannot be proved.

Appendix H of MISRA C:2012 lists hundreds of cases of undefined and critical unspecified behavior in the C programming language standard, a majority of which is not individually decidable.

For the most part, MISRA C checkers ignore undecidable rules such as rule 1.3, although violations of these rules are known to have a dramatic impact on software quality.

However, for other programming languages, static-analysis technology is available that can tackle this challenge without inundating users with false alarms. One example is the SPARK toolset developed by AdaCore, Altran, and Inria, which is based on four principles: › The base language Ada provides a solid foundation for static analysis through a well-defined language standard, strong typing, and rich specification features. › The SPARK subset of Ada restricts the base language in essential ways to support static analysis, by controlling sources of ambiguity such as side-effects in functions and aliasing of names. www.embedded-computing.com

As shown in Figure 1, SPARK can be incrementally adopted in a C codebase, progressively gaining assurance through the five levels of SPARK adoption and by supporting “hybrid verification” that combines formal analysis (SPARK) with traditional testingbased methods (C).4 SPARK Stone Level – Basic Guarantees The first level of SPARK adoption is called the Stone Level. It corresponds to code that conforms to the SPARK subset of Ada. Just adopting this level guarantees many consistency properties that cannot be enforced for C. These include: › The use of a proper package system as opposed to C’s use of textual-based inclusion of files with no consistency requirements across translation units. › Strict and readable syntax that emphasizes clarity and minimizes “gotchas” as opposed to C’s very permissive syntax which makes it easy to write programs whose effect is not what was intended. › Adherence to the strong typing rules of Ada and SPARK, as opposed to C’s “poor type safety [that] permits a wide range of implicit type conversions to take place [which] can compromise safety as their implementation-defined aspects can cause developer confusion.” (MISRA C:2012, Annex C).

MISRA C attempts to tame these possible inconsistencies of the C language with a variety of guidelines. It defines, in particular, stronger typing rules (“The essential type model”) and restricts the use of function parameters/results and control structures.

While these avoid common sources of developer confusion, they are intentionally not bulletproof, as they would otherwise make most C programs illegal.

These basic guarantees are easily achieved in SPARK with a simple compiler-like ­analysis by a tool called GNATprove, thanks to the stronger rules that define the SPARK subset of Ada. SPARK Silver Level – Strong Safety & Security Guarantees MISRA C guidelines also aim at preventing more subtle errors, reads of uninitialized data, conflicting side-effects in expressions, and undefined behavior such as division Embedded Computing Design EMBEDDED WORLD | Spring 2021

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SAFETY & SECURITY STANDARDS

by zeros or buffer overflows (which can have safety as well as security consequences). All of this falls into the category of undecidable rules, for which few MISRA C checkers provide complete detection.

These are completely prevented at the Silver level of SPARK adoption, which corresponds to analyzing the program with both flow analysis (reaching the second level of SPARK adoption called Bronze), and proof of the absence of runtime errors (reaching the third level, i.e. Silver). To reach this level, a developer will generally need to define types with the specific constraints that they are designed to support and supply contracts on functions exported between files – using so-called preconditions for specifying the obligations on the caller, and postconditions for specifying the obligations on the callee.

The process for reaching the Silver level involves interaction with the IDE. The developer runs the GNATprove tool (possibly on a subset of the program), investigates the GNATprove diagnostics, updates the program accordingly, and repeats. Such interactions are facilitated by the detailed information provided by GNATprove at every step to guide developers.

Figure 2 shows an example of a message displayed by GNATprove.

After locating the addition operation, which may cause an overflow, GNATprove gives an example of a value triggering the problem – here the largest Integer value (denoted Integer’Last in SPARK).

The “reason for check” explains clearly that the result of the addition should fit in a machine integer, which is not the case if X is the largest integer value before the addition. Then, GNATprove suggests that adding a suitable precondition to the function Incr might solve the problem by specifying here that X cannot be that largest value.

SPARK Beyond the Silver Level There are further benefits of using SPARK that go well beyond what MISRA C checkers can provide. At the Gold and Platinum levels, a developer specifies properties of the program through

14

FIGURE 2

A message displayed by GNATprove.

SPARK contracts and can then use GNATprove to guarantee that these properties will be met. A developer can also enable GNATprove warnings to detect dead code (also an objective pursued by MISRA C) and inconsistencies in the code, using the powerful proof technology that forms the basis of GNATprove analysis.

Conclusion Essentially, all objectives pursued by MISRA C are best achieved in SPARK, with a combination of a stronger base language (Ada) and a powerful analysis tool (GNATprove).

Developers who are planning to use MISRA C rules can achieve increased assurance by adopting SPARK for part of their applications.

The rules in MISRA C represent an impressive collective effort to improve the reliability of C code in critical applications, with a focus on avoiding error-prone features rather than enforcing a particular programming style. At a fundamental level, however, MISRA C is still built on a base language that was not really designed with the goal of supporting large high-assurance applications. It’s hard to retrofit reliability, safety, and security into a language that did not have these as goals from the start.

As C will remain the base language for large programs like the Linux kernel, we can foresee the coexistence of two trends to protect better against fallibilities in C programs where MISRA C can play a role, and to replace C with safer languages like Rust and SPARK Ada for part of the code. Major actors in the automotive industry have already started on this latter path, like NVIDIA5 and JTEKT.6 A detailed comparison of SPARK and MISRA-C, as well as various courses to learn Ada and SPARK, can be found at AdaCore’s learn.adacore.com site.

Guidance for adoption of SPARK can be found at https://www.adacore.com/books/ implementation-guidance-spark/.

The GNATprove tool is freely available as part of the GNAT Community Edition at https://www.adacore.com/download.

Yannick Moy is SPARK Product Manager at AdaCore and co-director of the ProofInUse joint laboratory with Inria. He leads the development of SPARK and previously worked on source code analyzers for PolySpace (now The MathWorks) and at Université Paris-Sud. References:

1. Syzbot. https://syzkaller.appspot.com/upstream.

2. Hatton, L. (2004). Safer Language Subsets: An Overview and a Case History, MISRA C. Information and Software Technology, 46(7), 465–472. https://doi.org/10.1016/j. infsof.2003.09.016.

3. MISRA C. Wikipedia. https://en.wikipedia.org/wiki/MISRA_C

4. Climbing the Software Assurance Ladder – AdaCore. https://www.adacore.com/papers/climbingthe-software-assurance-ladder.

5. AdaCore Enhances Security-Critical Firmware with NVIDIA. AdaCore. https://www.adacore.com/ press/adacore-enhances-security-critical-firmware-with-nvidia.

6. Electric Power Steering System Supplier JTEKT Selects SPARK Pro for Safety-Critical Automotive Software. AdaCore. https://www.adacore.com/press/jtekt-spark-pro-automotive.

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The Era of 5G, Industry 5.0, and AI Comes with Challenges Interview with Stefan Skarin, CEO of IAR Systems

How has the pandemic affected your business, and what do you expect the “new normal” to look like?

Will 2021 be the year that RISC-V gains a significant market share? Why or why not?

SKARIN: I always try to see potential instead of problems. And however counterintuitive it might sound, the pandemic has given us the potential to get to know our colleagues and customers on a personal level even though we are not meeting in person. With everyone attending virtual meetings from home, you get to interact on a new level, with the person in their home, and sometimes even meet their cat.

SKARIN: Yes and no. I do believe that 2021 will be a breakout year for RISC-V. The ecosystem continues to grow and we are seeing smaller customers starting to use it, but we are also seeing R&D groups at some larger companies starting to explore the architecture, and there are few large companies committed to using it in at least some business units. However, the architecture is still young, and there is definitely a lot of caution around new technology, especially among larger corporations.

Another challenge that can bring potential is the need for efficient workflows and problem solving over long distances.

I believe this added flexibility is what we will keep as the new normal.

With reports of hacks and breaches occurring on a regular basis, why are we still having such a difficult time convincing the embedded community that security must be baked into their designs right from the start?

SKARIN: I think it’s a combination of a few different factors. As humans, we are creatures of habit, and change can be hard.

Developers are just not in the habit of working with security and they will need a strong reason to change that. In addition, everyone is busy, and wants to save time as well as money.

When cutting corners to save resources, security is often taken out of the equation. Why? Well, it could have to do with a lack of liability. However, that is changing and with legislation rapidly coming in place, security is becoming a personal liability for CEOs and CISOs, among others. This will make it harder to cut security out.

Another factor is the fact that security in MCUs is mainly available in high-end (expensive) devices. Many of our customers are not ready to move from their current device. We believe there is still plenty to be done, perhaps not reaching the maximum level of security, but security that could be “good enough” for the application at hand. Security should not be all or nothing; the important thing right now is to get started, and reach a higher level than we have today.

What’s the biggest challenge developers face as we move into the era of Industry 5.0, 5G, and extensive use of artificial intelligence?

SKARIN: Those technologies you mention are all the keys to our future. However, none of them will be realized to their full potential if we don’t improve our code quality. We will need to push out quality software as fast as possible. This is a really tricky problem, because if you go too fast you tend to make mistakes, and if you get something wrong in your embedded code, it can render the system inoperable. This challenge is more and more being solved through the use of continuous integration and continuous deployment. These techniques help to improve efficiency, but also quality, if done right. By implementing code quality checks and automated testing, it’s possible to easily verify that the created software conforms to safe and reliable coding practices, and behaves the way it’s supposed to.

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Addressing Security Challenges in an Increasingly Connected World

By Mike Balow, Americas Vice President of Connected Secure Systems, Infineon Technologies What’s the latest IoT security horror story that you’ve heard? How did it happen, what did it cost, and how could it have been prevented?

BALOW: There have been quite a few troubling incidents, but I see them more as wakeup calls than true horror stories.

As for the cost of incidents, actual damage is often kept confidential.

Dollar value is just one way to measure loss though, and as the IoT extends into consumer-facing products, the impact of a security breach can be much greater than lost production. To start, incidents get a lot more public exposure. When security researchers successfully attacked automated driver assist systems a few years back it made worldwide headlines.

We’ve also repeatedly seen reports of connected home devices being attacked.

One example among many is a 2019 case in Tennessee, where a family discovered that an in-home connected camera was accessed by outside intruders. It turns out that the household Wi-Fi was not appropriately secured and the family didn’t use two-factor authentication, but that explanation raises a serious issue for suppliers of IoT products. Succeeding in smart homes and other emerging areas means making security both strong and easy to implement. Ideally, it should be built-in from the beginning and in a comprehensive, ideally automated, way that needs little or even no interaction by the user.

We’ve all heard the saying that the good guys have to get it right “every time” when it comes to security, but the bad guys only have to get it right once. Taking that statement

at face value for a moment, security breaches and vulnerabilities are inevitable.

So, does this mean that, moving forward, technology organizations will have to integrate dedicated security departments or organizations regardless of their position in the supply chain to ensure they can be “right” as close to “every time” as possible?

BALOW: As I mentioned, the incidents that have occurred have woken up the industry to security risks. Today’s focus on developing “smart” products, which of course means connected products, has made system-level and end-to-end security a top design priority.

A part of the change in priority has been a recognition of how to embed security into every design. Security is built on authentication, encryption, and integrity at every access point to a system. Since the early 2000s, Infineon has supplied Trusted Platform Module-compliant (TPM-compliant) devices, which are certified security microcontrollers that provide a Root of Trust (RoT) as the basis for security architectures in computing devices. Hardware-based security has proven to be far more resilient than software-only approaches and this approach to RoT is now incorporated into nearly every type of embedded system security design.

At Infineon, hardware RoT is implemented in a family of stand-alone security processors, our OPTIGA™ portfolio, as well as in trusted microcontrollers with integrated security hardware that include the AURIX™ and PSoC® 64 microcontrollers. Beyond security controllers, we provide the highly secured NOR Flash memory devices and secured Wi-Fi/Bluetooth connectivity ICs. Our security chips are based on decades of expertise and work to advance the stateof-the-art, and are produced in secured and certified environments. Certification extends throughout the value chain, so customers don´t need to secure and audit the complete value chain separately. Device manufacturers benefit from our investment in R&D and extensive production and logistics infrastructure.

In an era where sales are often driven by low cost and short time to market, security offers little conspicuous ROI and adds development time. What strategies, tools, tips, or techniques are available to development organizations that can help them streamline robust security implementations and meet their goals?

BALOW: What we’ve seen is that the industry’s move to security by design recognizes that there is an ROI. Look at authentication, even in non-connected products.

In consumer electronics products, authentication is about product integrity. In ink jet printers and digital cameras, adding an authentication IC to ink cartridges and batteries assures that counterfeit products of potentially low quality or even user risk cannot be used. It’s hard to measure the value of protecting integrity. For the printer manufacturer, the same feature also protects recurring revenue from sale of consumables, and that’s an easy value to calculate.

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Based on your interaction with customers, do you think the adoption rate of sufficiently robust security architectures and practices in the connected device industry is sufficient today, at least at a company/ organizational level? Why so high or so low, and what’s needed to move that needle?

FIGURE 1

A broad range of defenses exist to protect IoT devices

With connected devices, authentication is the basis for encryption and for guarding security keys that are essential to protecting the system. It’s why we are seeing the concept being incorporated into regulatory frameworks, such as the UK Code of Practice, ETSI standards, and state regulations recently rolled-out in California and Oregon.

Reference designs and pre-certified solutions help manufacturers meet their own goals and emerging requirements for built-in security (Figure 1). These involve more than just a module delivered to a manufacturing site. OPTIGA and our other security controllers include a unique cryptographic key pair and certificate stored in hardware.

Behind the hardware is a trusted process to deliver it to the customer, from design environments and manufacturing sites to protected key programming, with security certification at every step.

Security has been a challenge since the inception of the Internet of Things, but in that time a rash of new technologies have become poised to upend traditional approaches to security. These include Differential Power Analysis (DPA), AI, and quantum cryptography. How do, or should, these developments impact the security posture of technology organizations looking to protect themselves in the near-, mid-, and long-term?

BALOW: You’re right. As long as there are bad actors trying to penetrate security, the science behind security will keep advancing. Protections against DPA and other types of “side-channel” attack techniques were specifically addressed in our security controllers even before such attacks were made public. This was possible as we are constantly pushing the boundaries of countermeasures research with our own internal teams and in cooperation with the global security community. For instance, Infineon is active in development of next-generation cryptography and algorithms related to quantum cryptography, including a global competition to establish standards sponsored by the US National Institutes of Science and Technology (NIST). The company also was recognized as early as 2017 for its work in implementing post-quantum cryptography on contactless security chips like those used in bank cards.

In addition to helping drive the state-of-the-art in crypto, we are working to extend the scope of hardware-based protection across all classes of devices and connectivity.

We did that last year for cellular connectivity of IoT devices with the launch of OPTIGA Connect IoT, a turnkey embedded SIM (eSIM) that supports carrier-agnostic coverage in more than 200 countries and territories. It’s simple, fast, and secured Internet connectivity that let’s IoT system builders focus on what they do best, knowing that security is built in.

BALOW: I talked already about how we’ve seen security move to the top of priority lists for any company that’s building connected products, which means just about every company. In the industrial IoT in particular, new systems are implemented with very solid architectures. There are likely still some vulnerabilities in legacy systems, but awareness and proactive approaches are the norm, not the exception.

In the consumer IoT, comprehensive approaches and implementations of security are now like table stakes to enter the market. Consumers are growing more aware of the need to secure these systems and starting to think about their own vulnerability. And the industry is responding. A major example is the Connected Home over IP (CHIP) project that’s going on under the auspices of the Zigbee Alliance. It will be a standard, on track for publication in the first part of this year, that enables Zero-Touch Provisioning for the Smart Home.

Essentially, when a consumer buys any device certified as compliant, like a smart coffeemaker, that device has a hardware RoT protecting pre-loaded secured software and credentials. Out of the box, the consumer scans a QR code, presses a pairing button and the smart home network verifies the credentials and admits the device.

That’s it. It’s a really exciting initiative with wide support across the smart home ecosystem that we think will definitely move the needle.

Infineon Technologies www.Infineon.com

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Fundamentals of IoT Security

By Eric Heiser, u-blox

Faced with a constantly evolving landscape, an agile approach to security is required by developers of IoT ecosystems in order to respond rapidly to emerging threats.

A

s IoT applications become missioncritical, security is paramount. By their very nature, IoT ecosystems are vulnerable to security threats at multiple levels. Faced with a constantly evolving landscape, an agile approach to security is required by developers of IoT ecosystems in order to respond rapidly to emerging threats.

Organizations must decide whether to retain this scarce resource, with the associated investments in ongoing training, or to partner with external organizations that can ­provide the required support throughout the development cycle.

Both device manufacturers and ecosystem developers must have simple, scalable, and sustainable IoT security strategies in place to achieve short- and long-term business objectives.

Developers of IoT ecosystems must also demonstrate compliance with relevant regulations and standards through vetting by independent public bodies. Relevant standards include the Common Criteria for Information Technology Security Evaluation (ISO/IEC 15408); the US Federal Information Processing Standards Publications (FIPS PUBS); and the Baseline Security Certification (CSPN), operated by ANSSI, the national security agency of France. Within the EU, products, processes, and services are certified through the European Cybersecurity Certification process, which is owned by the European Network Information Security Agency. This process is based upon the success of CSPN

IoT security is undoubtedly a complex field requiring specialized security expertise.

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Security and Quality Assurance: The PDCA Process Existing Total Quality Management (TQM) processes in the software industry already address security issues. Futhermore, the Plan, Do, Check, Act (PDCA) process embodied in the ISO-27001 information security standard is well understood as a secure development methodology (Figure 1).

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Tampering, Repudiation, Information disclosure, Denial of service, and Elevation of privilege (STRIDE) methodology, developed by Microsoft security engineers, is a commonly used tool for this phase (Figure 2).

The output of this assessment is a document that forms the basis of an integrated risk management approach and is a key enabler of future compliance and formal certification.

and certificates that, once issued, are recognized throughout the Union.

FIGURE 1

The Plan, Do, Check, Act (PDCA) development process defined by the ISO-27001 information security standard is well understood throughout industry.

FIGURE 2

The STRIDE methodology was developed by Microsoft security engineers to model and asses cyber threats.

In addition to negotiating the complexities of the PDCA process, organizations developing secure IoT ecosystems must therefore also understand how and when to interact with the relevant standards bodies and vetting agencies.

Plan: Threat Modeling and Assessment As with any project, developing a secure IoT ecosystem begins with a robust plan, which should ensure that security issues are addressed as early as possible in the development cycle. The plan should identify business risks and high-priority assets requiring protection, and should also include a rigorous threat assessment and elaboration of the security measures required for effective risk mitigation.

Threat modelling and assessment is a key security practice, and the Spoofing, www.embedded-computing.com

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SAFETY & SECURITY STANDARDS

Do: Design the IoT Security Architecture The threat assessment findings must now be embodied in the design of the IoT solution’s security architecture. The scope of this design covers both hardware and software and, to ensure resilience to evolving cyber threats, designers must make certain that: › Any IoT device has a unique ID that cannot be cloned, laying the foundation for all other security functions. This Root of Trust (RoT) functionality enables all parties to trust the identity, authentication, communication, and data coming from the device. The RoT also provides the cryptographic hardware and software capabilities required to enable trusted functions, and API layers enable external applications to access these capabilities. › CPU, memory, and connectivity can’t be used for non-designated tasks, limiting the threat from hacker activities. › Privacy, confidentiality, and regulatory compliance are ensured by protecting the integrity of all data, whether static or in motion. › Decisions made using data from an IoT ecosystem are executed in a secure environment, safe from tampering and intellectual property theft. › Any commands sent to an IoT device (e.g. “inject insulin”, “open/close valve”, “apply brakes”, etc.) are validated as coming from a legitimate source.

This phase of the project is key to establishing an effective IoT security architecture and requires the use of a highly trained, expert resource. This resource is notoriously scarce within the industry and retention may be further complicated by the cyclical nature of product development: Security design is typically done once and then reused for an entire product family, meaning that in-house security experts may not be continuously utilized.

It may therefore make sense for many organizations to consider working with external partners, who cannot only provide the required security design expertise but can also offer advice and guidance throughout the end-to-end PDCA process.

Upon completion of the “Do” phase of the PDCA process, the secure architecture design is ready for penetration testing.

Check: Defend, Attack, Score To ensure that the device meets the security requirements of its target market, it must be tested for compliance or formal certification by an independent body, such as CSPN. Testing by an independent organization avoids the conflicts of interest that may exist with business-backed bodies and standards such as Common Criteria, ensuring the objectivity of testing.

Assessing an IoT device’s security level requires the use of accepted references and methodologies to assess its robustness against formally identified threats. This evaluation can be conducted using either a quantitative or a qualitative approach.

Attack scoring is a widely used quantitative method where the Evaluation Assurance Level (EAL) is refined with a score determined through a vetting process conducted by an independent security laboratory. The two commonly applied scoring mechanisms are either the Joint Interpretation Library methodology, used by CSPN, or the Common Vulnerability Scoring System, managed by the Forum of Incident Response and Security Teams (FIRST).

Qualitative evaluations, also conducted by independent security laboratories, test for security gaps within the device that would permit the success of high-probability, highimpact attacks. The degree of evaluation for this methodology is based on the level of expertise and the complexity of the tools that would be required to mount a realistic attack. This approach establishes a security or confidence level in the device, with

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Embedded Computing Design EMBEDDED WORLD | Spring 2021

QUALITATIVE EVALUATIONS, CONDUCTED BY INDEPENDENT SECURITY LABORATORIES, TEST FOR SECURITY GAPS WITHIN THE DEVICE THAT WOULD PERMIT THE SUCCESS OF HIGH-PROBABILITY, HIGH-IMPACT ATTACKS. the assigned level being reached when testing activities fail to reveal a gap for the defined attack.

A qualitative baseline evaluation is sufficient for most IoT products and this evaluation can be further simplified for products that are built on devices that have already been through a security evaluation process, such as u-blox’s range of cellular IoT modules. Certified modules such as these will have undergone extensive evaluations, simulating typical paths of attack and testing the embedded security of the devices against attacks including fault injections and side-channel analysis.

By integrating modules that have been tested to this level, developers gain the assurance that an attacker with physical access to the device will not be able to defeat the security countermeasures, cryptographic algorithms, private keys, and other security functionality.

Act: Sustaining Security Throughout the Lifecycle Following the planning, design, and evaluation stages, IoT device security must be deployed, scaled, and sustained throughout the device’s lifecycle.

Although software security implementations can suffice for low-threat, lowbusiness-value situations, devices used in high-value, high-exposure applications require a hardware RoT that has been provisioned at a trusted location during the production run. The security www.embedded-computing.com

software security through a tailored vulnerability and threat analysis, end-to-end security architecture consulting, and comprehensive pre-release testing.

The Security Solution As described, the security process can be simplified for solutions based on certified modules such as the u-blox cellular range. These modules integrate the Kudelski IoT security platform, which creates a chain of trust linking devices, data, IoT platforms, and applications, enabling users to manage all key IoT assets using simple APIs. The platform is comprised of three elements – a software or hardware RoT, a device-based security client, and a cloud or customer-premise-based security server. The pre-integrated components include features that enable the implementation of secure device designs and data for IoT applications. Users of the platform can create and operate a wide range of digital and physical assets, and ensure that security protections adapt to future threats.

FIGURE 3

Security organizations can assist companies with the PDCA process regardless of where they are in the development lifecycle.

challenges of large-scale IoT ecosystem deployments also demand the inclusion of features such as zero-touch provisioning, secure cloud connectivity, and power- and bandwidth-efficient key management.

Reducing the in-life exposure to security threats requires the collection and monitoring of large quantities of both internally- and externally-sourced data.

Although this can be a demanding task, it is critical to ensure the timely detection and remediation of threats.

Organizations without the necessary inhouse resources should seriously consider working with a trusted partner on this activity.

Engaging with External Support Throughout the Security Journey Many specialist security organizations, such as the one formed through a u-blox and Kudelski partnership, can provide expert security capabilities to support the PDCA workflow regardless of where you may be in the development process (Figure 3).

Designing an effective IoT security architecture is an essential but complex process requiring special expertise. The PDCA process is a well-established methodology that incorporates the necessary security testing and certification steps and, when properly applied, ensures the implementation of a robust IoT security architecture.

Organizations can choose to retain this scarce resource or engage with external providers, depending on the specifics of their product development cycles.

Eric Heiser joined the Product Center Cellular at u-blox AG in 2016. Prior to this position, he was Division Vice President & GM, Strategic Sales & Corporate Planning at Kyocera Communications Inc. for 8 years. Eric holds an MBA from the Marriott School of Business at BYU and a B.S. in Electrical Engineering from the University of Missouri, Rolla.

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MOTOR CONTROL

How to overcome the power versus heat dissipation challenge in Embedded Motor Control Systems

By Andrew Phillips, TDK-Micronas

Power and thermal dissipation are ongoing challenges for developers of embedded motor-control systems, as the increasing deployment of actuators in cars, the drive to reduce engine CO2 emissions, and increasing vehicle weight have resulted in ever-more integration and performance density. This article proposes a number of improvements in the motor control software and hardware environment using a stepper-motor actuator IC as an example, that aim to addresses these challenges.

I

n vehicles, motors and actuators are used in a wide range of applications from front grille shutters and adaptive headlights to door mirror adjusters. Motor control ICs, as the name suggests, control the performance of electric motors.

These devices are evolving to integrate all the necessary functions, such as voltage regulators, oscillators, watchdogs, flash memory, EEPROMs, ADCs, phase current controls, and motor drivers. This high level of integration enables a compact and smart actuator design within a single chip. The downside, however, is that all these increases in integration and performance density create heat.

In embedded motor control systems, where space is at a premium, engineers

22

are reaching their limits in terms of power dissipation and thermal management. But this challenge is not unbeatable; specific measures can help solve the power-heat ­dissipation problem.

FIGURE 1

A block diagram of the stepper motor actuator.

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MOTOR CONTROL

Establishing a Thermal Budget To establish the thermal budget, I examined a stepper motor actuator based on a TDK-Micronas HVC 4xyzF SDB-I v4.1 evaluation board, which uses a highly integrated motor control IC (Figure 1). The board is similar to a real-life application in terms of its structure and size.

The basic requirements for operating the actuator are shown in Table 1.

Ambient temperature (TA)

TABLE 1

-40°C to 85°C

Operating voltage (VBAT)

8 V to 16 V

Phase current (Iphase_RMS)

250 mA (0.250A)

Basic actuator operating requirements.

The maximum possible ambient temperature (TA) is calculated from the power dissipation to be expected in the IC (PV_IC), the thermal resistance between junction and ambient (RthJA), and the maximum permitted junction temperature (TJ). Here, the IC’s ambient temperature on the circuit board should be considered without any housing, though there may be one present. As a worst-case scenario, maximum values are applied: TA max. = TJ max. – PV_IC max. x RthJA max.

The total power dissipation converted in the IC is composed of the power dissipation from the motor drivers (PMotorDriver), as well as of the power dissipation of the CPU and the IC’s peripheral modules of the IC (PDDP): PV_IC max. = PMotorDriver max. + PDDP max.

The motor driver losses are calculated from phase current (IPhase_RMS) and the integrated half-bridges’ output resistance. For each of the two motor phases, the resistance of a high-side (RDS(ON)hs) and a low-side transistor (RDS(ON)ls) are considered. The switching losses for one PWM modulated transistor are approximated: Psw = 1/2 x U x I x (tr + tf) x fPWM The switching losses at 20 kHz PWM frequency, standard setting of the switching speed, and three PWM modulated transistors are represented by an additional power loss adder of 13%. For simplicity, I did not consider freewheeling losses separately.

As a worst-case scenario consideration, the motor is operated continuously, i.e., the effective phase current flows continuously. The motor driver losses are thus calculated: PMotorDriver max. = 2 x (IPhase_rms2 x (RDS(ON)hs max. + RDS(ON)ls max. x 1.13)) The losses from the CPU and peripherals are determined from the current consumption of the IC (IDDP) and the given operating voltage (VBAT). For simplification, the voltage drop at any polarity protection that may be present is ignored, representing an additional safety margin.

Junction Temperature (TJ max.)

Current Consumption [Without Motor Drivers] (IDDP max.)

50°C 5 mA (0.035A)

ON Resistance of the Motor Driver’s High-Side (RDS(ON)hs max.)

2.8 Ω

ON Resistance of the Motor Driver’s Low-Side (RDS(ON)ls max.)

2.8 Ω

TABLE 2

These datasheet parameters can be used to calculate the motor’s maximum power dissipation.

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MOTOR CONTROL

With the help of the datasheet maximum parameters in Table 2 (page 23), the maximum power dissipation is calculated: PDDP max. = IDDP max. x VBAT max.

FIGURE 2 A simplified thermal model of the TDK HVC 4xyzF SDB-I v4.1 evaluation board.

PDDP max. = 0.035 A x 16 V = 0.56 W This enables us to calculate the maximum motor losses: PMotorDriver max. = 2 x (IPhase_rms2 x (RDS(ON)hs max.+ RDS(ON)ls max.)) x 1.13 PMotorDriver max. = 2 x (0.252A2 x (2.8 Ω + 2.8 Ω)) x 1.13 = 0.791 W In turn, we can then calculate the total power dissipation converted in the IC: PV_IC max. = PMotorDriver max. + PDDP max.

PV_IC max. = 0.791 W + 0.56 W = 1.351 W A simplified thermal model of the actuator shows that this is limited to the primary thermal resistances, which should be enough to consider the steady state (Figure 2).

The starting point is a circuit board similar to the circular evaluation board, made from FR4 material (Figure 3). It is 1.6 mm thick and has a diameter of 40 mm. It has two signal layers, a 35 µm copper layer, a 3 x 3 thermal via array, and a copper surface on the bottom side below the ePad, which is of an approximated area of 0.75 cm2.

This circuit board achieves an RthJA max. of about 32 K/W. Thus, we can calculate the maximum possible ambient temperature of the circuit board: TA max. = TJ max. – PV_IC max. x RthJA max.

TA max. = 150°C – (1.351 W × 32 K/W) = 106.8°C

The motor losses (PMotor) are only depicted through the copper losses, which constitute the majority of losses to keep things simple. The resistance of the motor phases, RPhase, is assumed to be 12 Ω. We can, therefore, calculate the power dissipation of the motor: PV_Motor = 2 x (IPhase_rms2 x RPhase) PV_Motor = 2 x (0.2502 A2 x 12 Ω) = 1.5 W With this information, we can then calculate the total power dissipation (Ptot) in the housing: Ptot = PV_IC max. + PV_Motor = 1.351 W + 1.5 W = 2.851 W The temperature gradient (ΔT) across the actuator housing is thus determined by: ∆TAH = Ptot W x RthAH K/W ∆TAH = 2.851 W x 11 K/W = 31.36 K If this temperature gradient is added to the actuator’s maximum specified ambient temperature (85°C), this results in an internal housing temperature of 116.4°C. There is a gap of 10 K between the previously calculated maximum allowable ambient temperature of the circuit board (106.8°C), without motor and housing, and the housing’s internal temperature (116.4°C), which has now been determined. Appropriate action to close this gap, therefore, needs to be taken.

FIGURE 3 The TDK HVC 4xyzF SDB-I v4.1 evaluation board.

Usually, the circuit board and motor are positioned closely together in a housing.

Therefore, to calculate the temperature within the housing, the motor’s power dissipation must also be considered. I used a plastic housing with a measured thermal resistance (RthAH) of 11 K/W.

24

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working on background tasks; slowing the clock speed during this time will significantly reduce the current consumption.

FIGURE 4 Current consumption of the TDK HVC 4223F MCU standardized to 20 MHz. The line indicates current savings.

A good compromise is to choose a 5 MHz CPU clock speed for background tasks. A quarter of the maximum clock speed, which is 20 MHz, achieves a current savings of 38 percent (Figure 4).

The total current consumption (without motor drivers), therefore, is lowered by 60 percent × 38 percent = 22.8 percent.

Use Only When Needed The most effective way to reduce power dissipation is not to let it occur at all. All the peripheral modules, therefore, should only be active when required. By far, the most significant consumers of power in the evaluation board are the ADC (8 mA), BEMFComparator (1.3 mA), and Enhanced PWM (1.1 mA).

While the motor is running, the BEMFC and EPWM must be active to create a holding torque even during dwell times. In contrast, the ADC is not always required and, as it is the greatest consumer of power, a significant savings can be attained by “on demand” operation.

In our stepper motor application, the ADC measures the back electromotive force voltage to identify overload and the step loss connected with it. Assuming the speed is 1000 full steps per second, the ADC is active 1000 times per second, or every milli­ second. A conversion time of 1 µs and the use of eight sequential conversions per event, and factoring in warm-up and synchronization times, results in a total ADC active time of 20 µs per full step.

Therefore, the average active time (TA) can be calculated as follows: TA= Ton/Tperiod = (20 µs)/(1000 µs) = 0.02 From this, we can calculate the average current consumption (IADC_av.) of the ADC: IADC_av. = 8 mA × 0.02 = 0.16 mA The current consumption of the module can thus be lowered by 7.84 mA, which corresponds to a power dissipation reduction of 7.84 mA × 16 V = 125.4 mW. Optimizing Clock Speed In embedded actuators, software is generally event-controlled, where actions are triggered by interrupts. The CPU is mostly involved with background tasks and waiting for new events. These can be internal events, such as a timer interrupt, or external events, such as over- or under-voltage interrupts.

Dynamically slowing the CPU clock speed during non-time-critical background tasks reduces the current consumption. As soon as an interrupt arises, the CPU can automatically switch over to the maximum clock speed, and the interrupt service routine can be processed at maximum speed. At the end of the interrupt service routine, the software switches back to the lower clock speed.

For typical stepper motor software, the CPU spends on average 40 percent of its time performing interrupt service routines. This means that 60 percent of the time is spent www.embedded-computing.com

Typical current consumption of the HVC 4223F MCU, with all peripheral modules switched off (where fYS = fCPU = 20 MHz), is 15 mA. Therefore, 15 mA × 22.8 percent = 3.42 mA can be saved.

This corresponds to a power dissipation reduction of 3.42 mA × 16V = 54.72 mW. Lowering Switching Losses The switching losses in the motor drivers are caused by voltage, current, and switching time. As external requirements determine both voltage and current, only the switching time can be varied. Here, we can set the switching speeds in three stages. In the fastest setting, the switching time can be more than halved compared with the slowest setting. Reducing the switching losses adder from 13 percent to 5 percent of the motor driver losses are calculated: PMotorDriver max. = 2 x (IPhase_rms2 x (RDS(ON hs max. + RDS(ON)ls max.)) x 1.05 PMotorDriver max. = 2 × (0.250² A² x (2.8 Ω + 2.8 Ω)) x 1.05 = 0.735 W As the original power consumption calculation was 0.791 W, this corresponds to a power dissipation reduction of 56 mW. However, note that careful consideration towards the electromagnetic compatibility must be checked, as this staging technique could influence individual cases.

PCB Optimization The ePad on the bottom of the QFN package (Figure 5, page 26) takes the primary heat flow vertically. The heat must conduct from underneath the chip, through the circuit board to the bottom layer of the PCB. Therefore, it is essential to make the copper surface on the bottom layer as large as possible to ensure horizontal distribution and effective heat removal.

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MOTOR CONTROL

Because standard vias have the risk of solder outflow, we recommend that they are filled with resin and capped with copper. We also recommend using 4 x 4 or 5 x 5 via arrays. Any more will only lead to a small reduction of the thermal resistance (Figure 6). If the demands on the mechanical stability permit, you can also reduce the thickness of the circuit board, as the thermal resistance in the vertical direction is directly proportional to the circuit board thickness.

Further improvement in heat dissipation can be attained by maximizing the ground plane connected to the ePad. Through the layout optimization, the copper surface can be doubled to approximately 1.5 cm², which reduces the thermal resistance by 2 K/W. Com­ pared with the original two-layer circuit board, which has a thermal resistance of 32 K/W, these optimizations reduce it down to 26 K/W. If costs are not a concern, you can use a four-layer circuit board, which lowers the thermal resistance down to 20 K/W by connecting the ePad to additional interior layer ground planes.

It is also cheaper, but less effective, to double the copper layer thickness of the exterior layers to 70 µm, which gives a reduction of 1 to 2 K/W on this circuit board. However, if you do decide to take this option, do so at an early stage as the thicker copper layer impacts the layout of the signal layers. This is because the minimum track width and distances must almost be doubled when doubling the copper thickness.

Maximum Headroom By optimizing the software, the power dissipation of the IC could be reduced by 238.1 mW. Optimization measures on the circuit board reduce the thermal resistance (RthJA) by 6 K/W. With these new numbers, we can re-calculate the maximum permitted ambient temperature of the circuit board.

TA max. = 150°C – (1.351 W – 0.2381 W) x (32 – 6) K/W = 121.0°C Through simple and cost-effective measures, a 14.2 K improvement could be

26

FIGURE 5 A QFN40 package with exposed pad (ePad).

FIGURE 6 Rth of the vias standardized on a 2 x 2 via.

attained compared with the initial permitted maximum ambient temperature of the circuit board of 106.8°C. The new calculation of the temperature gradient along the housing with lowered power dissipation results in: ∆TAH = (2.851 W – 0.2381 W) x 11 K/W = 28.74 K This corresponds to an improvement of 2.62 K compared with the initial temperature gradient of 31.36 K. Added to the required maximum ambient temperature of the actuator (85°C), the new internal housing temperature results in 113.7°C. This closes the gap, with a comfortable headroom of 7.3 K. Conclusion Using cost-effective optimizations to the software and circuit board can improve an application’s thermal budget and give developers of embedded motor control systems plenty of headroom. Importantly, these improvements can be achieved on any embedded motor control system.

The TDK-Micronas HVC flex servo-drive family enables the cost-effective development of high-performance and compact embedded motor control systems. Powered by a 32-bit Arm Cortex-M3-based CPU, it addresses the power versus heat dissipation challenge. Besides the two-phase bipolar-stepper motor that I used in the calculation, the microcontroller, which integrates all the necessary functions, is equally suitable for brushless DC (BLDC) motors with up to three phases, and brushed DC (BDC) motors.

Andrew Phillips is Automotive Sales Manager at TDK-Micronas. He has served in a variety of roles at several major semiconductor companies over the past 30 years, including applications support, market development, and sales. Andrew received a BSEE degree from Oakland University.

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MOTOR CONTROL

Controlling Output Modules with Full Isolation from the Microcontroller

By Thomas Brand, Analog Devices

Whether in buildings or on production floors, programmable controllers are needed everywhere today to regulate various processes, machines, and systems. This involves programmable logic controllers (PLCs) or distributed control system (DCS) modules to which the devices are connected.

T

o control these devices, the PLCs and DCS modules usually have output modules with current outputs, voltage outputs, or a combination of both. Industrial control modules cover the standard analog output voltage and current ranges of ±5 V, ±10 V, 0 V to 5 V, 0 V to 10 V, 4 mA to 20 mA, and 0 mA to 20 mA. Especially in the industrial sector, galvanic isolation of the microcontroller and the output peripherals is often required.

Classic solutions provide for a discrete design to convert the digital signals from the microcontroller to analog signals or provide the different analog outputs, and to realize the galvanic isolation. However, compared with integrated solutions, a discrete design exhibits many disadvantages. For example, the large number

28

of components results in high system complexity, a large board size, and high costs.

Additional characteristics such as short-circuit capability or even fault diagnostics bring these drawbacks to the fore.

Integrated Control A better solution is to integrate as many functions as possible on a single chip, as is done, for example, with the AD5422, a high-precision, 16-bit DAC from Analog Devices Inc. (ADI). In addition to the digital-to-analog conversion, it also offers a fully integrated programmable current source and a programmable voltage output, and thus meets the requirements of industrial process control applications.

Figure 1 shows an example circuit for fully isolated control of an analog output stage of an output module. It is especially suitable for PLCs and DCS modules in process control applications requiring standard current outputs of 4 mA to 20 mA and unipolar or bipolar output voltage ranges. This circuit is based on the AD5422, a highprecision 16-bit digital-to-analog converter (DAC) from ADI, in combination with the ADuM1401 quad-channel digital isolation module.

The outputs of the 16-bit DAC are configurable via a serial peripheral interface (SPI).

The module also has integrated diagnostic functions, which can be useful in industrial environments. The required insulation resistance between the microcontroller

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MOTOR CONTROL

and the DAC is provided by the isolation module, whose four channels are used for the SPI connection to the DAC: three channels (LATCH, SCLK, and SDIN) transmit the data and the fourth channel (SDO) receives the data.

Industrial-Grade EMC Especially in industrial applications, robust outputs that are resistant to high interference voltages must be provided. The requirements for robustness are set forth in standards such as IEC 61000, which specifies, for example, the requirements with respect to electromagnetic compatibility (EMC).

FIGURE 1

This simplified example circuit for isolated control of an analog output stage uses the Analog Devices AD5422 16-bit DAC and the ADuM1401 quad-channel digital isolation module.

FIGURE 2

IEC 61000-compliant protective circuits for the outputs of the AD5422.

To comply with these standards, it is necessary to have additional external protective circuits at the outputs. One possibility for protective circuitry is shown in Figure 2.

The current output (IOUT) can be selectively programmed in either the 4 mA to 20 mA or 0 mA to 20 mA range. The voltage output is provided via the separate VOUT pin, which can be configured for voltage ranges of 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V. The overrange for all voltage ranges is 10 percent. Both analog outputs have short-circuit and open-circuit protection, and can drive capacitive loads of up to 1 µF and inductive loads of up to 50 mH. The DAC requires an analog power supply (AVDD) in the range of 10.8 V to 40 V. For the digital supply voltage (DVCC), 2.7 V to 5.5 V is required. Alternatively, DVCC can serve as a supply pin for other components in the system or as a termination for pull-up resistors.

For this, the DVCC_SELECT pin should be floating and the internal 4.5 V LDO regulator voltage should be applied to the DVCC pin. The maximum available supply current is 5 mA. In the circuit shown, the DVCC is used to supply the galvanically isolated side of the ADuM1401.

High-precision conversion results are obtained from the 16-bit DAC using the www.embedded-computing.com

ADR4550 external reference voltage. This is a high-precision, low-power, low-noise voltage reference with a maximum initial accuracy of 0.02 percent, solid temperature stability, and low output noise.

Such circuits are especially suitable for output modules of ubiquitous PLCs or DCS modules that provide both current and voltage outputs and must comply with EMC standards such as IEC 61000.

Thomas Brand began his career at Analog Devices in Munich in 2015 as part of his master’s thesis. After graduating, he was part of a trainee program at Analog Devices. He currently supports large industrial customers in Central Europe and also specializes in the field of Industrial Ethernet.

References:

1. Analog Devices Inc. (ADI). (2018, February). 16-Bit, Fully Isolated Output Module Using the AD5422 Single-Chip Voltage and Current Output DAC and the ADuM1401 Digital Isolator. Retrieved from https://www.analog.com/media/en/technical-documentation/ application-notes/an-1519.pdf.

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2021 EMBEDDED WORLD

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Infineon Technologies www.infineon.com

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 +49 89 234 65555 https://www.linkedin.com/company/infineon-technologies/mycompany/

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Embedded Computing Design EMBEDDED WORLD | Spring 2021

www.embedded-computing.com

Samtec COM-HPC® Interconnect Solutions The development of the COM-HPC® specification exceeds the demand for high-speed performance in embedded computers. COM-HPC coexists with the COM Express® specification, providing the scalability and enhanced performance for next-gen embedded system design.

COM-HPC offers system and interface flexibility by adopting a pair of 400 pin connectors (800 pins total) based on Samtec’s AcceleRate® HP High-Performance Arrays. Samtec COM-HPC interconnect solutions support existing and future interfaces such as PCIe® 5.0 (32 GT/s) and up to 100 Gb Ethernet.

The female Module Receptables are employed at a standard height. The male Carrier Plugs vary to allow for either a 5mm or 10mm stack height.

Depending on the application, the connector pinouts are optimized for Client or Server modules as defined in the COM-HPC specification.

FEATURES Ą High-performance, flexible open-pin-field array Ą High-speed PCIe® 5.0 (32 GT/s) and 100 Gb Ethernet capable Ą 400 pin BGA mount Ą 4 rows x 100 columns Ą 2.2 / 2.4 / 2.2 mm row pitch Ą 0.635 mm pitch Ą Up to 300 W at 11.4 – 12.6 Volts Ą Module Receptacle J1/J2 – Samtec ASP-209946-01 Ą Carrier Plug P1, P2 (5 mm Stack) – Samtec ASP-214802-01 Ą Carrier Plug P1, P2 (10 mm Stack) – Samtec P/N ASP-209948-01

Applications • • • • • •

Datacom & Telecom Embedded Edge Servers Industrial Medical Imaging 5G Wireless Infrastructure 5G Connected Vehicles

ASP-209948-01

ASP-214802-01 ASP-209946-01

BGA mount increases density and performance

Samtec, Inc.

www.samtec.com/COMHPC www.embedded-computing.com

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5 mm Stack

10 mm Stack

Module Receptacle ASP-209946-01

Module Receptacle ASP-209946-01

Carrier Plug ASP-214802-01

Carrier Plug ASP-209948-01

COMHPC@samtec.com www.linkedin.com/company/samtec-inc

 +1-812-944-6733 @samtecinc

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Embedded Computing Design EMBEDDED WORLD | Spring 2021

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Embedded Computing Design

PICMG COM-HPC

Embedded Computing Design

PICMG COM-HPC

New design options on COM-HPC and COM Express The first COM-HPC Client size A module and a next generation COM Express Compact Computer-on-Module provides engineers the choice to further scale the performance of their existing systems or develop the next generation of products utilizing COM-HPC’s broader array of interfaces. OEMs will benefit from the substantial performance improvements as well as communication enhancements that the new modules based on 11th Gen Intel® Core™ processors deliver to the highend computing sector. Typical applications can be found in many high-end solutions, from embedded systems and edge computing nodes to network hubs, and local fog data centers to core network appliances, as well as ruggedized central cloud data centers for critical government applications.

FEATURES Ą conga-HPC/cTLU COM-HPC Client Size A module and conga-TC570 COM Express

Compact module will be available with new scalable 11th Gen Intel Core processors.

Ą Both modules are the first to support PCIe x4 in Gen 4 performance to connect

Ą Ą Ą Ą

congatec

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peripherals with massive bandwidth. In addition, designers can leverage 8x PCIe Gen 3.0 x1 lanes.

COM-HPC module offers latest 2x USB 4.0, 2x USB 3.2 Gen 2, and 8x USB 2.0, the COM Express module offers 4x USB 3.2 Gen 2 and 8x USB 2.0.

COM-HPC modules offer 2x 2.5 GbE for networking, whereas COM Express modules execute 1x GbE, with both supporting TSN. Sound is provided via I2S and SoundWire in the COM-HPC version, and HDA in the COM Express modules.

Comprehensive board support packages are provided for all leading RTOS’s, including hypervisor support from Real-Time Systems as well as Linux, Windows and Chrome.

sales-us@congatec.com

 www.linkedin.com/company/congatec

www.congatec.us

 858-457-2600 twitter.com/congatecAG



Security

ChipWhisperer-Pro (CW1200) The ChipWhisperer-Pro (CW1200) is purpose-built for power analysis AND fault injection work, perfect for analyzing your designs against advanced security threats. The ChipWhisperer-Pro has been designed to remain compatible with existing ChipWhisperer-Lite interfaces but adds new features thanks to a more powerful internal FPGA (almost 5x larger), a larger internal buffer (98 Ksamples compared to 24 Ksamples), the addition of a streaming mode for huge captures at slower speeds, real-time analog pattern matching triggers for working with real FEATURES hardware targets, and more. It uses a unique synchronous capture technology to Ą Complete Side Channel Power Analysis & Fault Injection kit provide well-aligned power traces. The open-source nature means that you can including analysis tool for power analysis, clock glitching, and even add custom features in the FPGA. voltage glitching with 32-bit and 8-bit example targets.

The ChipWhisperer-Pro kit comes with all the accessories that you need, including Ą Open-source ChipWhisperer software supports analysis & data recording.

AVR and STM32F3 (Arm Cortex-M4) targets, simple differential and magneticfield probes, voltage translators, analog filters, and a waterproof storage case. Ą Power analysis examples include power analysis on AES, password comparisons, and RSA (with ECC coming soon).

Using our free library of Jupyter notebooks, you can learn how DPA and fault injection work, how to break password checks, and more! Ą Fault injection (glitching) examples include password bypass, memory dumping, Differential Fault Analysis (DFA) on RSA & AES. The ChipWhisperer project is an open-source toolchain for embedded security research. All the targets and capture hardware are supported by a Python-based Ą ChipWhisperer-Pro capture box supports clock-synchronization for perfect sample alignment, with 10-bit 105 MS/s capture. capture application. The open-source nature means you can modify for your specific needs; whether you are developing your own algorithms or want to perform Ą Real-time analog pattern matching trigger allows triggering on parts of analog waveform. validation on a proprietary target, ChipWhisperer has you covered.

For more information: https://www.newae.com/products/NAE-CW1200

NewAE Technology Inc. www.newae.com

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sales@newae.com

 www.linkedin.com/company/newae-technology-inc-

Embedded Computing Design EMBEDDED WORLD | Spring 2021

 902-999-8869

 @newaetech

www.embedded-computing.com

C-Trust Intellectual Property (IP) is the core of a company’s business, and an embedded application can contain several man years of development efforts. But how are you protecting that investment? If the IP is not secured in a satisfactory way, it is at risk of becoming stolen, counterfeited and copied, causing severe financial damage and posing an existential threat to the company. By applying foundation security measures such as encrypting the codebase and implementing secure manufacturing, companies can substantially reduce this risk. C-Trust is a security development tool that works as an extension to the development toolchain IAR Embedded Workbench and enables you to easily protect an existing or new application.

settings for providing the application with a baseline protection against illegal access, counterfeiting and copying.

C-Trust integrates security features into IAR Embedded Workbench and includes Preconfigured Security Contexts that automatically include all the necessary security and encryption

Ą Automatically encrypted code

IAR Systems www.iar.com

www.embedded-computing.com

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C-Trust offers support for a wide range of devices, including Arm-based MCUs from STMicroelectronics, Renesas and NXP, as well as the Renesas RX MCU family devices, enabling you to choose the right MCU for the security and functional needs of your application. In addition, support for the vast majority of MCUs can be achieved through the use of Hardware Abstraction Layer (HAL).

FEATURES Ą Integrated with IAR Embedded Workbench Ą Preconfigured Security Contexts included

info@iar.com www.linkedin.com/company/iar-systems/

 650-287-4250 @iarsystems

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Embedded Computing Design EMBEDDED WORLD | Spring 2021

37

Embedded Computing Design

Security

Embedded Computing Design

Storage

®

Solid State Storage and Memory

Industrial-Grade Solid State Storage and Memory Virtium manufactures solid state storage and memory for the world’s top industrial embedded OEM customers. Our mission is to develop the most reliable storage and memory solutions with the greatest performance, consistency and longest product availability.

Industry Solutions include: Communications, Networking, Energy, Transportation, Industrial Automation, Medical, Smart Cities and Video/Signage.

StorFly® SSD Storage includes: M.2, 2.5", 1.8", Slim SATA, mSATA, CFast, eUSB, Key, PATA CF and SD.

Features

Classes include: MLC (1X), pSLC (7X) and SLC (30X) – where X = number of entire drive-writes-perday for the 3/5-year warranty period.

• 22 years refined U.S. production and

Memory Products include: All DDR, DIMM, SODIMM, Mini-DIMM, Standard and VLP/ULP. Features server-grade, monolithic components, best-in-class designs, and conformal coating/under-filled heat sink options.

New! XR (Extra-Rugged) Product Line of SSDs and Memory: StorFly-XR SSDs enable multi-level protection in remote, extreme conditions that involve frequent shock and vibration, contaminating materials and/or extreme temperatures. Primary applications are battlefield technology, manned and unmanned aircraft, command and control, reconnaissance, satellite communications, and space programs. Also ideal for transportation and energy applications. Currently available in 2.5" and Slim-SATA formats.

Include: custom ruggedization of key components, such as ultra-rugged connectors and screwdown mounting, and when ordered with added BGA under-fill, can deliver unprecedented durability beyond that of standard MIL-810-compliant solutions.

XR-DIMM Memory Modules have the same extra-rugged features as the SSDs, and include heatsink options and 30μ" gold connectors. They also meet US RTCA DO-160G standards.

Virtium

www.virtium.com

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sales@virtium.com www.linkedin.com/company/virtium

Embedded Computing Design EMBEDDED WORLD | Spring 2021

• Broad product portfolio from latest technology to legacy designs 100% testing

• A+ quality – backed by verified yield, on-time delivery and field-defects-per-million reports • Extreme durability, iTemp -40º to 85º C • Industrial SSD Software for security, maximum life and qualification • Longest product life cycles with cross-reference support for end-oflife competitive products • Leading innovator in small-formfactor, high-capacity, high-density, high-reliability designs • Worldwide Sales, FAE support and industry distribution

 949-888-2444 twitter.com/virtium

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www.embedded-computing.com

BY ENGINEERS, FOR ENGINEERS In the rapidly changing technology universe, embedded designers might be looking for an elusive component to eliminate noise, or they might want low-cost debugging tools to reduce the hours spent locating that last software bug. Embedded design is all about defining and controlling these details sufficiently to produce the desired result within budget and on schedule.

Embedded Computing Design (ECD) is the go-to, trusted property for information regarding embedded design and development.

embedded-computing.com

Industrial SSDs and Memory for the Interconnected World

Stability and Security, Now More Important than Ever As our interconnected world emerges from challenging times, we will see ever-increasing demands on industrial-embedded ecosystems across the globe.

In its third decade of innovation and with a passion for servicing its customers, Virtium continues supporting the ever-growing storage and memory demands in Industrial Automation, NetComm, Transportation and Defense markets. With each day of global recovery and new growth, our customers’ success has never been more important.

Visit us today at www.virtium.com to learn more about our industrial-grade solid-state storage and memory solutions.

®

Solid State Storage and Memory