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International Journal of VLSI Design and Technology

International Journal of VLSI Design and Technology is a comprehensive journal that covers all aspects of VLSI technologies and their integration into recent technologies that are the focus of ongoing research. Journal has a wider scope including all major advancement in the technology and design that are related to VLSI. All articles presented here are peer-reviewed and are of good quality.

Focus and Scope of the Journal ! CMOS technologies ! Basic MOS models, spice models ! Frequency response stability and noise issues in amplifiers ! CMOS analog blocks: current sources and voltage references ! Differential amplifier op-amp and ota design ! Frequency synthesizers and phased lock-loop ! Non-linear analog blocks: comparators, charged-pump circuits and multipliers ! Data converters ! Analog interconnects and analog testing and layout ! 12 low voltage and low power analog ! Electronic design automation

International Journal of VLSI Design and Technology is published twice a year (bi-annual) in India by JournalsPub is an imprint of Dhruv Infosystems Pvt. Ltd. The outlooks stated in the articles do not essentially reflect of the publisher. The publisher does not endorse the quality or value of the advertised/sponsored products described therein. Please consult full prescribing information before issuing a prescription for any products mentioned in this publication. No part of this publication may be reproduced, stored in retrieval or transmitted in any form without written permission to the publisher. To cite any of the material contained in this journal, in English or translation, please use the full English reference at the beginning of each article. To reuse any of the material, please contact JournalsPub (info@journalspub.com).

PUBLICATION MANAGEMENT TEAM

Chairman Mr. Puneet Mehrotra Managing Director, JournalsPub, New Delhi

INTERNAL MEMBERS

Associate Manager Hidam Renubala

Commissioning Editors Ankita Singh

Priyanka Garg

Akanksha Marwah

Chhavi Goel

Deepika Bhadauria

Shrawani Verma

EDITORIAL BOARD MEMBERS Dr. Angsuman Sarkar, Kalyani Govt. Engg. College, Kalyani, India

Dr. Swapnadip De, Assistant Professor, Department of Electronics and Communication Engineering Meghnad Saha Institute of Technology, India

Prof.Dr. Ramakrishnan S, Dr.Mahalingam College of Engineering & Technology, India

Dr. Michael Loong Peng Tan Universiti Teknologi Malaysia (UTM), Malaysia

Dr. Ram Mohan Mehra Professor, Department of Electronic Science, University of Delhi South Campus India

Professor J N Roy IIT-Kharagpur, India Balakrishnan Govindan Nair Kollamala Principal, College of Engineering, Munnar, India

Dr. Huang Mingzhi Associate Professor, Department of Water Resources and Environment, Sun Yat-sen University, China

Dr. V. Balaji Bahir Dar University,Bahir Dar, Ethiopia, South Africa

Mr. Vijay R Wadhankar Rtmnu University, India

Mr. Mayank Chakraverty Member of IBM Semiconductor Research & Development Center, India

Shipra Suman Universiti Teknologi PETRONAS, Malaysia

Dr. Seyed Feraydune Kashefi Khavaran Higher-education Institute, Iran

Dr. Saeid Zoghi Department of Applied Chemistry, Shahrood Azad University, Shahrood, Iran

Nitin Kathuria ECE, ITS Engg College, G. Noida, Uttar Pradesh, India

Dr. Santosh Kumar Agrahari Poornima University, Jaipur, India

From the Editor's Desk Dear Readers, We would like to present, with great pleasure, the inaugural volume of a new scholarly journal, International Journal of VLSI Design and Technology. This journal is part of the VLSI Design and Technology, and is devoted to the scope of present Electronics issues, from theoretical aspects to application-dependent studies and the validation of emerging technologies. This new journal was planned and established to represent the growing needs of International Journal of VLSI Design and Technology as an emerging and increasingly vital field, now widely recognized as an integral part of scientific and technical investigations. Its mission is to become a voice of the Electronics and Telecommunication Engineering community, addressing researchers and practitioners in this area. The core vision of International Journal of VLSI Design and Technology in JournalsPub is to propagate novel awareness and know-how for the profit of mankind ranging from the academic and professional research societies to industry practitioners in a range of topics in Electronics and Telecommunication Engineering in general. Journals Pub acts as a pathfinder for the scientific community to published their papers at excellently, well-time & successfully. International Journal of VLSI Design and Technology focuses on original high-quality research in the realm of CMOS technologies, Basic MOS Models, SPICE Models, Frequency response, stability and Noise issues in amplifiers, CMOS analog blocks: Current Sources and Voltage references, Differential amplifier, OPAMP and OTA design, Frequency Synthesizers and Phased lock-loop, Non-linear analog blocks: Comparators, Charged-pump circuits and Multipliers, Data converters, Analog Interconnects and Analog Testing and Layout, 12 Low voltage and Low power Analog, Electronic design automation. The Journal is intended as a forum for practitioners and researchers to share the techniques of Electronics and Telecommunication Engineering and solutions in the area. Many scientists and researchers have contributed to the creation and the success of the Electronics and Telecommunication Engineering community. We are very thankful to everybody within that community who supported the idea of creating an innovative platform. We are certain that this very first issue will be followed by many others, reporting new developments in the field of VLSI Design and Technology. This issue would not have been possible without the great support of the Editorial Board members, and we would like to express our sincere thanks to all of them. We would also like to express our gratitude to the editorial staff of JournalsPub, who supported us at every stage of the project. It is our hope that this fine collection of articles will be a valuable resource for Electronics and Telecommunication Engineering readers and will stimulate further research into the vibrant area of Electronics and Telecommunication Engineering. Puneet Mehrotra Managing Director

Contents 1. A Review of Subthreshold Surface Potential for Single Gate Dual Material Double Halo MOSFET Swapnadip De, Aditi Kumari, Poulami Dutta, Ishita Gupta, Mainak Bhattacharya

2. DG-MOSFET Cascode Self Biasing Ota and LPF Performance Analysis Based on Gain, Bandwidth Shikha Soni

3. Conjunction of Spin â&#x20AC;&#x201C;RAM Technology in FPGA Circuits Shubham Rastogi, Monika Kathuria, Pankaj Sharma

4. Model Order Reduction of Continuous Large Scale Systems: A Conglomerating Approach Ankit Sachan, Manish Kumar Sharma, Deepak Parashar

5. Analysis of Device Parameters Variation on SRAM Cell for High Performance Memory Design Farhan Aziz, Vishal Lal Goswami, Ashutosh Dubey, Ranjeet Singh

6. FOG Computing: A Novel Perception to Minimize Attacks & Provide Security in Cloud Computing Environment Pooja, Yashpal Singh, Sonia Chaudhary

7. Review on Raspberry Pi Technology Amandeep Kaur, Yashpal Singh, Sonia Chaudhary

International Journal of VLSI Design and Technology Vol. 2: Issue 1

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A Review of Subthreshold Surface Potential for Single Gate Dual Material Double Halo MOSFET Swapnadip De*, Aditi Kumari, Poulami Dutta, Ishita Gupta, Mainak Bhattacharya Department of Electronics Communication Engineering, Meghnad Saha Institute of Technology, Nazirabad, Kolkata, India

Abstract An analytical model for the sub thershold surface potential in a short channel MOS transistor is developed by solving a pseudo-2D Poisson’s equation, formulated by applying Gauss’s law around a rectangular box in the channel depletion region. This model uses a physcially based non-uniform depletion layer depth along the channel incorporating the role of channel length (L) and junction depth (xj) , substrate doping (Na), oxide thickness (tox), and bias voltages in determining the surface potential. It is functionally one dimensional but provides a two dimensional accuracy. Using an analytical expression for subthreshold surface potential model of the device is devoloped here. Keywords: analytical modelling, Gauss’s law, MOSFET, subthreshold surface potential

INTRODUCTION For development of VLSI technology, channel length of MOSFET is decreased so electric field is increased and various effects are come out for short channel devices as Hot Electron effect,DIBL. To solve hot electron effect we will use the channel engineering technique which is halo doping process in conventional MOSFET. When channel length of Double gate MOSFETs decreases then effects on threshold voltage roll-off and the undesirable short channel effects (SCEs). The threshold voltage will decrease for decreasing channel length. The minimum acceptable channel length is primarily determined by the threshold voltage rolloff. The threshold voltage roll-off can be reduced where the threshold voltage increases with decreasing channel length, by locally raising the channel doping to the drain or source junctions. The high doping concentration in the channel near source/drain junctions has been

implemented via engineering, called implants.

lateral channel halo or pocket

In other side the gate engineering technique used here is the dual metal gate technology.Here for double material gate two laterally contacted materials of different work functions are used. In the channel of MOSFET two different materials M1 and M2 with lengths L1 and L2, and with work functions are Φ1 and Φ2 respectively, contacted laterally are used as the gate. The overall effective channel length L=L1+L2 is defined as the distance from the source-channel metallurgical junction to the drain-channel metallurgical junction. The work function of the metal gate 1 (M1) is greater than that of metal gate 2 (M2), that is, Φ1> Φ2 for n-channel MOSFET .This gives rise to a step change of the surface potential profile at the point where M1 and M2 are contacted. A higher flat-band voltage corresponding to the gate

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International Journal of VLSI Design and Technology Vol. 2: Issue 1

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DG-MOSFET Cascode Self-Biasing Ota and LPF Performance Analysis Based on Gain, Bandwidth Shikha Soni* Department of VLSI Design, Hindustan College of Science and Technology, Sharda Group of Institutions, Agra, Uttar Pradesh, India Abstract In today’s modern electronic era, analog integrated circuits have been widely adopted for high frequency applications. Operational transconductance amplifiers (OTAs) are considered to be promising as the building blocks for filters, oscillators at high frequencies. OTA-C filters are one of the most widely used continuous time filters because they are fast, enable low-power operation and tuning of the filter characteristics at higher frequencies. Double gate MOSFET is new device which shows improved performance and have ability to tackle problems of nanometer era. Double gate MOSFET as four terminal device is very suitable to design analog circuits. In independent driven mode, back gate is used to provide analog tunability of circuits along with gain in terms of area and power dissipation. In the present paper, the study of double gate MOSFETs and its suitability to designing high gain and wide bandwidth OTA. The proposed DG-MOSFET based MOSFET based OTA is used to implement second order low pass filter. Keywords: DG-MOSFET, MOSFET, LPF (low pass filter), OTA-C (operational transconductance amplifier) Tool- Tanner EDA 13.0

INTRODUCTION Operational amplifiers are widely used as basic building blocks in implementation of different kinds of analog applications such as amplifiers, summers, integrators, and differentiators. Other applications such as filters and oscillators are essential systems for electronic circuits. It works well for low-frequency applications. Op Amp circuits are difficult to design at higher frequency range, due to their frequency limitations. At high frequencies, operational trans-conductance amplifiers (OTAs) are considered to be promising to replace Op Amps as the building blocks for electronic circuits. Theories of using OTAs as the building blocks for analog applications have been well developed.[1] As the gate length of CMOS devices were scaled down to one micron, radio

frequency range applications over gigahertz range has become possible.[2,3] OTAs are also developed in nanometer era to maintain high performance of system in which they are used. Recently, CMOS OTAs are developed in three trends- high frequency, high linearity and low power. OTAs are developed in CMOS technologies due to the unique properties as:  Ease to implement a trans conductor because MOSFETs are voltagecontrolled current devices.  High cut-off frequency.  Well commercialized and low-cost processes.

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International Journal of VLSI Design and Technology Vol. 2: Issue 1

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Conjunction of Spin – RAM Technology in FPGA Circuits Shubham Rastogi*, Monika Kathuria, Pankaj Sharma Moradabad Institute of Technology, Moradabad, Uttar Pradesh, India

Abstract A FPGA (Field Programmable Gate Array) is a programmable logic device (PLD) with higher density and capable of implementing different functions in a short period of time. Basically, it is a 2-d array of logic blocks and flip flops with programmable interconnections. Earlier memories used with FPGA were volatile, slow re-programmable and had limited writing cycles. With conjunction of the Spin-RAM technology with the conventional FPGA circuits it enhances writing and reading speed, offers large retention time and provides nonvolatility. Spin-RAM usually consists of two thin films of altering ferromagnetic materials and a non-magnetic layer spacer. It offers Dynamic reconfiguration in FPGA circuits. SpinRAM based flip-flop can replace registers in SOC (System on Chip) and can be used in the field of aviation and space due to security. Keywords: Cache memory, dynamic reconfiguration, system on chip

INTRODUCTION Designing the memory hierarchy for microprocessors has grown significantly more challenging the past decade. The conventional approach has use SRAM for caches, DRAM for main memory and rotating disks, Flash memory for storage. Each of these technologies has scalability limitations with regard to power consumption, performance and speed or reliability. Hence there comes an alternative approach to use a universal memory. It is a single universal memory that embodies all ideal properties of each layer high performance, high density, high endurance, low power consumption and storage class nonvolatility. Spin transfer torque RAM (STT-RAM) built using magnetic tunnel junction (MTJ) is a promising “universal memory” candidate.[1-5] Most FPGA are static RAM (SRAM) based and thus they are volatile, in other

words each time power is off, the FPGA configuration is lost and hence has to setup at each power up. To avoid this drawback a non-volatile programmable read only memory (PROM) module is required. This not decreases the start-up time but also reduces the device cost and the required PCB area.[1] The small access time of the SRAM makes it popular in the FPGA industry. Nonetheless, its volatility and the need of an external non-volatile memory to store the conﬁguration data make it not suitable for nowadays embedded applications. The use of non-volatile memories such as MRAMs helps to overcome the drawbacks of classical SRAM-based FPGAs without signiﬁcant speed penalty. Besides its advantage that lies in power saving during

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International Journal of VLSI Design and Technology Vol. 2: Issue 1

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Model Order Reduction of Continuous Large Scale Systems: A Conglomerating Approach Ankit Sachan1*, Manish Kumar Sharma2, Deepak Parashar3 1

IIT, BHU Varanasi, Uttar Pradesh, India I.T.S. Engineering College, Greater Noida, Uttar Pradesh, India 3 B.S.A.C.E.T., Mathura, Uttar Pradesh, India

Abstract In this note, a method is presented for the order reduction of continuous approach for order reduction of complex discrete uncertain systems is proposed. Using Interval arithmetic Routh Stability arrays are formed to obtained numerator and denominator of reduced order model. The developed approach preserves the stability aspect of reduced system if higher order uncertain system is stable. A numerical example is included to illustrate the proposed algorithm along with the comparison with existing techniques. Keywords: factor division, interval system, inverse distance measure, Kharitonov’s polynomials, model reduction, pole-clustering method

INTRODUCTION The modelling of the physical system was done to define the characteristics of the model which helps to find out the size, physical behaviour, utility, etc. The required accuracy of the model largely depends on the purpose for which the model is intended. As VLSI technology advances, integrated circuits are designed for reduced sizes and with high performing ability which having consequences to interconnect with the effects that it have an increasing impact on many critical design criteria. Therefore, accurate modelling of the interconnected circuits has become very important.[1-5] A typical interconnect model usually involves thousands or even millions of components whose direct simulation can stretch the limit of computing resources. We have to reduces the complexity of the interconnected model for better understanding of the system which issues the topic i.e. reduction of the original model to an appropriate model with far lesser variables.[6,7] It is highly desirable that this

approximate model inherit many of the properties of the original system. Due to several advantages e.g. reduced computational effort in simulation, simplified understanding of system, simpler control laws etc. and model reduction has been ample area of research. Several methods have been proposed for reduction of continuous-time systems.[1,8,9] Among them, Padé approximation method has found to be very useful in theoretical physics research.[2,3] due to being computationally simple but the reducedorder model obtained using Padé approximation method often leads to be unstable even though the high-order system is stable. To overcome limitation, many improvements have been proposed[9] in literature. The order reduction of HOISs has also attracted researchers since the pioneering work by Kharitonov’s. Some methods have been presented for order

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International Journal of VLSI Design and Technology Vol. 2: Issue 1

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Analysis of Device Parameters Variation on SRAM Cell for High Performance Memory Design Farhan Aziz*, Vishal Lal Goswami, Ashutosh Dubey, Ranjeet Singh Department of Electronics and Communication Engineering, BSA College of Engineering and Technology, Mathura, Uttar Pradesh, India

Abstract As silicon industry is moving towards the end of the technology roadmap, controlling the variation in device parameters during fabrication is posing a great challenge. The variations in process parameters such as the channel length, width, oxide thickness, dopant-placement in a channel result in a large variation in threshold voltage. This paper investigates the impact of process variation on design metrics of Static Random Access Memory (SRAM) cell, which is used for process-tolerant cache architecture suitable for high-performance memory design. The six-transistor (6T) and seven-transistor (7T) SRAM cells have been used to analyze and evaluate the impact of process variation at 32nm technology. The 7T SRAM bitcell has 60% improvement in SNM at the cost of 11.1% area penalty, 30.7× hold power penalty, 16.7% read delay penalty and 1.2× variability penalty. This shows that the 6T SRAM cell is more robust and consumes less power than the 7T cell. Keywords: hold power, random dopant fluctuation (RDF), line edge roughness (LER), static noise margin (SNM), read access time, static random access memory (SRAM)

INTRODUCTION Process imperfections due to subwavelength lithography and device level variations in small-geometry devices such as random dopant fluctuation (RDF) and line edge roughness (LER) are making the devices to exhibit large variations in their circuit parameters, particularly in the threshold voltage (Vt). Therefore, this paper analyses standard 6T and 7T SRAM bit cell in light of process, voltage and temperature (PVT) variations to verify their functionality and robustness. Due to aggressive scaling of device dimensions, random variations in process, supply voltage and temperature are posing a major challenge to the future high performance circuits and system design.[13] The microscopic variations in number and location of dopant atoms in the

channel region of the device induce deviations in device characteristics.[4-6] These fluctuations are more pronounced in minimum-geometry devices commonly used in area-constraint circuits such as SRAM cells.[7] The intrinsic fluctuations are independent of transistor location on a chip. The threshold voltage (Vt) mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin (SNM). The SNM model in[8] assumes identical device threshold voltages across all cell transistors, making it unsuitable for predicting the effects of threshold voltage mismatch between adjacent transistors within a cell. Therefore, designer will require reevaluation and analysis of static noise margin in scaled technologies to ensure stability of SRAM cell. The spread

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International Journal of VLSI Design and Technology Vol. 2: Issue 1

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FOG Computing: A Novel Perception to Minimize Attacks and Provide Security in Cloud Computing Environment Pooja*, Yashpal Singh*, Sonia Chaudhary Department of Computer Science and Engineering, Ganga Institute of Technology and Management, Kablana, Jhajjar, Haryana, India

Abstract Cloud is essentially a clusters of multiple faithful servers committed within a network. Cloud Computing is a network grounded atmosphere that emphases on distribution computations or assets. In cloud customers only recompense for what they consumption and have not to pay for local funds which they want such as storage or infrastructure. So this is the chief benefit of cloud computing and chief aim for achievement fame in today’s world. Also cloud computing is individual of the most stimulating skill unpaid to its skill to decrease cost related with computing while cumulative suppleness and scalability for computer procedures. But in cloud the chief problematic that happens is security and currently a day security and privacy together are chief apprehension that desirable to be measured. To overwhelm the problematic of security we are familiarizing the new method which is called as Fog Computing. Fog Computing is not a standby of cloud it is just spreads the cloud computing by provided that security in the cloud environment. With Fog services we are capable to improve the cloud knowledge by dividing user’s data that essential to live on the edge. The chief purpose of fog computing is to place the data close to the end user. Keywords: cloud computing, encryption, fog services

INTRODUCTION We have our own confidential documents in the cloud. These files do not have much security. So, hacker in today’s worlds the small as well as big–big organizations are using cloud computing technology to protect their data and to use the cloud resources as and when they need. Cloud is a subscription based service. Cloud computing is a shared pool of resources. The way of use computers and store our personal and business information can arise new data security challenges. Encryption mechanisms not shield the data in the cloud from unapproved admission. As we differentiate that the outdated database system are characteristically positioned in secure environment where

user can admission the scheme individual complete a limited network or internet. With the fast development of W.W.W user can access almost any database for which they have correct admission right from anyplace in the world. By registering into cloud the use to get the resources from cloud providers and the organization can access their data from anywhere and at any time when they need. But this comfortness comes with certain type of risk like security and privacy. To overcome by this problem we are using a new technique called as fog computing. Fog computing provides security in cloud environment in a greater extend to get the benefit of this technique a user need to get registered with the fog. once the user is ready by

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Review on Raspberry Pi Technology Amandeep Kaur, Yashpal Singh*, Sonia Chaudhary Department of Computer Science and Engineering, Ganga Institute of Technology and Management, Kablana, Jhajjar, Haryana, India

Abstract Many organizations are working hard to secure We use different types of technologies but the Raspberry pi technology established a new platform by incorporating with the latest technology software to work with them in a user friendly environment and also working for future technologies and also developments regarding Raspberry pi 2 technology. These proven technologies can meet the needs of the most demanding of environments while their respective focus on manageability has automated many tasks and simplified administrative functions through easy-to-use interfaces developed through years of customer feedback. And at the end of the document we can conclude that soon we can save secrecy involved in message passing from the dangerous clutches of message hackers. Keywords: architecture of raspberry pi, characteristics of Raspberry, current app in use, history of raspberry pi

INTRODUCTION The RaspberryPi is a sequence of credit card-sized single-board processers advanced in the UK by the Raspberry Pi Foundation with the objective of encouraging the training of basic computer science in schools and third world countries. The innovative Raspberry Pi and Raspberry Pi 2 are contrived in numerous board conformations through licensed industrial arrangements with Newark element14 (Premier Farnell), RS Components and Egoman. These corporations sell the Raspberry Pi connected. Egoman produces a kind for dissemination exclusively in Taiwan, which can be illustrious from other by their red colouring and lack of FCC/CE marks. The hardware is the same across all producers. The original Raspberry Pi is grounded on the Broadcom BCM2835 syst em on a chip (SoC)which comprises

an ARM1176JZF-S 700 MHz processor, Video Core IV GPU, and was initially shipped with 256 megabytes of RAM, later advanced (models B and B+) to 512 MB. The system has Secure Digital (SD) (models A and B) or MicroSD (models A+ and B+) sockets for boot media and obstinate storage. In 2014, the Raspberry Pi Foundation propelled the Compute Module, which packages a BCM2835 with 512 MB RAM and an e MMC flash chip into a component for use as a part of entrenched systems. The Foundation provides Debian and Arch Linux ARM disseminations for download. Tools are accessible for Python as the chief programming language, with sustenance for BBC BASIC (via the RISC OS image or the Brandy Basic clone for Linux),C, C++, Java, Perl and Ruby. As of 8 June 2015, about 5 to 6 million Raspberry Pi have been shifted. While previously the wildest selling British

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Applied Mechanics

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International Journal of

VLSI Design and Technology Jan – June 2016

IJVDT

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Material Sciences and Engineering

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Biotechnology

Chemistry

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Physics « International Journal of Solid State Materials « International Journal of Optical Sciences